Adder circuits are fundamental building blocks in processors. The ripple carry adder is the simplest implementation but has increasing delay as the number of bits increases due to carry propagation. Faster adders like carry lookahead and carry select optimize the carry logic to reduce delay. Multipliers perform multiplication through generating and accumulating partial products using adders. Techniques like Booth recoding can reduce the number of partial products and additions to improve speed and reduce area of multiplier circuits.

1. ARITHMETIC CIRCUITS IN
CMOS VLSI

2. ADDER
• Adder is the most common part of the processor.
• It is the speed limiting element
• Optimization of the adder can be done at either
circuit level or logic level.
• Logic level optimizations – rearrange the Boolean
equations to obtain a faster or a smaller circuit
• Eg: carry look ahead adder

3. ADDER(contd..)
• Circuit optimizations- manipulate transistor
sizes and circuit topology to optimize the
speed.

4. RIPPLE CARRY ADDER
• Generate: the carry will be generated
Cout=1
G=1, when A=B=1
• Propagate: The incoming carry will be
propagated
Cout=Cin
P=1, When A or B =1

5. • Delete: The carry will be deleted
Cout=0
D=1, when A =B=0
• Delay equation: tadder= (N-1) tcarry+ tsum
• Worst case delay: when a carry generated at the
LSB position propagates all the way to the MSB
position
• Delay is proportional to the number of words N
RIPPLE CARRY ADDER(contd..)

6. • If N increases, delay also increases
• For designing fast adders. Carry circuits should
be optimized more than the sum circuit,
because carry has more impact on the delay.
• Inverting property of full adder: states that
“inverting all inputs of a full adder results in
inverting outputs”. This is used for optimizing
the speed of RCA
RIPPLE CARRY ADDER(contd..)

7. CARRY BYPASS ADDER
• Also known as carry skip adder.
• The carry is propagated either through the
bypass path or a carry is generated
somewhere in the chain.
• RCA is usually faster for small values of N than
compared to bypass adder.

8. LINEAR CARRY SELECT ADDER
• In RCA every full adder has to wait for the incoming
carry before an out going carry can be generated.
• In this method, both possible values of carry input
are anticipated and evaluate the result for both
possibilities in advance
• Once real value of incoming carry is known, the
correct result is selected with a mux stage
• Propagation delay is linearly proportional to N.

9. CARRY LOOK AHEAD ADDER
• The area of implementation grows
progressively with N. This adder is useful only
for small values of N (<=4)
• The addition time is independent of the no.of
bits.
• When N increases-> fan out increases-> which
makes circuit slow.

10. MULTIPLIERS
• Multipliers are complex adder arrays.
• To perform multiplication use single two-input
adder
• For input that are M and N bits wide, the
multiplication takes M cycles using an N-bit adder.
• Each partial product is generated by multiplying the
multiplicand with a bit of the multiplier.

11. • Array multiplier has following 3 functions:
->partial product generation
-> partial product accumulation
-> final addition
• Booth recoding techniques- reduces the
number of partial products to at most one half.
This means no. of additions is reduced. Circuit
speed improves. Area is reduced.
MULTIPLIERS (contd..)