This document discusses the integration of HDT's signal integrity and EMC simulation tools with Zuken Redac's PCB design tools. It summarizes the need for such integrated tools due to increasing circuit speeds and densities exacerbating signal and power integrity issues. It outlines HDT's tool suite including PRESTO for post-layout simulation and EMIR for EMC analysis. The benefits of integrating these tools directly into Zuken Redac's design flow are discussed, such as automatically generating simulations from the layout. The goals of the partnership between the two companies is to provide a complete concurrent engineering solution.

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Signal Integrity & EMC synthesis

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Ancient modeling

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…. and realization

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HDT
HIGH DESIGN TECHNOLOGY
 The company
 The demand
 The concept
 The product line
 The differentiators
 The project

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THE COMPANY
 Founded in 1990 to develop and
market high-performance EDA tools
 Focused on:
– signal integrity
– hardware modeling
– design & validation of digital systems
– EMC/EMI issue

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The Technical Need
20 MHz
100 MHz
0
20
40
60
80
100
120
1989 1992 1993 1994 1995 1996 1997
80286
80386
80386
80486
80486
80486
Pentium
Pentium
MHZ
Today
 You know the business trends
– Smaller
– Better
– Cheaper
– Sooner
 You know the law of OHM
– Interconnect = Gate Delay
– Faster circuits = Parasitic effects
– Miniaturization = Denser circuits
– Lower voltages = Noise sensitivity

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The Legal Need
Starting January 1996
the European guideline on Electro Magnetic
Compatibility is explicit:
If the product does not conform…
….it cannot go to the market !

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THE CONCEPT
PRESTO
123456
789
FILE_TYPE=HDT_PLIB;
TIME=Thu Dec 10 10:45:33 1992
COMPONENT=AC04, 74AC04;
FAMILY=FACT;
PACKAGE=DEFAULT, DIP14, SOIC14;
FACTORY=DEFAULT;
TYPE=IC;
NPINS=14;
BEGIN_PIN
FACT_DR24_P=2,4,6,8,10,12;
FACT_RC_P=1,3,5,9,11,13;
FACT_GND_P=7;
FACT_VCC_P=14;
END_PIN;
BEGIN_FUNCTION
DRIVER=2,4,6,8,10,12;
RECEIVER=1,3,5,9,11,13;
POWER_FACT=14;
GROUND_FACT=7;
END_FUNCTION;
END.
Driver
Receiver
SSN report
Compliance
analysis
report
Overshoots
undershoots
rise and fall
time
report
398.00 399.00 400.00 401.00 402.00 403.00 404.00404.40
TIME[nS]
-2.00 V
-1.75 V
-1.50 V
-1.25 V
-1.00 V
-0.75 V
-0.50 V
V(116)
70.00 80.00 90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00
-5.00V
-4.00V
-3.00V
-2.00V
-1.00V
0.00V
1.00V
2.00V
3.00V
4.00V
5.00V
6.00V
7.00V
8.00V

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The HDT line:
“The Backbone”
 SPRINT
– Simulation Program of Response of
Integrated Network Transients
 SIGHTS
– Standard Interface for Graphic
Handling of Transient Signals
 Mod-env
 Modeling environment

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The HDT line:
“Signal Integrity”
 PRESTO
– Post-layout Rapid Exhaustive Simulation
and Test of Operation
 TEMPO
– Tool for Electrical Multiple Performance
Optimization
 TEMA
– Transverse Electro Magnetic Analysis
 SSN
– Simultaneous Switching Noise

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The HDT line:
“EMC”
 PRESTO_CNT
– Post-layout simulation to evaluate
Conducted Noise Transmission
 EMIR
– EMIssion Radiated
 EMIR-Cable
– Cable attached PCB emission &
conducted noise transmission analysis

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The differentiators:
“Fast”
Remember this:
approx 0.3 secs for single net simulation!
• Comparison between
simulation and
measures
of high-speed
multiboard
system (155Mbit/s)
• 50000 elements
• 32 simultaneous input
sequence
• 16000 time points
• 60 min. simulation time
(HP 750)

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The differentiators:
“User friendly”
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TIME[nS]
-4.00V
-2.00V
0.00V
2.00V
4.00V
6.00V
8.00V
#U4_1
#IC23_4
lower and upper masks
mask violations
Net CLK1 upper and lower masks v iolation Error f igure: 8.12
Net DAT1 upper and lower masks v iolation Error f igure: 6.01
Net ADD1 lower mask v iolation Error f igure: 0.21
Net ADD2 upper mask v iolation Error f igure: 0.11
Net ADD3 upper mask v iolation Error f igure: 0.11
Net RD no v iolation Error f igure: -
Net RDN no v iolation Error f igure: -
70.00 80.00 100.00 120.00 140.00 160.00 180.00
TIME[nS]
-4V
-2V
0V
2V
4V
6V
8V
Eye-diagram opening
Jitter

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10 100 1 10
320
10
0
10
20
30
40
50
60
70
80
Frequency in MHz
|E| in dBV/m
EN 55022
Emissions from PCB +
cable: measurement
Emissions from PCB +
cable: simulation
Emissions from PCB:
simulation
Emissions from the
cable: simulation
The differentiators:
“Advanced”

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Zuken Redac’s and HDT’s
statements of intention
Mr Keiichi Watanabe
Zuken-Redac’s President and CEO
.. we are fully aware of the
challenges faced by designers
of high speed circuits
.. the amalgamation of high-
speed simulation with
powerful auto routers is truly
the concept of concurrent
engineering
Mr. Fernando Belforte
HDT’s President and General
Manager
.. to be successful two key
elements are required: an
excellent router and an
extremely fast analyzer
.. the technological leadership of
Zuken-Redac and HDT will
benefit he industry as a whole,
and the resulting product will
be a reference for the
profession

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VISULA & PRESTO
Actual features:
PRESTO Analysis from the Visula Layout Editor
• A menu item in the Visula Layout Editor
automatically generates the CAD output and calls
Presto with the extracted data.
Component value association
• A ‘VALUE’ attribute set in Visula , for passive
components, is automatically passed to Presto.
Simulation of selected NETS
• It is possible to simulate only on some nets selected
from the Visula layout editor.

17. Components model association ( from DB)
• A ‘MODEL’ attribute set in Hotstage for every
component is passed to SPRINT making easier the
simulation set up.
NetClass association
• A ‘CLASS’ attribute set in Hotstage for every nets
is passed to SPRINT.
Signal integrity evaluation at Schematic level
• Simulation takes place after the placement phase
and before the routing process to screen out
preliminary problems.
HOTSTAGE & SPRINT
Actual Features:

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Zuken Redac & HDT Integration
Today

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THE PROJECT
Specifications
Logical
Simulation
Routing of PCB
PCB Testing
What If Analysis
PRESTO - EMIR
EMC Compliance
Signal Integrity

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Zuken Redac & HDT Integration
Tomorrow …. and after Tomorrow

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State of art modeling