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How to design your own chip?
- 1. How to designyour own chip? LibreCores Free and Open Digital Hardware Philipp Wagner FrOSCon 2016
- 2. How to designyour own chip? 22016-08-20 The story of Ton Lear
- 3. How to designyour own chip? 32016-08-20 The story of Ton LearNot Real
- 4. How to designyour own chip? 42016-08-20 Digital Hardware Design Free and Open Source Silicon (FOSSi) maker open (source) hardware What's the difference?
- 5. How to designyour own chip? 52016-08-20 Design Entry: HDL
- 6. How to designyour own chip? 62016-08-20 The Digital Hardware Design Flow HDL Sources simulation 3rd -party libraries IP Cores design project
- 7. How to designyour own chip? 72016-08-20 Simulation
- 8. How to designyour own chip? 82016-08-20 The Digital Hardware Design Flow HDL Sources synthesis simulation 3rd -party libraries IP Cores FPGA implementation design project
- 9. How to designyour own chip? 92016-08-20 Chips? Image source: https://deliciousgf.wordpress.com/2012/04/29/gluten-free-and-vegan-veggie-chips/
- 10. How to designyour own chip? 102016-08-20 The Digital Hardware Design Flow HDL Sources synthesis simulation 3rd -party libraries IP Cores ASIC backend FPGA implementation design project
- 11. How to designyour own chip? 112016-08-20 Chips! image from https://pixabay.com/en/chips-potato-chips-unhealthy-thick-448746/, CC0 (public domain)
- 12. How to designyour own chip? 122016-08-20 FOSSi Reality Check 1 The Simulation Check
- 13. How to designyour own chip? 132016-08-20 Simulation: Required Ingredients ● code to simulate ● a simulator ● testing
- 14. How to designyour own chip? 142016-08-20 Write your code ● Choose from the incumbents – Verilog/SystemVerilog – VHDL ● or one of the new contenders – Bluespec SystemVerilog – Chisel (UC Berkely) – MyHDL
- 15. How to designyour own chip? 152016-08-20 Simulation ● The “big 3” commercial simulators – Incisive Enterprise Simulator/ NCSim (Cadence) – ModelSim (Mentor) – VCS (Synopsys) ● FOSS solutions – Icarus Verilog – GHDL – Verilator ● Add a good waveform viewer – gtkview
- 16. How to designyour own chip? 162016-08-20 Testing & Verification ● cocotb: Python-based test ● vunit: VHDL unit testing ● Open Source VHDL Verification Methodology (OS-VVM)
- 17. How to designyour own chip? 172016-08-20 “The Simulation Check”: Results ● Hobbyist-Accessibility-Score: 4/5 ● FOSS score: 4/5 ● Fun score: 2/5
- 18. How to designyour own chip? 182016-08-20 FOSSi Reality Check 2 The FPGA Check
- 19. How to designyour own chip? 192016-08-20 FPGA Design: Required Ingredients ● code to simulate ● a simulator ● testing ● a synthesis tool ● an implementation tool ● an FPGA board
- 20. How to designyour own chip? 202016-08-20 FPGA Synthesis ● Commercial – Synopsys Synplify – vendor tools (Xilinx, Altera, …) ● free alternatives – Verilog-to-Routing (VTR) – Yosys
- 21. How to designyour own chip? 212016-08-20 FPGA Implementation ● Mostly vendor tools – Xilinx ISE/Vivado, Altera Quartus, … ● free alternatives – IceStorm for Lattice iCE40 something to watch: Clifford @ FOSDEM 2016 https://archive.fosdem.org/2016/schedule/event/icestorm/
- 22. How to designyour own chip? 222016-08-20 FPGA Boards: student (< 100 $) DE0-Nano $79 22,320 cells Artix-7 35T $99 33,280 cells iCEstick $20 1280 cells All board pictures (c) by the manufacturers.
- 23. How to designyour own chip? 232016-08-20 FPGA Boards: amateur (~ 500 $) Nexys 4 DDR ZTEX 2.1x Altera DE2-115 All board pictures (c) by the manufacturers.
- 24. How to designyour own chip? 242016-08-20 FPGA Board: pro (> 1000 $) Xilinx KC705 Xilinx VC707 All board pictures (c) by the manufacturers. Altera Cyclone V SoC Development Kit
- 25. How to designyour own chip? 252016-08-20 “The FPGA Check”: Results ● Hobbyist-Accessibility-Score: 3/5 ● FOSS score: 2/5 ● Fun score: 4/5
- 26. How to designyour own chip? 262016-08-20 FOSSi Reality Check 3 The ASIC Check
- 27. How to designyour own chip? 272016-08-20 ASIC Production: Required Ingredients ● code to simulate ● a simulator ● a synthesis tool ● really good testing & verification ● a design kit ● an implementation tool ● money
- 28. How to designyour own chip? 282016-08-20 The Design Kit ● standard cell libraries, design rules, electrical parameters, ... ● get it from the foundry ● bad: requires pretty tough NDA ● good: it's usually for free (again, as in beer)
- 29. How to designyour own chip? 292016-08-20 ASIC Implementation ● Commercial options – Synopsys Design Compiler – Cadence Encounter Toolset ● FOSS options – qflow – Coriolis2
- 30. How to designyour own chip? 302016-08-20 Got Money? [[user:]]viaWikimediaCommons,CCBY-SA
- 31. How to designyour own chip? 312016-08-20 Need Money ● Multi-Project Wafer – available from multiple vendors, e.g. Europractice – example ● 50 pcs Globalfoundries 40 nm ● 4 750 €/mm² (at least 9 mm² = 42 750 €) + packaging, etc. ● up to 1500 KGates/mm² – cheaper in older technologies (65nm + up) ● eASIC – pre-characterized ASICs “configured” with one custom layer
- 32. How to designyour own chip? 322016-08-20 “The ASIC Check”: Results ● Hobbyist-Accessibility-Score: 0.1/5 ● FOSS score: 1/5 ● Fun score: 1-5/5 ● Satisfaction score: 10/5 let's do it anyways?
- 33. How to designyour own chip? 332016-08-20 Don't celebrate alone. PicturebyWeI-chiehChiu(flickr),CCBY-SA
- 34. How to designyour own chip? 342016-08-20 Join the party! The bachelor party. Signed Louis Wain. Oil on canvas, 29.5 x 60 cm (public domain, via Wikimedia Commons)
- 35. How to designyour own chip? 352016-08-20 FOSSi Reality Check 4 The Community Check
- 36. How to designyour own chip? 362016-08-20 Required ingredients ● Let others participate ● Build on existing work ● Learn, teach and exchange ideas
- 37. How to designyour own chip? 372016-08-20 How to live together? photobyPrskavka(WikimediaCommons),publicdomain
- 38. How to designyour own chip? 382016-08-20 Choose a license ● Permissive ● Weak Copyleft ● Strong Copyleft
- 39. How to designyour own chip? 392016-08-20 Licensing: Permissive ● without patent clause – MIT and BSD widely used – example project: RISC V ● with patent clause – new: SolderPad License by Andrew Katz
- 40. How to designyour own chip? 402016-08-20 Licensing: Weak Copyleft ● File-based copyleft – OHDL: Julius Baxter for mor1kx, based on MPLv2 ● library copyleft – LGPL ● commonly used on opencores.org ● what's “linking” in a hardware context?
- 41. How to designyour own chip? 412016-08-20 Licensing: Strong Copyleft ● GPL – GPLv3 uses “hardware-friendly” language ● lesson learned from open sourcing SPARC – example user: Gaisler LEON3 (GPLv2+) – implications not fully understood ● ASIC (design kit)? ● FPGA (built-in primitives)?
- 42. How to designyour own chip? 422016-08-20 OpenCores.org photobyAndreGlechikoff(Flickr),CCBY-SA
- 43. How to designyour own chip? 432016-08-20 Community hub needed ● publish your work ● find code to re-use ● learn, teach, inspire
- 44. How to designyour own chip? 442016-08-20 Introducing LibreCores
- 45. How to designyour own chip? 452016-08-20 LibreCores Goals ● Documentation – How to get started? – Best practices – Success stories ● News & Discussion – Planet LibreCores ● Project repository – a directory of FOSSi projects – with quality indicators
- 46. How to designyour own chip? 462016-08-20 LibreCores: Where are we today? ● Documentation – How to get started? – Best practices – Success stories ● News & Discussion – Planet LibreCores ● Project repository – a directory of FOSSi projects – with quality indicators First content online online! to be released in October!
- 47. How to designyour own chip? 472016-08-20 Who's behind all that? ● OpenRISC community ● Group formed ~2 years ago ● First plans presented at ORCONF 2015 at CERN ● since end of 2015: FOSSi Foundation, CiC (UK) to provide shared legal entity
- 48. How to designyour own chip? 482016-08-20 So: How to design your own chip? ● join an existing project: OpTiMSoC, lowrisc, … ● fire up your editor: most tools are free (as in beer) ● FPGA designs are within reach ● ASICs only for some of us
- 49. How to designyour own chip? 492016-08-20 Conference Announcement ● October 7 – 9 ● University of Bologna, in Bologna, Italy ● No admission fee (but please register) visit www.orconf.org for more info & registration
- 50. me Philipp Wagner mail@philipp-wagner.com www.philipp-wagner.com let's talk! FOSSiFoundation discussion@lists.librecores.org www.fossi-foundation.org #librecores on freenode You can freely remix this presentation under the terms of the Creative Commons BY-SA 4.0 license.