VLSI IEEE 2018 Project Titles

1. Project Code
VLSI18NXT01
Systematic Design of an Approximate Adder: The Optimized
Adder
VLSI18NXT02 A Simple Yet Efficient
VLSI18NXT03
Low-Complexity VLSI Design of Large Integer
Encryption
VLSI18NXT04 Approximate Hybrid High Radix Encoding for
VLSI18NXT05 An Efficient Fault-Tolerance Design for Integer Parallel
VLSI18NXT06
Sense-Amplifier-Based Flip
Voltage Operation
VLSI18NXT07 A Performance Degradation Tolerable Cache Design by
VLSI18NXT08 FIR Filter Realization via Deferred End
VLSI18NXT09 Modular Design of High
VLSI18NXT10
An Energy-Efficient Network
Architecture
VLSI18NXT11 Towards a Dependable True Random Number
VLSI18NXT12
A Computationally Efficient Reconfigurable
Based on CSD Decoded
Algorithm
VLSI18NXT13 LFSR-Based Test Generation for Path Delay Faults
VLSI18NXT14
On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns
Recorded in Scan Chains
VLSI18NXT15 DR-scan: Dual-rail Asynchronous Scan DfT and ATPG
VLSI18NXT16 On-Chip Diagnosis of Generalized Delay Failures
VLSI18NXT17
Double MAC on a DSP: Boosting the Performance
on FPGAs
VLSI18NXT18
Secure Double Rate Registers as an RTL
Attacks
VLSI18NXT19 Low Overhead Warning Flip
VLSI IEEE PAPERS – 2018 PROJECT TITLES
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant
A Simple Yet Efficient Accuracy-Configurable Adder Design
Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic
Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers
Tolerance Design for Integer Parallel Matrix–Vector Multiplications
Based Flip-Flop With Transition Completion Detection for Low
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies
FIR Filter Realization via Deferred End-Around Carry Modular Addition
Modular Design of High-Efficiency Hardware Median Filter Architecture
Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder
Towards a Dependable True Random Number Generator With Self-Repair Capabilities
A Computationally Efficient Reconfigurable Constant Multiplication Architecture
CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination
Based Test Generation for Path Delay Faults
Test Methodology with All Deterministic Compressed Test Patterns
Recorded in Scan Chains
rail Asynchronous Scan DfT and ATPG
Chip Diagnosis of Generalized Delay Failures using Compact Fault Dictionaries
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis
Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring
Lower Part Constant-OR
Multipliers for Fully Homomorphic
Efficient Inexact Multipliers
Vector Multiplications
Completion Detection for Low-
Exploiting Memory Hierarchies
Carry Modular Addition
Median Filter Architecture
Reconfigurable Viterbi Decoder
Repair Capabilities
Constant Multiplication Architecture
Expression Elimination
Test Methodology with All Deterministic Compressed Test Patterns
using Compact Fault Dictionaries
of Convolutional Neural Networks
Countermeasure Against Power Analysis
Sharing for Timing Slack Monitoring

2. VLSI18NXT20 An Adaptive Mechanism for Designing
VLSI18NXT21 Toward Energy-Efficient Stochastic Circuits
VLSI18NXT22
On the Analysis and the Mitigation of Power Supply
Network Impedance
VLSI18NXT23
Design of Area-Efficient and Highly Reliable RHBD
Applications
VLSI18NXT24
A Flexible and Energy
Dedicated ISA and Accelerator
VLSI18NXT25 Low-Cost Lifting Architecture and Lossless
VLSI18NXT26 A Method to Detect Bit Flips
VLSI18NXT27
Fault Group Pattern Matching with Efficient Early Termination for High
Redundancy Analysis
VLSI18NXT28
Bitstream Fault Injections (BiFI)
FPGAs
VLSI18NXT29
Hardware/Software Co
Encryption Scheme
VLSI18NXT30
Efficient Protection of the
FPGAs
An Adaptive Mechanism for Designing Efficient Snoop Filters
Efficient Stochastic Circuits Using Parallel Sobol equences
On the Analysis and the Mitigation of Power Supply Noise and Power Distribution
Network Impedance Variation for Scan-Based Delay Testing Techniques
Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace
A Flexible and Energy-Efficient Convolutional Neural Network celebration With
Dedicated ISA and Accelerator
Architecture and Lossless Implementation of Daubechies
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM
Fault Group Pattern Matching with Efficient Early Termination for High
Redundancy Analysis
Bitstream Fault Injections (BiFI) – Automated Fault Attacks against SRAM
Hardware/Software Co-Design of an Accelerator for FV Homomorphic
Using Karatsuba Algorithm.
Efficient Protection of the Register File in Soft-processors Implemented on Xilinx
equences
Noise and Power Distribution
Based Delay Testing Techniques
10T Memory Cell for Aerospace
celebration With
Implementation of Daubechies-8 Wavelets
Fault Group Pattern Matching with Efficient Early Termination for High-Speed
Automated Fault Attacks against SRAM-based
Homomorphic
processors Implemented on Xilinx