This document contains contact information for Innovative Technology Services and a list of 72 VLSI titles. It provides the address, phone numbers, and email/website for Innovative Technology Services in Chennai, India. It also encourages contacting them for more titles in various domains like NS2, Java, VLSI, MATLAB, Android, and .NET.

1. Innovative Technology Services +91 97 91 20 60 40
+91 99 44 43 00 65
Innovative Technology Services
762/625, PH Road, NSK Nagar,
Arumbakkam, Chennai - 106.
+91 44 420 12 180, +91 97 91 20 60 40, +91 99 44 43 00 65
info@itsexplore.com | support@itsexplore.com
www.itsexplore.com
VLSI-IEEE 2013 TITLES
ITS-VLSI13-01 A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High
PerformanceJoint Source Channel Codes
ITS-VLSI13-02 3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip
ITS-VLSI13-03 A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented
Memories
ITS-VLSI13-04 A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
ITS-VLSI13-05 A High-Speed Low-Complexity Modified FFT Processor for High Rate WPAN
Applications
ITS-VLSI13-06 A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless
Sensor Networks
ITS-VLSI13-07 A Meet-in-the-Middle Algorithm for Fast Synthesis of Depth-Optimal Quantum
Circuits
ITS-VLSI13-08 AC-Plus Scan Methodology for Small Delay Testing and Characterization
ITS-VLSI13-09 Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant
Deflection Router
ITS-VLSI13-10 All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty
Cycle
ITS-VLSI13-11 An Analytical Latency Model for Networks-on-Chip
ITS-VLSI13-12 An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under
Write-Through Policy
ITS-VLSI13-13 An On-Chip Network Fabric Supporting Coarse-Grained Processor Array

2. Innovative Technology Services +91 97 91 20 60 40
+91 99 44 43 00 65
ITS-VLSI13-14 An Ultrasynchronization Checking Method With Trace-Driven Simulation for
Fast and Accurate MPSoC Virtual Platform Simulation
ITS-VLSI13-15 Application Space Exploration of a Heterogeneous Run-Time Configurable
Digital Signal Processor
ITS-VLSI13-16 Architecture for Real-Time Nonparametric Probability Density Function
Estimation
ITS-VLSI13-17 Built-In Generation of Functional Broadside Tests Using a Fixed Hardware
Structure
ITS-VLSI13-18 A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy
ITS-VLSI13-19 Checkpointing for Virtual Platforms and SystemC-TLM
ITS-VLSI13-20 Circuit-Level Timing Error Tolerance forLow-Power DSP Filters and Transforms
ITS-VLSI13-21 Combined Architecture/Algorithm Approach to Fast FPGA Routing
ITS-VLSI13-22 CORDIC Designs for Fixed Angle of Rotation
ITS-VLSI13-23 Design and Implementation of an On-Chip Permutation Network for
Multiprocessor System-On-Chip
ITS-VLSI13-24 Design of Digit-Serial FIR Filters: Algorithms,Architectures, and a CAD Tool
ITS-VLSI13-25 Efficient Implementation of Reconfigurable Warped Digital Filters With Variable
Low-Pass, High-Pass,Bandpass, and Bandstop Responses
ITS-VLSI13-26 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density
Parity Check (EG-LDPC) Codes
ITS-VLSI13-27 Exploration and Optimization of 3-D Integrated DRAM Subsystems
ITS-VLSI13-28 Glitch-Free NAND-Based Digitally Controlled Delay-Lines
ITS-VLSI13-29 Improved Trace Buffer Observation via Selective Data Capture Using 2-D
Compaction for Post-Silicon Debug
ITS-VLSI13-30 IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
ITS-VLSI13-31 Joint Decoding of LDPC Code and Phase Factors for OFDM Systems With PTS
PAPR Reduction
ITS-VLSI13-32 Latch-Based Performance Optimization for Field-Programmable Gate Arrays

3. Innovative Technology Services +91 97 91 20 60 40
+91 99 44 43 00 65
ITS-VLSI13-33 MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
ITS-VLSI13-34 Mining Hardware Assertions With Guidance From Static Analysis
ITS-VLSI13-35 NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing with Bounded-
Length Maze Routing
ITS-VLSI13-36 Novel MIMO Detection Algorithm for High-Order Constellations in the Complex
Domain
ITS-VLSI13-37 On the Fixed-Point Accuracy Analysis and Optimization of Polynomial
Specifications
ITS-VLSI13-38 Pipelined Radix- Feedforward FFT Architectures
ITS-VLSI13-39 Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM
Architecture Using TSV
ITS-VLSI13-40 Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-
Throughput MIMO-OFDM Systems
ITS-VLSI13-41 Scalability Analysis of Memory Consistency Models in NoC-based Distributed
Shared Memory SoCs
ITS-VLSI13-42 Scaling Energy Per Operation via an Asynchronous Pipeline
ITS-VLSI13-43 Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on
FPGA Platform
ITS-VLSI13-44 Selective Flexibility:Creating Domain-Specific Reconfigurable Arrays
ITS-VLSI13-45 Self-Repairing Digital System With Unified Recovery Process Inspired by
Endocrine Cellular Communication
ITS-VLSI13-46 STBC-OFDM Downlink Baseband Receiver for Mobile WMAN
ITS-VLSI13-47 Techniques for Compensating Memory Errors in JPEG2000
ITS-VLSI13-48 Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
ITS-VLSI13-49 The LUT-SR Family of Uniform Random Number Generators for FPGA
Architectures
ITS-VLSI13-50 Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs
for Area and Speed

4. Innovative Technology Services +91 97 91 20 60 40
+91 99 44 43 00 65
ITS-VLSI13-51 A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High
Performance Joint Source Channel Codes
ITS-VLSI13-52 A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm
ITS-VLSI13-53 A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture
ITS-VLSI13-54 An Adaptive Subsystem Based Algorithm for Channel Equalization in a SIMO
System
ITS-VLSI13-55 Binary Discrete Cosine and Hartley Transforms Analysis
ITS-VLSI13-56 Computing Two-Pattern Test Cubes for Transition Path Delay Faults
ITS-VLSI13-57 Design of Hardware Function Evaluators Using Low-Overhead Nonuniform
Segmentation With Address Remapping
ITS-VLSI13-58 DS-CDMA Implementation With Iterative Multiple Access Interference
Cancellation
ITS-VLSI13-59 FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage
Area Network
ITS-VLSI13-60 Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple
Constant Multiplication/Accumulation
ITS-VLSI13-61 Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs
Using PolynomialFitting Measurements
ITS-VLSI13-62 One Analog STBC-DCSK Transmission Scheme not Requiring Channel State
Information
ITS-VLSI13-63 Reconfigurable Accelerator for the Word-Matching Stage of BLASTN
ITS-VLSI13-64 Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome
Computation
ITS-VLSI13-65 Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform
Generation
ITS-VLSI13-66 Scaling, Offset, and Balancing Techniques in FFT-Based BP Nonbinary LDPC
Decoders
ITS-VLSI13-67 Two-Rate Based Low-Complexity Variable Fractional-Delay FIR Filter
Structures

5. Innovative Technology Services +91 97 91 20 60 40
+91 99 44 43 00 65
ITS-VLSI13-68 VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters
Using Algebraic Integers
ITS-VLSI13-69 VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor
ITS-VLSI13-70 VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
ITS-VLSI13-71 An Efficient Interpolation-Based Chase BCH Decoder
ITS-VLSI13-72 An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly
Shuffled Decoding
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Innovative Technology Services
#762/625, PH Road, EVR Periyar Salai,
NSK Nagar, Arumbakkam, Chennai - 106
+91 44 420 12 180, +91 97 91 20 60 40, +91 99 44 43 00 65
info@itsexplore.com | support@itsexplore.com
www.itsexplore.com
Land Mark: Near to AMPA SKYWALK mall,
Opp. to CHENNAI FORD Car Showroom