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MSR PROJECTS
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VLSI PROJECTS-2017-18 PROJEC T CODE PROJECT TITLE VL01 A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving VL02 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL VL03 Split SAR ADCs Improved Linearity With Power and Speed Optimization VL04 Area-Delay Efficient Binary Adders in QCA VL05 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay VL06 Low-Power Programmable PRPG With TestCompression Capabilities VL07 Design and Analysis of Approximate Compressors for Multiplication VL08 high speed convolution and deconvolution algorithm VL09 Multi operand Redundant Adders on FPGAs . VL10 Design Of high Performance 64 Bit MAC Unit VL11 3 input xor or xnor gate VL12 A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications VL13 Fully Reused VLSI Architecture ofFM0Manchester Encoding Using SOLS VL14 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” VL15 high speed convolution and deconvolution algori VL16 Low-Power and Area-Efficient Shift Register Using Pulsed Latches VL17 A Decimal Binary Multi-operand Adder using a Fast Binary to Decimal Converter VL18 Implementation of High Speed Low Power Combinational and Sequential Circuits using Reversible logic VL19 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks VL20 Low-Cost High-Performance VLSI Architecture for

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Vlsi list b.tect -9581464142

  • 1. VLSI PROJECTS-2017-18 PROJEC T CODE PROJECT TITLE VL01 A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving VL02 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL VL03 Split SAR ADCs Improved Linearity With Power and Speed Optimization VL04 Area-Delay Efficient Binary Adders in QCA VL05 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay VL06 Low-Power Programmable PRPG With TestCompression Capabilities VL07 Design and Analysis of Approximate Compressors for Multiplication VL08 high speed convolution and deconvolution algorithm VL09 Multi operand Redundant Adders on FPGAs . VL10 Design Of high Performance 64 Bit MAC Unit VL11 3 input xor or xnor gate VL12 A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications VL13 Fully Reused VLSI Architecture ofFM0Manchester Encoding Using SOLS VL14 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” VL15 high speed convolution and deconvolution algori VL16 Low-Power and Area-Efficient Shift Register Using Pulsed Latches VL17 A Decimal Binary Multi-operand Adder using a Fast Binary to Decimal Converter VL18 Implementation of High Speed Low Power Combinational and Sequential Circuits using Reversible logic VL19 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks VL20 Low-Cost High-Performance VLSI Architecture for