1. NITHIN S. PODUVAL
4302 College Main APT 353, Bryan, TX-77801, PH: (214)-436-7246,Email:nithinpoduval@tamu.edu
Objective: Looking for full time opportunities in Analog and Mixed Signal Design
EDUCATION
Texas A&M University, College Station, Expected Graduation Dec 2015
Master of Science in Electrical Engineering (Thesis) GPA:4.0/4.0
Advised by Dr. Jose Silva-Martinez
University of Texas at Dallas, Richardson, Texas, USA August 2013-May 2014
Birla Institute of Technology and Sciences (BITS), Pilani, India May 2013
Bachelor of Engineering
RELEVANT COURSEWORK
Analog Integrated Circuit Design (ECEN 474), VLSI Design, Digital Circuits, High Speed Links Circuits and Systems, Low Noise
Electronic Design, RF Integrated Circuit Design, Digital Systems,
EXPERIENCE
Freescale Semiconductor, Austin, TX
Analog Design Engineering Intern, Low Power Microcontrollers Group (June2015-Aug 2015)
-Design and characterization of high speed analog circuits for regulating supply variations
ACADEMIC PROJECTS
Optimization of class-AB amplifier for non-linearity (Thesis) (Jazz 180nm technology)
• Designed a class AB amplifier with feedforward compensation using the Monticelli level shifter topology. The
class AB amplifier has fast settling (within 5ns) and is to be used as part of a switched capacitor amplifier.
• The amplifier’s linearity is to be optimized using a novel feedback circuit which will lower third harmonic
distortion.
• Characterization of non-linearity in the class AB output stage across PVT variations.
Fast Settling fully Differential Operational Amplifier (IBM 0.180 um technology)
• Designed a fully differential two stage Operational Amplifier with Common Mode Feedback which achieves the following
specifications- Gain of 50 dB, unity gain frequency 2GHz, phase margin of 600, , settling time time < 15ns, .
• Designed schematic , layout, extracted parasitics and compared schematic and post layout simulations.
High Speed Link Circuits and Systems (90 nm technology)
• Design of clocked comparators for 5 GHz operation in 90nm technology-Designed and compared performance of
Strong Arm Latch, CML Latch, Schinkel and Goll low voltage latches.
• Equalizer design – Designed TX FIR, CTLE(Continuos Time Linear Equalizer)and DFE (Decision Feedback
Equalizer)
• Designed LC VCO with center frequency 5GHz, tuning range- 1GHz.
DFE Compatible CDR at 10Gbps (90 nm technology)
• Designed a dual loop clock and data recovery system at half rate compatible with DFE equalization.
• Implemented PLL based frequency tracking loop and circuit blocks -quadrature LC VCO,Loop filter, Charge Pump,PFD, divider .
• Designed half rate Alexander phase detector, FSM accumulator and Phase Interpolator for the phase tracking loop .
• Equalized 10GBps channel data using 3-tap FIR, CTLE and 3-tap DFE before clock recovery.
• Jitter specifications compliant to SONET OC 192 standard were followed.
Digital VLSI Design: 16-Bit ALU design and implementation in IBM-130nm technology
• Implemented the ALU in behavioral Verilog supporting common ALU operations .
• Synthesized to obtain the netlist using Synopsis design compiler and verified functionality.
• Designed a standard cell library using basic logic cells, Multiplexer and Dflipflop using Cadence Virtuoso with
optimization for delay and area.. Extracted parasitics using Cadence Assura
• Characterized the library using Liberty NCX and mapped it to the synthesized Verilog netlist. Automatic placement and
routing was done using Cadence Encounter to obtain the final layout.
Digital Systems: Implemented a fully pipelined 5 stage MIPS processor using data forwarding , hazard detection and branch
prediction techniques in behavioral Verilog.
RF Integrated Circuit Design: Designed the layout of spiral inductor using IBM 130nm CMOS technology in Cadence Virtuoso.
Estimated the inductance and parasitic capacitances of the structure.