A 128 tap highly tunable cmos if finite impulse response filter for pulsed radar applications

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A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for
Pulsed Radar Applications
Abstract:
A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar
applications. To eliminate dispersion effects in the received waveform, a finite impulse
response (FIR) topology is proposed, which has a measured standard deviation of an in-
band group delay of 11 ns that is primarily dominated by the inherent, fully predictable
delay introduced by the sample-and-hold. The filter operates at an IF of 20 MHz, and is
tunable in BW from 1.5 to 15 MHz, which makes it optimal to be used with varying pulse
widths in the radar. Employing a total of 128 taps, the FIR filter provides greater than 50-
dB sharp attenuation in the stop band in order to minimize all out-of-band noise in the
low signal-to-noise received radar signal. Fabricated in a 0.18-µm silicon on insulator
CMOS process, the proposed filter consumes approximately 3.5mW/tap with a 1.8-V
supply. A 20-MHz two-tone measurement with 200-kHz tone separation shows IIP3
greater than 8.5dBm.
Software Implementation:
 TANNER EDA
Existing System:
Discrete time analog-domain finite impulse response (FIR) filters are used in a wide
range of applications, such as wireless local area network and cellular receivers,
frequency synthesizers, frequency down conversion, software defined radio, line
equalizers, and various other usages. However, FIR topologies have not been used in
radar systems to filter received radar pulses, where they could potentially be even more

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useful. In a pulsed-Doppler radar transceiver, RF pulses are transmitted and the Doppler-
shifted echo signal is returned and processed by the receiver.
Figure 1 : Block diagram of a pulsed-Doppler radar system with mono bit sub sampling. This paper presents the
design of the matched filter
An example of a pulsed-Doppler radar system (see Fig. 1) measures the range and
velocity of a target by detecting the transmit time and Doppler shift of a reflected RF-
modulated pulse. This transmitter consists of a pair of signal sources—a reference
oscillator operating at fIF and a voltage controlled oscillator (VCO) operating at the RF
frequency fVCO. The reference signal is up converted to fVCO– fIF and then pulse
modulated at a pulse repetition frequency (PRF) fPRF. A binary pseudorandom phase
code is employed to eliminate range ambiguities, while also reducing receiver sensitivity
to any in-band interferers that may be present. The pseudorandom pulsed RF signal is
radiated from the antenna, to the target, and then reflected back to the antenna with some
delay proportionate to the distance between the antenna and the target. The return signal
also undergoes a Doppler shift fD dependent on the target’s velocity. The received signal
at fVCO– fIF– fD is amplified, band pass filtered, and then down converted by an image-
reject mixer to fIF + fD. This IF signal is band pass filtered through a radar matched filter

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and then sampled once per pulse by a 1-b analog-to-digital converter (ADC) clocked at fS
= fPRF. The sampled signal is then processed by a digital signal processor (DSP) for
analysis to determine the range and velocity of the target.
In radar systems, the received signals are typically very weak, often much weaker than
the surrounding noise levels resulting in poor signal-to-noise (SNR) ratios. In designing
the matched filter, it would be beneficial to reduce the bandwidth (BW) as much as
possible in order to improve the SNR; however, filter BWs that are too small would not
be able to pass the received pulse without distortion of the pulse envelope in the time
domain. Therefore, the matched filter must be designed with a BW large enough to pass
the received pulse without causing extreme time-domain distortion, while being small
enough to maximize receiver SNR.
In current applications, the matched filter has typically been implemented with surface
acoustic wave and bulk-acoustic wave filters. The disadvantage of these filters is that
they are bulky, un-tunable, temperature sensitive, and must be off chip which is
expensive compared to on-chip solutions. Most previously reported FIR filters typically
fall into one of two categories. however, these are low-pass filters that can be adjusted in
BW by varying the clock rate. If the transfer functions were modified to a band pass
shape, adjusting the clock rate would not only change the filter BW but also have the
unfortunate effect of varying the filter’s center frequency.
Designed in a 0.18-μm silicon on insulator (SOI) CMOS process [37], this paper presents
an FIR band pass matched filter that has a 1.5–15-MHz tunable BW centered at 20 MHz.
The proposed FIR filter employs 128 taps realized by trans conductors, switches,
capacitors, and 34 non overlapping clock phases. The trans conductors are highly tunable,
which allows them to realize various filter BWs without altering the filter clock rate of 75
MHz. The entire FIR filter architecture dissipates approximately 450 mW and achieves

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attenuation greater than 50 dB at 5 MHz beyond the −3-dB frequency with a center
frequency of 20 MHz. Group delay variations are limited within approximately 10 ns.
Disadvantages:
 Less Efficiency
 More Area and power Consumption
 Less Number of TAP
Proposed System:
To meet the requirements of the radar receiver, the band pass filter needed to be tunable
in BW, while maintaining constant group delay. This is difficult to achieve with
conventional analog filters, so a discrete-time FIR topology was chosen. FIR filters are
process, voltage, and temperature (PVT) variation tolerant and can usually be scaled in
frequency by scaling the clock frequency. FIR filters can usually be implemented at a
much higher order than would be conceivable with Gm-C, active-RC, and switched-
capacitor techniques. The discrete time FIR filter can have a constant group delay, whose
value depends only on the clock rate and the number of taps.
Figure 2 : Proposed 128-tap programmable FIR band pass filter block diagram
The MATLAB digital filter toolbox was used to obtain the required order and
coefficients needed for each desired BW. The selected IF was 20 MHz with an overall
clock rate of 75 MHz. The BW was tunable from approximately 1.5 to 15 MHz. In order
to obtain the required attenuation of −50 dB at 5 MHz beyond the pass band, four

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identical 32-tap FIR filters were cascaded as illustrated in Fig. 2. Since the operation of
the FIR filter in this application is discrete time in nature, the input was first sampled
with a sample-and-hold (S/H) circuit. As will be seen during the discussion of the filter
architecture, the input to the FIR filter must remain constant during each clock cycle; thus
a time-interleaved S/H topology was used to provide a constant input throughout the
entire clock cycle.
Figure 3 : Thirty-two-tap FIR filter architecture system level including 32 tunable transconductor cells, 34
capacitors, switches, and a MUX.
Sample-and-Hold Design
The input to the FIR filter needs to be constant during each clock period, so that the
charge injected onto the capacitor is proportionate to the sampled input voltage. An S/H
circuit, which uses half the clock period to track the input signal, cannot be used. Fig. 4
shows the proposed S/H circuit (single-ended representation for simplicity), which is a
time interleaved approach. During one clock period, one of the two S/H circuits will track
the input, while the other holds a constant value. These operations will then switch for the

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next clock cycle, and so on. The S/H circuits each require two non overlapping clock
phases: one clock will turn the switches ON to sample the input voltage onto the
capacitor, while the second clock is used to put the capacitor in feedback around the
amplifier during the hold phase.
Figure 4 : S/H architecture.
Advantages:
 More Efficiency
 Less Area and power Consumption
 Number of TAP will increased
References:
[1] D. Jakonis, J. Folkesson, P. Eriksson, and C. Svensson, ―A 2.4-GHz RF sampling receiver front-end
in 0.18 μm CMOS,‖ IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1265–1277, Jun. 2005.
[2] T. Sano, T. Maruyama, I. Yasui, H. Sato, and T. Shimizu, ―A 1.8 mm2, 11 mA, 23.2 dB-NF,
discrete-time filter for GSM/WCDMA/WLAN using retiming technique,‖ in Proc. IEEE Custom Integr.
Circuits Conf. (CICC), Sep. 2007, pp. 703–706.
[3] D. Senderowicz et al., ―A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular
telephony using recycling integrator correlators,‖ in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.
Tech. Papers, Feb. 2000, pp. 354–355.

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[4] M.-F. Huang, ―A discrete-time charge-domain filter with bandwidth calibration for LTE
application,‖ in Proc. IEEE Custom Integr. Circuit Conf., Sep. 2011, pp. 1–4.
[5] D. Ahn and S. Hong, ―A low cost analog FIR channel select filter for wireless receiver,‖ in Proc.
IEEE Radio Wireless Symp., Jan. 2011, pp. 211–214.
[6] M.-F. Huang and L.-F. Chen, ―A programmable-bandwidth front-end with clock interleaving down-
conversion filters,‖ in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2008, pp. 349–352.
[7] M.-F. Huang, ―A quadrature charge-domain filter with an extra in-band filtering for RF receivers,‖ in
Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), May 2010, pp. 31–34.
[8] M.-F. Huang, L.-F. Chen, and T.-L. Chiu, ―A quadrature charge-domain filter with frequency down-
conversion and filtering for RF receivers,‖ in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC),
Jun. 2009, pp. 547–550.
[9] C. Park, J. Yoon, and B. Kim, ―Non-decimation FIR filter for digital RF sampling receiver with
wideband operation capability,‖ in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2009, pp. 487–
490.
[10] H. Repo and T. Rahkonen, ―Programmable switched capacitor 4-tap FIR filter,‖ in Proc. Eur.
Solid-State Circuits Conf. (ESSCIRC), Sep. 2003, pp. 445–448.
[11] S.-P. U, R.-P. Martins, and J. E. Franca, ―A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter
with 320-MS/s output for DDFS system in 0.35-μm CMOS,‖ IEEE J. Solid-State Circuits, vol. 39, no. 1,
pp. 87–99, Jan. 2004.
[12] S. Lindfors, A. Parssinen, and K. A. I. Halonen, ―A 3-V 230-MHz CMOS decimation subsampler,‖
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 3, pp. 105–117, Mar. 2003.
[13] S. Karvonen, T. A. D. Riley, and J. Kostamovaara, ―A CMOS quadrature charge-domain sampling
circuit with 66-dB SFDR up to 100 MHz,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp.
292–304, Feb. 2005.

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