A reconfigurable ldpc decoder optimized applications

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A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications
Abstract:
This paper presents a high data-rate low-density parity-check (LDPC) decoder, suitable
for the 802.11n/ac (WiFi) standard. The innovative features of the proposed decoder
relate to the decoding algorithms and the interconnection between the processing
elements. The reduction of the hardware complexity of decoders based on the min-sum
(MS) algorithms comes at the cost of performance degradation, especially at high-noise
regions. We introduce more accurate approximations of the log sum-product algorithm
that also operate well for low signal-to noise ratio values. Telecommunication standards,
including WiFi, support more than one quasi-cyclic LDPC codes of different
characteristics, such as codeword length and code rate. A proposed design technique
derives networks, capable of supporting a variety of codes and efficiently realizing
connectivity between a variable number of processing units, with a relatively small
hardware overhead over the single-code case. As a demonstration of the proposed
technique, we implemented a reconfigurable network based on barrel rotators, suitable
for LDPC decoders compatible with WiFi standard. Our approach achieves low
complexity and high clock frequency, compared with related prior works. A 90-nm
application-specified integrated circuit implementation of the proposed high-parallel
WiFi decoder occupies 4.88 mm2 and achieves an information throughput rate of 4.5 G
bit/s at a clock frequency of 555 MHz.
Software Implementation:
 Modelsim
 Xilinx 14.2
Existing System:

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LOW-DENSITY parity-check (LDPC) codes are linear block error-correction codes,
defined by a sparse parity check matrix (PCM). In recent years, they have received
increased attention, mainly due to their excellent error correction capabilities, the
availability of iterative decoding schemes, and their inherent parallelism, which make
LDPC decoders suitable for hardware implementation. The flexibility in selecting the
various code parameters facilitates their use in a variety of applications. A bipartite
Tanner graph, which consists of two sets of nodes, is a widely used way to represent a
PCM H. Each row of H corresponds to a parity-check equation, graphically represented
as a check node of the Tanner graph, while each column of H corresponds to a codeword
bit, represented as a variable node. An ace in H indicates a connection between the
corresponding variable and check nodes of the Tanner graph. Message-passing (MP)
algorithms for decoding LDPC codes operate by iteratively exchanging information along
the edges of the Tanner graph, between connected variable and check nodes. There are a
variety of MP decoding algorithms, such as the sum-product (SP), log-SP, and min-sum
(MS) algorithm. This paper presents an efficient LDPC decoding architecture for
802.11n/ac applications. The following innovative features are incorporated into the
introduced LDPC decoder.
1) Modifications of the MS algorithm improve the decoding performance of the WiFi
LDPC decoder. Optimal MS correction factors have been defined, taking into
consideration the quantization effects in hardware.
2) A systematic construction method derives a network that is able to rotate any set A of
n input messages, where the number n of messages contained in the set is selectable from
among any set D of d values, D = {z0,z1,...,zd−1}, where 1 < z0 < z1 < ... < zd−1. 3) A
simple reconfigurable barrel rotator (RBR) efficiently realizes the connectivity between a
variable number of processors in the WiFi LDPC decoder.
Disadvantages:

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 Less Efficiency
 Error detection is not potently operated
Proposed System:
Proposed wifi LDPC decoder
The overall architecture of the proposed decoder is depicted in Fig. 1. Decoding is
performed through an iterative process of information exchange between N variable
processors and the check processor. Each one of the variable processors consists of z
variable-node processing units (VPUs) and one

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` Fig. 1. Block diagram of the WiFi LDPC decode
VPU RAM. The check processor consists of z check-node processing units (CPUs). A
number of N RBR networks realize the connectivity between the processing elements of
the decoder, supporting 12 different configuration schemes. The computation path is
divided into a number of pipeline stages to increase the operation frequency. Underlined
numbers, and the corresponding dashed arrows, in Fig. 1, represent the basic computation

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stages and data-flow of the decoder; stages 1 and 3 correspond to variable-node and
check-node processing, respectively, stages 2 and 4 to transmission of v-to-c and c-to-v
messages, respectively, and stage 5 to LLR update. The RBR interface (i/f) selects
between v-to-c and c-to-v transmission, without need of a dedicated RBR for each path.
Each VPU generates one v-to-c message, and each CPU receives N messages, per clock
cycle. The relocation of check-node operations to the variable nodes has led to balanced
pipeline stages, and consequently higher operating frequency; for example, as detailed
below, the absolute values computation has been merged with the calculation of the v-to-
c messages. The design parameters N and z strongly affect the area complexity, speed,
and power consumption. Larger values of N and z derive highly parallel multi gigabit
architectures, while smaller values lead to low-cost decoders. Therefore, this architecture
is very flexible and easily adjustable to different design demands and constraints. The
introduced WiFi LPDC decoder implements variations of the MS algorithm, under the
layered decoding scheduling. In layered decoding, the rows of the LDPC PCM H are
processed in subsets (layers) in successive order. Using the information that has already
been updated by previous layers, layered decoding improves the convergence speed by
reducing the number of iterations required to achieve a target BER. This comes at the
cost of additional clock cycles per iteration due to the increased number of exchanged
messages during a single iteration. The sequential schedule of layered decoding

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Fig. 2. Architecture of the VPU circuit and interconnection with the VPU RAM.
Table 1
Maximum dv Values for the wifi LDPC codes
The architecture of the VPU circuit and the VPU memory is depicted in Fig. 2. For
simplicity, we assume N = 24 and z = 81. The VPU RAM is connected with the z VPUs
of the variable processor, which correspond to the z variable nodes of a vertical layer e (1

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≤ e ≤ 24) of the PCM. This memory stores, concatenated in the same memory word, and
without suffering of data conflicts, z c-to-v messages sent from the CPUs to the variable
processor. The VPU RAM is optimized with respect to the maximum variable-node
degree of the specific vertical layer, as derived by the 12 codes of the 802.11n/ac
standard (Table I). More specifically, assuming an n-bit data quantization, the size of the
VPU RAM is
given by max(dv ) × (z · n). The Ext module performs sign extension to the incoming
messages (LLRs and c-to-v messages) to prevent overflow during the addition operation.
A number of log2(max(dv ) extra bits are used. The updated LLR values are stored in a
register (Reg_est). The Sat − Abs module merges two operations: 1) the saturation of the
adder’s output in the n-bit quantization dynamic range and 2) the computation of the
absolute value. The relocation of the absolute computation, which is an MS check-node
operation, into the VPU decreases the CPU critical path. The sign and the magnitude of
the computed v-to-c message are concatenated to an n-bit output (out_v). The sign of the
v-to-c message is stored to a register, and used by the Sign module to identify the sign of
the new c-to-v message inv.
Advantages:
 Efficient in manner
 Excellent error detection capability
References:
[1] R. Gallager, “Low-density parity-check codes,” IRE Trans. Inf. Theory, vol. 8, no. 1, pp. 21–28,
1962.
[2] D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check
codes,” Electron. Lett., vol. 33, no. 6, pp. 457–458, Mar. 1997.

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[3] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inf. Theory, vol. IT-27,
no. 5, pp. 533–547, Sep. 1981.
[4] D. J. C. MacKay, “Good error-correcting codes based on very sparse matrices,” IEEE Trans. Inf.
Theory, vol. 45, no. 2, pp. 399–431, Mar. 1999.
[5] M. Chiani, A. Conti, and A. Ventura, “Evaluation of low-density parity check codes over block
fading channels,” in Proc. IEEE Int. Conf. Commun. (ICC), vol. 3. Jun. 2000, pp. 1183–1187.
[6] M. P. C. Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low-
density parity check codes based on belief propagation,” IEEE Trans. Commun., vol. 47, no. 5, pp. 673–
680, May 1999.
[7] J. Chen and M. P. C. Fossorier, “Near optimum universal belief propagation based decoding of low-
density parity check codes,” IEEE Trans. Commun., vol. 50, no. 3, pp. 406–414, Mar. 2002.
[8] J. Chen and M. P. C. Fossorier, “Density evolution for two improved BP-based decoding algorithms
of LDPC codes,” IEEE Commun. Lett., vol. 6, no. 5, pp. 208–210, May 2002.
[9] A. Anastasopoulos, “A comparison between the sum-product and the min-sum iterative detection
algorithms based on density evolution,” in Proc. IEEE Global Telecommun. Conf., vol. 2. Nov. 2001,
pp. 1021–1025.
[10] I. Tsatsaragkos and V. Paliouras, “Reconfigurable barrel shifter and rotator,” U.S. Patent 8 713 399
B1, Apr. 29, 2014.
[11] M. M. Mansour and N. R. Shanbhag, “High-throughput LDPC decoders,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 976–996, Dec. 2003.
[12] D. E. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,”
in Proc. IEEE Workshop Signal Process. Syst., Oct. 2004, pp. 107–112.
[13] M. P. C. Fossorier, “Quasi cyclic low-density parity-check codes from circulant permutation
matrices,” IEEE Trans. Inf. Theory, vol. 50, no. 8, pp. 1788–1793, Aug. 2004.

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