Noise insensitive pll using a gate-voltage-boosted source-follower regulator and residual noise cancellation

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A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted
Source-Follower Regulator and Residual Noise Cancellation
Abstract:
In this brief, we propose a supply noise-insensitive charge pump phase-locked loop
(PLL) using a source-follower (SF) regulator and noise cancellation. In order to minimize
the voltage drop of the SF regulator while improving supply rejection, a gate-voltage-
boosting technique and the body-controlled noise cancellation are proposed. To suppress
the phase noise from the ring oscillator, a reference multiplier is employed to maximize
the PLL loop bandwidth. Implemented in 65-nm CMOS, a prototype PLL at 3.2 GHz
achieves supply noise spur of less than −33 dBc for a 50-mVpp supply noise around the
loop bandwidth while consuming 3.12 mW from a 1-V supply.
Software Implementation:
 Modelsim
 Xilinx 14.2
Existing System:
Phase-locked loop (PLL) based on ring oscillator is widely used for clock generation in
various applications since it has a small area and a wide tuning range. Unfortunately, the
frequency of a ring oscillator is sensitive to and strongly influenced by its bias
environment, particularly supply voltage, and thus, its jitter performance is severely
degraded in the presence of supply noise. Ring oscillator also has poor phase noise
compared with the LC counterpart, which results in large jitter.
While PLL loop bandwidth can be maximized to reduce the phase noise of the ring
oscillator, it is typically limited to one tenth of the reference frequency. To reduce the
effect of the supply noise, several supply noise reduction techniques have been

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investigated. In a conventional supply-regulated PLL architecture, a low-dropout
regulator (LDO) shields the ring oscillator from the supply noise. However, it requires
additional power and a large decoupling capacitor for stability.
Furthermore, when the LDO is inside the PLL, as shown in Fig. 1(a), it limits the PLL
loop bandwidth and thus requires LDO to have a larger bandwidth, which in turn
increases the power consumption. For example, it was shown that the LDO must have 50
times the PLL loop bandwidth to achieve the desired supply rejection. On the other hand,
there are some supply regulated PLLs that place the LDO outside the PLL loop. These
PLLs do not suffer from the bandwidth issue as mentioned earlier but requires a large
decoupling capacitor and a separate voltage reference. In a discrete-time LDO is
proposed to isolate LDO noise, but it uses two pair of 80- and 160-pF decoupling
capacitors. While there have been other techniques to remove the effect of supply noise,
they are aimed for use in digital PLLs and not suitable for analog PLLs that are still used
in many applications.

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Fig. 1. Block diagrams of (a) conventional supply-regulated PLL and (b) proposed SF-regulated PLL
using noise cancellation
In this brief, we propose a supply noise-insensitive charge-pump PLL (CPPLL) using a
source-follower (SF) regulator and a noise canceling circuit. In order to minimize the
voltage drop in the SF regulator, a gate-voltage booster using switched capacitor is
employed. To remove residual supply noise at the output of the regulator, a noise
cancellation technique that uses the body of the SF regulator is proposed. Finally,

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reference multiplication technique is employed to extend the PLL loop bandwidth to
reduce the phase noise from the ring oscillator.
Disadvantages:
 Phase noise reduction is in slow process
 Reliability is low
Proposed System:
Gate-voltage -boosted source-follower regulator with a noise cancellation
Supply Noise-Insensitive CPPLL With a Gate-Voltage-Boosted SF Regulator:
A block diagram of the proposed supply noise-insensitive PLL is shown in Fig. 1(b). It
consists of a CPPLL with a reference multiplier, a SF regulator, and a noise cancellation
circuit. As the SF regulator is a feed-forward circuit and does not have a feedback
amplifier like
Fig. 2. Block diagrams of (a) conventional low dropout voltage regulator and (b) proposed gate-voltage-
boosted SF regulator.

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the conventional LDO, it achieves a wideband noise suppression. The noise cancellation
circuit improves the supply rejection by eliminating the residual noise at the regulator
output that is not removed by the SF regulator. As the PLL is unaffected by the regulator
bandwidth, a reference multiplier is used so that the PLL can achieve a wide loop
bandwidth that exceeds f ref /10. The reference multiplier generates 200-MHz output from
a reference of 50 MHz, which allows 10 MHz of loop bandwidth that helps to suppress
the phase noise of the ring oscillator
Gate-Voltage-Boosted SF Regulator With Noise Cancellation
A typical LDO has a feedback loop that consists of an error amplifier and a PMOS pass
transistor to achieve a low dropout voltage and high supply rejection, as shown in Fig.
2(a). Its supply rejection is approximately A0 and the voltage drop from the supply to the
regulator output can be as small as the overdrive voltage of the PMOS (i.e., V OV= V GS −
V THP). Unfortunately, it consumes additional power and area due to the amplifier and
stabilizing capacitor. To solve these issues while maintaining a low dropout voltage, a
gate-voltage boosted SF regulator is proposed, as shown in Fig. 2(b). We basically
exploit the fact that a transistor has a small gain from its drain to the source and thus
employ an SF for the regulator. To address the large voltage drop from the gate to the
source, a voltage-boosting circuit is employed to generate V DD + V THN the gate of SF.
As this boosted voltage contains supply noise, a low-pass filter is added before the SF
gate input. Its cutoff frequency is much smaller than the PLL loop bandwidth so that the
low-frequency noise not filtered by the LPF can be suppressed by the PLL. The detailed
performance of the proposed gate-boosted SF regulator is as follows. The supply
rejection can be described as

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where gm and r0 are the trans conductance and output resistance of NMOS and RRO is
the effective resistance of the ring oscillator. Assuming 1/gm is much smaller than r0 and
RRO, supply rejection is approximately gmr0 which is similar to the conventional LDO.
Regarding the dropout voltage, the gate voltage of the proposed SF is boosted to about
VDD + VTHN, and hence, the output voltage is about VDD − VOV, resulting in a
similar voltage drop to the conventional LDO. While the above-mentioned analysis
shows that the proposed gate boosted SF regulator has a similar performance to the
conventional LDO, its performance is actually degraded in practice due to the tradeoff
between supply rejection and dropout voltage. That is, as we try to reduce the dropout
voltage by increasing the gate voltage, becomes smaller and thus reduces the amount of
supply rejection. This is shown in Fig. 3, which is a simulation result of the proposed
Fig. 3. Simulation results of the supply rejection and dropout voltage versus gate voltage.

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Fig. 4. Block diagram of the proposed noise cancellation circuit
SF regulator. It can be seen that as gate voltage increases, dropout voltage is reduced but
the supply rejection is degraded. For example, a gate voltage of 1.4 V results in a dropout
voltage of less than 50 mV but the supply rejection is degraded to less than 10 dB.
However, it can also be seen that if we allow a dropout voltage of more than 100 mV,
then the supply rejection is more than 20 dB that can be sufficient for many applications.
For a low-noise PLL, we aim at achieving higher supply rejection and thus propose a
noise cancellation technique that can be added to the SF regulator. The basic block
diagram of the proposed noise cancellation technique is shown in Fig. 4. To cancel
residual noise at the output of the SF, the body of the NMOS is controlled by supply
noise that is level shifted and scaled by a gain stage. Note that since the gains from drain
to source and body to source are both positive, the gain stage must have a negative gain
of −G for noise cancellation.
Circuit implementation
Gate-Voltage-Boosted Source-Follower Regulator:
The schematic of the gate-voltage-boosted SF regulator and its timing diagram are shown
in Fig. 5. Note that while a high gate voltage allows a low dropout voltage, too high gate

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voltage will put M N in triode region, where the SF regulator no longer operates properly.
Hence, the gate voltage is boosted not to exceed V DD+V THN so that M N is always in
saturation region. In detail, transistors M 1 and M 2 generate VTHN+VOV for V1. To
reduce power consumption, ha M 2 s a small W/L, which results in 50 μA of current. ha
M 1 s a large W/L so that V OV V THN. The output of the threshold voltage generator is
boosted by a switched capacitor circuit using non overlapping clocks 1 and 2 that are at
200 MHz, derived from the divided clock of the PLL output. An RC low-pass filter of
about 100-kHz cutoff frequency is added to remove high-frequency supply noise that
cannot be filtered by the PLL and to suppress ripple at V GATE arising from
Fig. 5. Schematic of the voltage boosted SF regulator and its timing diagram.

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Fig. 6. Schematic of the ring oscillator with noise cancellation circuit
switched capacitor. The RC low-pass filter is implemented with an N-poly without
silicide resistor and a metal–oxide–metal capacitor, whose values are 250 K and 10 pF,
respectively. While the ideal boosted voltage is V DD + V THN + V OV, it is actually smaller
due to the parasitic capacitance of the boosting circuit. Simulation results show that the
boosted voltage is 1.22 V when V THN is 300 mV and the supply is 1 V. The resulting
regulated output is 860 mV and the supply rejection is 24 dB.
Ring Oscillator and Noise Cancellation Circuit :
The schematic of the proposed SF-regulated ring oscillator with noise cancellation circuit
is shown in Fig. 6. The ring oscillator consists of differential delay cells. The supply of
delay cells is tied to source of that M N is the output of the SF regulator. The loop filter
output adjusts V CTRL to tune the frequency of ring oscillator. The noise cancellation
circuit consists of two stages. The supply noise is level shifted and scaled by two stacked
diode-connected transistors. Next, it is fed to the body of M N via a gain stage that is

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implemented by a source-degenerated common-source amplifier. The implemented noise
cancellation circuit has a phase delay of about 3.5° at noise frequency near the loop
bandwidth (10 MHz). Such a phase shift leaves about 5% of residual noise after noise
cancellation even if the cancellation gain is perfectly matched. However, since the SF
regulator alone already reduces the supply noise to less than 1/10, the overall effect of
phase shift is less than 0.5% of supply noise.
Fig. 7. Schematic of (a) reference multiplier and (b) duty cycle corrector
Reference Multiplier :
The schematic of reference multiplier is shown in Fig. 7. It consists of a digital duty cycle
corrector and two frequency doublers composed of delay cells and an XOR gate. Since
the frequency doubler uses both rising and falling edge of the input clock, the input duty
cycle must be 50 % or else the output clock will have spurs. The incoming reference
clock is assumed to be 50 %, and the duty cycle corrector after the first frequency doubler
adjusts the duty for the second frequency doubler.
Advantages:
 Phase noise reduction is reduced
 Reliable in operation
References:

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[1] E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, “Replica compensated linear regulators for
supply-regulated phase-locked loops,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb.
2006.
[2] A. Arakali, S. Gondi, and P. K. Hanumolu, “Low-power supplyregulation techniques for ring
oscillators in phase-locked loops using a split-tuned architecture,” IEEE J. Solid-State Circuits, vol. 44,
no. 8, pp. 2169–2181, Aug. 2009.
[3] Q. Sun, Y. Zhang, C. Hu-Guo, K. Jaaskelainen, and Y. Hu, “A supplynoise-insensitive PLL in
monolithic active pixel sensors,” IEEE Sensors J., vol. 11, no. 10, pp. 2212–2219, Oct. 2011.
[4] K.-C. Choi, S.-G. Kim, S.-W. Lee, B.-C. Lee, and W.-Y. Choi, “A 990-μW 1.6-GHz PLL based on a
novel supply-regulated activeloop-filter VCO,” IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 60, no. 6,
pp. 311–315, Jun. 2013.
[5] H. C. Ngo, K. Nakata, T. Yoshioka, Y. Terashima, K. Okada, and A. Matsuzawa, “A 0.42ps-jitter
−241.7 dB-FOM synthesizable injection-locked PLL with noise-isolation LDO,” in IEEE ISSCC Dig.
Tech. Papers, Feb. 2017, pp. 150–152.
[6] D. Kim and S. Cho, “A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a
wideband noise suppression loop,” in Proc. IEEE Symp. VLSI Circuits, Jan. 2017, pp. 180–181.
[7] T. Wu, K. Mayaram, and U.-K. Moon, “An on-chip calibration technique for reducing supply
voltage sensitivity in ring oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr.
2007.
[8] A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, “A 0.4-to-3 GHz digital PLL with PVT
insensitive supply noise cancellation using deterministic background calibration,” in IEEE ISSCC Dig.
Tech. Papers, Mar. 2011, pp. 92–93.
[9] Y.-C. Huang, C.-F. Liang, H.-S. Huang, and P.-Y. Wang, “A 2.4 GHz ADPLL with digital-regulated
supply-noise-insensitive and temperatureself-compensated ring DCO,” in IEEE ISSCC Dig. Tech.
Papers, Feb. 2014, pp. 270–271.
[10] C.-W. Yeh, C.-E. Hsieh, and S.-I. Liu, “A 3.2 GHz digital phase-locked loop with background
supply-noise cancellation,” in IEEE ISSCC Dig. Tech. Papers, Jan. 2016, pp. 332–333.

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[11] H. Huh et al., “A CMOS dual-band fractional-N synthesizer with reference doubler and
compensated charge pump,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 100–516.

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