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Crosstalk Aware Bandwidth Modelling for VLSI RC Global Interconnects using 2-π Model
1. CROSSTALK AWARE BANDWIDTH
MODELLING FOR VLSI RC GLOBAL
INTERCONNECTS USING 2-Π MODEL
Presented By
Santosh Kumar Chhotray
National Institute of Technology, Durgapur
7. PROPOSED ESTIMATION METHOD
Aggressor Waveform
0
( )
dd a
aagg
dd a
t
V t
V t
V t
2
1
( )agg dd
a
V s V
s
In S-domain
In Elmore delay model, the delay time between node na1 and
node na2, D1→2 is represented as
1 2 1 1 2 3 2 2 3a a a c a a a c aD R C C C C R C C C
8. CONT..
Aggressor Waveform
Where
Now becomes
1 1 2 3 2 2 3a a a a c a a a c aR C C C C R C C C
Effective capacitance
1 1 2 3 2 2 3a a a c a a a c aT R C C C C R C C C
3 3dj a aT R C
1 1 2 3 2 2 3a a a a c a eff a a c a effR C C C C R C C C
a
3 3 1 dj
T
T
a eff aC C e
9. PROPOSED ESTIMATION METHOD
Analytic Waveform of Victim Interconnect
1 2 1 1 2
3 2
( ) ( )
1
v v v v v c
noise agg
R R C s R R C s
V s V s
as bs ds
1 2 3 1 1 3v v v v v c va R R R C C C C
1 1 2 2 3 3 3 3 3 2 1 2v v v v C v v v v v v c v vb R C R C C C R C R C C C R R
1 1 2 3 2 2 3 3 3v v v c v v v c v v vd R C C C C R C C C R C
10. CONT..
Now Vnoise(S) can be written as
where poles s1, s2 and s3 are roots are of . When
relationship of s1< s2<< s3 is satisfied, the most
dominant pole s3 is represented as 1/d. Replacing d by
Vnoise (S) obtained as
31 2
1 2 3
( ) ( )noise agg
KK K
V s V s
s s s s s s
v
1 2
( )
1
v v c
noise dd
v a
R R C
V s V
s s
11. CONT..
After solving with partial fraction
Now taking ILT
1 2 1
( )
1
v v v
noise c dd
a v
R R
V s C V
s s
1 2
( ) 1 v
t
tv v
noise c dd
a
R R
V t C V e
12. DELAY ESTIMATION
Simplifying above equation
1 2
0.5 1 v
t
tv v
dd c dd
a
R R
V C V e
50%
1 2
1
(1/ )
2
v a
c
v v
t C
R R
For delay estimation equating
Vnoise(S)=0.5 Vdd
13. BANDWIDTH ESTIMATION
Rearranging above equation
Now replacing S by
1 2( )
( )
( ) 1
v vnoise
c
agg v a
R RV s
H s sC
V s s
1 2
( )
1
v v
c
a v
R R s
H s C
s
1 2
2 2
( )
1
c v v v
a v
C R R j
H j
j
14. CONT..
Now to get 3db bandwidth
1 2
2 2
1
2 1
c v v
v v
C R R
3 2 22
1 22 2
a
dB
c v v a v
f
C R R
18. CONCLUSION
For delay estimation
For bandwidth estimation
3 2 22
1 22 2
a
dB
c v v a v
f
C R R
50%
1 2
1
(1/ )
2
v a
c
v v
t C
R R
19. REFERENCES
[1] Wu Shien-Yang, Liew Boon-Khim, Young K.L., Yu C.H., and Sun S.C., 1999,
“Analysis of Interconnect Delay for 0.18µm Technology and Beyond, IEEE
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20. CONT..
[8] Kar R., Maheshwari V., Maqbool Mohd., Mal A. K., Bhattacharjee
A. K., 2010 , “A Closed form Delay Evaluation Approach using Burr’s
Distribution Function for High Speed On-Chip RC Interconnects”,
IEEE 2nd International Advance Computing Conference (IACC
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[9] Kar R., Maheshwari V., Reddy M. Sunil K, Agarwal V., Mal A.
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On-Chip VLSI RC Interconnects using First Three Circuit Moments”,
14th VLSI Design And Test Symposium (VDAT 2010), July 7-9, ,
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Crosstalk Modeling for Noise Constrained Interconnect
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