Final presentation [dissertation project], 20192 esv0002

DISSERTATION INDUSTRY PROJECT
[ECE- 514]
FINAL SEMINAR
PRESENTED BY:
Mohammed Furqhan
[2192ESV0002]
PRESIDENCY
UNIVERSITY
GUIDED BY:
Mr. Subramanyam Vinayaka Babu
Director
4semi Technology India Pvt Ltd
6/13/2021
IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM
1
CO-ORDINATED BY:
Ms.Akshaya M Ganorkar
Assistant Professor
Presidency University

 Introduction Of The Company
 Moto Of The Company
 Objective
 Topic
 Lcd Simulation
 Adc Simulation
 Dac Simulation
 Labview User Interface
 System Requirnments
 Future Scope
 Conclusion
 Refrences
IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM 6/13/2021 2

 4semi Technology is at the forefront of technology innovation, providing customers solutions for all embedded and
programmable FPGAs. We offers expertise in FPGA / ASIC Design, High Speed Board Design and Physical Layout, PNR
flow and Associated flows, STA, LEC, IR and Custom Analog Layout.
 4semi Tech to focuses on its core competency; the development and deployment of leading-edge programmable
technology that provides maximum value to customers we bringing new products to the market and helping user for
the next generation of electronics.
 4semi technology provides solutions for both hardware and software dependencies.
 4semi Technology provides product engineering solutions and services for customer premise equipment across
different types of hardware solutions.
6/13/2021
IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM 3

 4semi Technology provide excellent engineering services with high quality design and verification services which
improve overall productivity and cost effectiveness. We provide expert consultants and contractors both on site and
offshore in semiconductor and hardware domain.
 4semi Technology provides product engineering solutions and services for customer premise equipment across
different types of hardware solutions.
 4semi Technology provides efficient, robust and cost-effective answers for your individual or business needs.
 4semi Technology provide excellent engineering services with high quality design and verification services which
improve overall productivity and cost effectiveness. We provide expert consultants and contractors both on site and
offshore in semiconductor and hardware domain.
6/13/2021

OBJECTIVES
 Interfacing LCD with SPARTAN-6
 Acquiring data from ADC/DAC through (Sensors).
 Displaying real-time data on LCD.
 Ni-LabVIEW interface (DAQ/DATA LOGGING)
 Future scope

LCD
ADC
DAC
GUI
INTERFACE
6/13/2021
010101
SPARTAN-6
TQG-144
SC6SLX9
SPEED -2
FPGA
LCD-RC1602A
ADC-MCP3004
DAC-DAC084S085

6/13/2021
Title, author and Year Description
[1] Title: Exploring The Serial Capabilities For 16x2 Lcd Interface
Author: Pooja Soni1 , Kapil Suchdeo
Year- 2012
Advancements in technology for chip manufacturing are leading to the
device which incorporates various functionalities within single chip. To
reduce the complexity and size of the overall printed circuit board.
Keeping the same idea in mind, lots of embedded project require to
interface with 16x2 LCD or character LCD, which is one of widely used
LCD available in market, with growing complexity and need to provide
lots of functionality within the same size, the pins provided on the
controller remains same, now it become difficult to share pins of the
controller, the present work reflects about the working model which
describes a technique to reduce the pin requirements of pin hungry
interfaces for example considering 16x2 LCD normally if one has to
interface such LCD’s, they need to dedicate at least 6 pins or at
maximum 11 pins of a controller.

6/13/2021
[2] Title: Poorani, S., et al. "FPGA based fuzzy logic
controller for electric vehicle." Journal of the Institution
of Engineers 45.5 (2005): 1-14.
The hardware consists of one 20 character by 4-line LCD screen,
potentiometers for acceleration and braking, battery, ADC 0808, motor,
IR sensor, PWM driver circuit and five toggle switches. Figure 3 shows
the hardware interface for the design. To get the acceleration data, a
47K potentiometer is used. Likewise, another potentiometer is used to
get the brake data. A lead acid battery of 12V 7.5 AH is used to give the
power supply to the whole module. A voltage regulator circuit is used
to provide the 5V that is needed from the 12V available to other
components in the circuit. The voltage for the motor (12V) is taken
directly from the battery and a voltage regulator circuit is used to step
down the 12V to 5V in order to drive the Xilinx, ADC and LCD
components.

6/13/2021
[3] Title:Pujari, Sashank Shekhar, et al. "Design &
implementation of FIR filters using on-board ADC-DAC &
FPGA." International Conference on Information
Communication and Embedded Systems (ICICES2014).
IEEE, 2014.
Electronics industry is very prodigiously moving towards digital
platform, but the world is analog in nature, so when any analog signal
needs to be processed in digital platform it should be converted to
digital with the help of analog to digital converter. After processing
through digital platform by the help of DAC it will be again converted to
analog format. Here the digital platform is ALTERA CYCLONE-II FPGA.
FIR filters are used in every aspect of present-day technology because
filtering is one of the basic tools of information acquisition and
manipulation. Different types of digital FIR filters are implemented on
external signal by using VERILOG HDL language over FPGA.

6/13/2021
[4] Title: Dagbagi, Mohamed, et al. "ADC-based embedded
real-time simulator of a power converter implemented in a low-
cost FPGA: Application to a fault-tolerant control of a grid-
connected voltage-source rectifier." IEEE Transactions on
Industrial Electronics 63.2 (2015): 1179-1190.
This paper deals with embedded real-time (RT) simulators
applied in power electronic applications and implemented in
low-cost field-programmable gate arrays. Indeed, such
simulators' intellectual properties (IPs) are not only intended
for hardware-in-the-loop (HIL) testing but also can be
advantageously embedded within digital controllers to ensure
functions such as observation, estimation, diagnostic, or
health monitoring.

6/13/2021
[5] Title: Exploring The Serial Capabilities For 16x2 Lcd
Interface
Author: Pooja Soni1 , Kapil Suchdeo
Year- 2012
In this paper we discuss the design and implementation of a
FPGA power DAC for digital audio applications. The paper
concentrates on the sigma-delta modulator, which is used to
convert an oversampled PCM input signal into a 1-bit code
suitable for controlling a power switch. The design of the bit-
flipping architecture used to reduce the pulse-repetition
frequency of the output is discussed, together with the loop
filter structure and transfer function design. This is followed by
details of FPGA architecture and the optimizations required for
implementation.

IMPLEMENTATIO
N ON FPGA REAL
TIME
DATA
ACQUASITION
SYSTEM
6/13/2021

6/13/2021 IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM 13

14
IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM 6/13/2021

 Liquid crystal display (LCD) is a device
that utilizes the electro-optical
characteristics of a liquid crystal to
convert an electrical stimulus into a
visual signal.
 It helps bring to life your imagination
and ideas and display them on a screen.
6/13/2021
IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION
SYSTEM 15

Let us ride on a beam of light
as it passes through the various
components of an LCD screen
16

17

LCD consist of 8- Data lines D0-D7, RS- Register Select line, RW-Read Write line, En-
Enable line.
First, we need to send commands to initialize the display, Curser Position, Clear
Display, increment curser etc. All this command are sent to instruction Register.
Instruction Register can be enabled by RS = ‘0’, RW = ‘1’, En= ‘1’.
ASCI Values for Commands used in the code
38 = Function Set: 8-bit, 2 Line, 5x7 Dots

After sending
commands, Data can be
transferred to Display in
the LCD. For sending
Data enable Data
Register by sending
RS= ’1’, RW= ‘1’, En= ’1’
Data can be transferred
in 2 ways 8-bit mode and
4-bit mode. Here we are
interfacing in 8-bit mode
with the entire Data pin
D0-D7.
VHDL Code consists for
2 counters i and j. i
counter used to divide
the clock and j counter
used to get the array
elements.

Functions of some important pins
 RS: Register Select
• 0: Command
• 1: Character
 RW: Read / Write
• 0: Write
• 1: Read
 E: Enable
• Low to high pulse of 3ms
 D0-D7: Data pins used to send command or
character to be displayed
 D7: Used in read mode for reading completion of current
operation

21
Sr. No. Command in
Hex
Operation
1 01 Clear display
2 02 Return home
3 04 Shift cursor to left
4 05 Shift display to right
5 06 Shift cursor to right
6 07 Shift display to left
7 08 Display off, Cursor off
8 0A Display off, Cursor on
9 0C Display on, Cursor off
10 0E Display on, Cursor on
11 0F Display on, Cursor blinking
12 10 Shift cursor to left
13 14 Shift cursor to right
Sr. No. Command in Hex Operation
14 80 Cursor at first line, first
character
15 C0 Cursor at second line, first
character
16 38 2 Lines, 5x7 crystal matrix
and 8 bit mode
17 28 2 Lines, 5x7 crystal matrix
and 4 bit mode


22

 To send all commands to LCD, RS = 0, RW = 0
 Command : 38H = 2 lines, 5x7 matrix, 8-bit display
mode
 and data lines (D7-D0) are used
E = 0
Delay of 40 ns
E = 1
Delay of 230 ns
 Command : 06H = Shift cursor right
E = 0
Delay of 40 ns
E = 1
Delay of 230 ns
 Command : 0CH : Display on, cursor off
E = 0
Delay of 40 ns
E = 1
Delay of 230 ns
6/13/2021

COMMAND
SENDING
(8-BIT
MODE)
Command : 01H: Clear display
•E = 0
•Delay of 40 ns
•E = 1
•Delay of 230 ns
Command : 80H: Cursor at 1st line
1st character
•E = 0
•Delay of 40 ns
•E = 1
•Delay of 230 ns
6/13/2021

 To send characters (GHRIET) to LCD, RS = 1,RW = 0
 Data : 47H = G
E = 0
Delay of 40 ns
E = 1
Delay of 230 ns
 Data : 48 = H
E = 0
Delay of 40 ns
E = 1
Delay of 230 ns
 Data : 52 = R
E = 0
Delay of 40 ns
E = 1
Delay of 230 ns
6/13/2021

CHARACTE
R SENDING
(8-BIT
MODE)
Data : 49: I
•E = 0
•Delay of 40 ns
•E = 1
•Delay of 230 ns
Data: 45: E
•E = 0
•Delay of 40 ns
•E = 1
•Delay of 230 ns
Data: 54: T
•E = 0
•Delay of 40 ns
•E = 1
•Delay of 230 ns
6/13/2021

27

6/13/2021

INIT
Finish LCD
initialization
sequence
DONE
Display
State diagram
Power on Init
Sequence in
State Dig 1
Init_done = 0
Init_done = 1
CHAR_S
LCD_RS = 1
Data
Tx_byte = 48H
CHAR_E
LCD_RS = 1
Data
Tx_byte = 52H
CHAR_I
LCD_RS = 1
Data
Tx_byte = 45H
CHAR_T
LCD_RS = 1
Data
Tx_byte = 54H
CHAR_M
LCD_RS = 1
Data
Tx_byte = 49H
CHAR_E
LCD_RS = 1
Data
Tx_byte = 50H
CHAR_4
LCD_RS = 1
Data
Tx_byte = 47H
SET_Addr
LCD_RS = 0
CMD
Tx_byte = 08H
FUNCTION_SET
LCD_RS = 0
CMD
Tx_byte = 28H
ENTRY_SET
LCD_RS = 0
CMD
Tx_byte = 06H
SET_DISPLAY
LCD_RS = 0
CMD
Tx_byte = 0CH
CLEAR_DISPLAY
LCD_RS = 0
CMD
Tx_byte = 01H
PAUSE
82000 clock
6/13/2021

 A super-twisted nematic display (STN) is a type of monochrome passive-matrix liquid
crystal display (LCD).
 STN displays, with the molecules twisted from 180 to 270 degrees, have superior
characteristics.
 The main advantage of STN LCDs is their more pronounced electro-optical threshold
allowing for passive-matrix addressing with many more lines and columns.
 STN LCDs require less power and are less expensive to manufacture than TFT LCDs,
another popular type of LCD that has largely superseded STN for mainstream laptops.
STN displays typically suffer from lower image quality and slower response time than
TFT displays.

• DSTN can stand for:
• Double layer STN – An earlier passive matrix LCD technology that used an extra
compensating layer to provide a sharper image.
• Dual Scan STN – An enhanced STN passive matrix LCD. The screen is divided into
halves, and each half is scanned simultaneously, thereby doubling the number of
lines refreshed per second and providing a sharper appearance. DSTN was widely
used on earlier laptops. See STN and LCD.
• FRSTN – Fast Response STN
• FSTN – Film compensated STN, Formulated STN or Filtered STN. A passive matrix LCD
technology that uses a film compensating layer between the STN display and rear
polarizer for added sharpness and contrast. It was used in laptops before the DSTN
method became popular and many early 21st Century cellphones.
• FFSTN – Double film super-twist nematic
• MSTN – Monochrome super-twist nematic
• CCSTN – Color Coded Super Twist Nematic. An LCD capable of displaying a limited range
of colors, used in some digital organizers and graphic calculators in the 1990s
6/13/2021 IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM 37

38

An analog to digital converter is a circuit
that converts a continuous voltage value
(analog) to a binary value (digital) that can
be understood by a digital device which could
then be used for digital computation.
These ADC circuits can be found as an
individual ADC ICs by themselves or
embedded into a microcontroller. They’re
called ADCs for short.

A good way to look at the working of an ADC is to imagine
it as a mathematical scaler. Scaling is basically mapping
values from one range to another, so an ADC maps a
voltage value to a binary number.
What we need is something that can convert a voltage to a
series of logic levels, for example in a register. Of course,
registers can only accept logic levels themselves as inputs,
so if you were to connect the signal directly to a logic input
the results wouldn’t be good
Something in between the logic and the analog input
voltage needs to act like an interface Here are some
important features of ADCs, while going through them
we’ll learn how they work.
6/13/2021

41

 These ADCs are perhaps the most accurate. They consist of a comparator, a simple flash
DAC and a memory register. The device initially assumes all the bits in the register
except for the highest significant bit (which is a one) to be zeroes.
 The register then sends this to the DAC which converts it to an analog voltage, which is
compared with the input through the comparator. If the input voltage is higher than the
DAC voltage, then the MSB remains one.
 This process repeats until all the bits have been set either to zero or one, in other words
till the register value exactly equals the input voltage.
 This ADC is one of the most used where accuracy is needed and speed is not too much
of a limitation, for example in microcontrollers. SA type ADCs can easily achieve
conversion times of a few microseconds.
SYSTEM
6/13/2021 42

43

 Here we are interfacing on board
analogous out-put sensors so that we
can interface ADC
 THE CH1 and CH2 both the channels
are left for external interface of signal s
 CH3 AND CH4 we can see the out put
after interfacing it with the ADC with
CH-3 AND LM35 SENSOR OUTPUT
AND CH-4 AS POTENTIOMETER
OUTPUT

 Now as per following image J4 & J7 jumper
connected, analog input given
 from temperature sensor lm35 and pot PR1
respectively
Working of adc in spartan 6 fpga

 The maximum input voltage is 3.3v
 This above circuit shows the way the
channels are connected through jumpers
internally

 IN the above figure we can see that channel A and
channel B are left out for external interface e.g.
transducer
 IN REAL TIME
 Channel C – lm35
 Channel D - POT

 Now suppose Vref is 3.3V
 As 10bit ADC max count is 1023
 Voltage for one steep = Vref / 1023
 Voltage for one steep = 0.00322
 Now the see count that display on LCD
as shown below
 Input voltage at Ain-D =0.00322 X count
on LCD
SYSTEM
6/13/2021 48

 LCD code included in the top-bit file
interfaced and executed in phase -01

 This figure shows the Xilinx
environment in which the ADC setup
interfacing with LCD

 All the 4 channels are coded with bin –
bcd converters

 Parallel to serial code

 Serial in parallel out code

 ADC code

 State machine – code used for ADC

 All the components listed in the
main executing file the TOP-BIT
The SPI bus specifies four logic signals:
SCLK : Serial Clock (a clock signal that
is sent from the master)
MOSI : Master Output, Slave Input (data
sent from the master to the slave)
MISO : Master Input, Slave Output (data
sent from the slave to the master)
SS : Slave Select (sent from the master,
active on low signal). Often paired with
the Chip Select (CS) line on an
integrated circuit that supports SPI.

 PIN assignment .ucf file through plan-
ahead

 Location from data sheet pin
Assignment Using Plan-ahead

 Syntax check
 The code is completely synthesized and
compatible to the FPGA used

 The lcd bit locations are mapped with
the output channels of adc to be
interfaced in real-time

 The code is successfully synthesized and
ready to dump using ise-impact

 After the programming bit file is
generated, we need to select the bit file
and program

 HERE,
 CH1 and CH2 and left for
external inputs of signals for
e.g., a transducer
 CH3 is interfaced with the LM-
35 the on-board temp sensor
 CH4 is interfaced the
potentiometer

 CALCUL
ATION
LM35-
POTENT
IOMETE
R
 Vref=3.3
 10-bit ADC MAX count is = 2*10 = 1024
 Voltage for 1 step = 3.3/1024 = 0.0032
 Input voltage = 0.00322 x count on LCD

65

 The board includes 8-bit 4 channels, digital-to-analog converter.
 (DACs) DAC084S085, DAC allows easy interface to most popular microprocessor
buses and output ports.
 DAC works on 3.3V.
 VREF is connected to 3.3V, so analog voltage output rang of all channel is 0 to 3.3V.
 DAC Interface

 As it name implies, DAC is used to convert the form of a digital
signal into the form of an analog signal. In some application,
the DAC needed for interface the FPGA with some other
external devices. The FPGA should process only digital value. So
that devices are required such as ADC and DAC. The function
of DAC has been explained below.
 The digital input is given to DAC such as 0 or 1 which means the
voltages are represented as logic 1 or 0. The binary value can
be sent either the form of serial or parallel which is depends up
on the chip only. Now the output of DAC would be analog.
SYSTEM
6/13/2021 67

8- BIT DAC
Here 8-bit DAC has been used on the FPGA
which is based on SPI (Serial Peripheral
Interface) protocol.
The controller designed to covert the digital data
into analog, where the digital data is transferred
using SPI Controller and DAC (MCP4921)
converts the serial data into the analog.
SPI Controller controls the speed, data
transmission, DAC selection etc.
As it is SPI based DAC, the number of pin in IC
is low.

Power supply
VDD is the power supply
pin of the DAC which is
the range various from
2.7v to 3.3v. If use
decoupling capacitor,
will improve the
performance of DAC.
Chip select (CS)
The CS pin is used to
initiate the communication
between the FPGA and
DAC. If this pin is low, the
conversion will initiate. If
the pin is high, the
conversion will terminate.
Serial clock input
The serial clock is used
to initiate the conversion
and it gives clock for
each bit while
conversion.
Serial data input
This pin is used as clock
into input channel
configuration data.
Latch DAC
The pin is called as latch
DAC synchronization
input. This is used to
transfer the data from
input latch register to the
DAC register (output
latch) when the pin is
low.
Reference voltage (Vref)
Normally this pin is
connected to VDD.
VSS
This is analog ground
pin which is connected
to ground of the supply.
Vout
This pin is DAC output
pin. The voltage range of
DAC output varies from
VSS to VDD
6/13/2021

 SIMULATION

 SEVEN SEGMENT CODE

73

74

 RTL MODULE

 Simulation result

 FINAL RESULT

6/13/2021
FPGA
LCD
7-SEG
RE-
SET
ADC
DAC
NI-LABVIEW
GUI/DATA
LOGGING
DIP-
SWITCH

 NI-LABVIEW

82

USB
LCD
INPUT/OUTPU
T
ADC/DAC WIRELE
SS
WIRED
ETHERNET
GUI
INTERFAC
E
6/13/2021
 FUTURE SCOPE

 HARDWARE
REQUIREM
ENTS
System : Intel i3 2.1
GHZ
• Memory : 4 GB
• Hard Disk : 80 GB.
• FPGA
XILINX ISE TOOL
NI-LABVIEW
NI-VISA
MODELSIM
6/13/2021

 Operating System : Windows 7 / 8 or above.
 Tools : Xilinx ise , modelsim , ni-labview , ni-visa
 Language : VHDL
6/13/2021

 Basic knowledge on electronics.
 FPGA interfacing.
 Working and interfacing of fpga with ni-labview.
 Working and interfacing of fpga with Xilinx ise tool
 VHDL programming
 Learning how to generate a synthesize-able code from a design in Xilinx.
 Learning the working of different sensors e.g.- lm35,adc,dac

 The system is to monitor the external / internal analog /digital signals.
 Displaying the values of the signals on a 16x2 lcd in Realtime.
 User interface using LabVIEW helps us to see the signals in a wave form graph.
 DAQ(data acquisition) is used to pair with the analog voltages.
 Ni visa / ni fpga module is used to link the device.
 Data Logging is used to store the data in a excel sheet in NI- LABVIEW.
 This is a low-cost system which can be used in medical fields replacing huge
machine e.g.- oscilloscope

 Exploring The Serial Capabilities For 16x2 Lcd Interface
 Author: Pooja Soni1 , Kapil Suchdeo
 Year- 2012
 https://en.wikipedia.org/wiki/Liquid-crystal_display
 https://www.pantechsolutions.net/cpld-fpga-boards/spartan6-fpga-project-board
 https://www.xilinx.com/products/silicon-devices/fpga/spartan-6
 https://www.engineersgarage.com/arduino/measuring-room-temperature-with-lm35-using-arduino/
 https://chibiforge.org/doc/19.1/hal/group___a_d_c.html

 https://www.alldatasheet.com/view.jsp?Searchword=MCP3004
 https://components101.com/articles/analog-to-digital-adc-converters
 https://www.xilinx.com/products/silicon-devices/fpga/spartan-6
 Xin-ping Chen, "Design of control module for ADC based on FPGA," 2011 IEEE International
Conference on Computer Science and Automation Engineering, 2011, pp. 571-572, doi:
10.1109/CSAE.2011.5953285.
 Designing an introductory FPGA-based embedded system laboratory
 American Journal of Embedded Systems and Applications 2014; 2(2): 6-12 Published online June 30, 2014
(http://www.sciencepublishinggroup.com/j/ajesa) doi: 10.11648/j.ajesa.20140202.11
6/13/2021

IMPLIMENTATION ON FPGA REAL TIME DATA ACQUISITION SYSTEM
90
6/13/2021

Final presentation [dissertation project], 20192 esv0002

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Final presentation [dissertation project], 20192 esv0002