1. MATTHIAS ANTHONY GIRARDI
PO Box 311
MENDHAM, NEW JERSEY 07945
(602) 321-4702
M.Girardi@onsemi.com
OBJECTIVE Engineer, Engineering Manager, Project Manager, or Manager for high volume semiconductor
factory.
EDUCATION B.S.E. in Electrical Engineering, Arizona State University, May 1995
Full-time student and worked full-time (Fully financed own education)
Certification in Leadership, Non-Commissioned Officer School, United States Air Force ROTC,
Arizona State University October 1988
Certification in Leadership and Communication, United States Air Force Auxiliary June 1987
Recipient of Billy Mitchell, Amelia Earhart, and General Carl A. Spaatz Awards in United States
Air Force Auxiliary for training and demonstration of leadership and aerospace skills
Started working on getting an MBA degree in Technology Management from the University of
Phoenix. Have completed 33% of the classes with a GPA of 3.9. This is currently on hold while
on assignment in Malaysia.
EXPERIENCE ON Semiconductor ISMF Fab, Seremban, Malaysia
September 2014 to Present as the Back End & Center Of Excellence (COE) Operations Manager.
Responsible for leading the overall manufacturing, equipment, and process engineering team to
get 32,000 or more wafers a week out of the ISMF back grind and back metal operation for the fab
and COE. This is a team of three staff managers, 6 section managers, 14 engineers, 46
Technicians, and 186 operators running and maintaining a three shift 24 hours a day 7 days a
week high volume manufacturing operation. Are is required to run with high yield (97%+ with
current yields reaching the 98-99% range), turn the work in progress at least once a day (just at
this mark but can do better with inventory reduction and line linearization), and 90%+ On Time
Delivery. Must also constantly support new product introduction and development projects
(currently running On Time Delivery of 100% of these 300-500 wafers per week requirement).
This line currently processes 4”, 6”, and 8” wafers down to 2 mils final thickness with very low
thickness and TTV tolerance requirements. Work is underway to develop processes that can do 1
mil final thickness wafers or less as well as process wafers with high warp (some products can run
15-25 mm of warp). Also spend time developing long term plans and strategies for people
development, expansion, new part development, new process development, and second
sourcing/transfer projects. Operation must run with low scrap and low cost with a year-on-year
goal of 6% overall cost reduction (team has meet every year so far). Line must support processing
all types of products from discrete devices, to high end IC’s.
ON Semiconductor ISMF Fab, Seremban, Malaysia
January 2013 to September 2014 as the Process Engineering Manager. Responsible for leading a
team of 30 engineers and 21 shift engineers/techs to improve process performance, stability, and
characterization to electrical performance based on inline testing. Leading scrap reduction in the
team and cross functional team s to reduce scrap and improve yields (33% reduction as of end of
Q3’13). Also helped to organize and restructure the team to make it more efficient and have
proper leadership in place at the section manager level. Lead Photo and Etch organization to
reduce redo’s by 50% or more to enable the factory to ramp up to 19,500 wafers per week internal
and 9,500-10,500 wafers per week foundry for back grind and/or back metal (COE). Worked with
cross functional team to help implement tools and processes to enable the factory to ramp to
21,000 wafers per week internal and 10,500-1,500 wafers per week COE. Help to mentor existing
and new engineers in all disciplines. Organized and lead SPC, FMEA, and OCAP focus meetings
to instill these systems as part of the culture. Helped to bring in Plasma Die Singulation/Ablation

2. process, Low TTV IGBT process, and 2 mil MOSFET process on 8” wafers. Working on cost
reductions that will total over $1,000,000 USD in 2014 if the funding is approved. Mentoring
replacement section manager to the eventual rotation out of the expat position into other rolls for
the company when the time comes.
ON Semiconductor ISMF Fab, Seremban, Malaysia
September 2009 to December 2012 as the site Project Manager. Responsible for designing,
building, and starting up the new factory. Expanding fab to 50K square feet of new clean room
space at class 1000 and class 100 to run 6" wafers. New fab was built on schedule and old fab has
been renovated. Moved and installing over 250 tools on site while running the factory at 10K
wafers per week. Coordinating between the fab, contractors, planning, and other areas of the
company to achieve this with as minimal impact to production as possible. Fab is capable of 25K
wafers per week and 6K wafers per week of foundry. Also running numerous other projects at the
same time to facilitate other capacity expansion (Taiko Grinder Capacity doubling, SANYO
technology/tool transfer, and COE expansion), bring in new processes (AuSn back metal
sputtering, Si Back Side Plasma Etching, Plasma Die Singulation, Very Low TTV Wafer
Grinding, and Ultra Thin wafer processing down to 0.5 mils), and various cost/defectivity
reduction projects (automated microscopes, particle scanners, in line particle measurement, etc.).
Projects rage in cost from $40 Million dollars down to a few hundred thousand dollars. I am also
in charge of doing long range planning for increasing the factory to 35K wafers per week and 15K
wafer per week foundry.
ON Semiconductor ISMF Fab, Seremban, Malaysia
January 2008 to September 2009 as Process Engineering Manager. Responsible for leading a
team of 25 engineers to improve yields, capacity, and quality in a 10K wafers per week fab. Have
increased yields on the foundry business from mid 80’s to 99% plus and holding steady. Lead
team in cost reductions in 2009 of over 1.3 million dollars. Team was also very successful in
getting first pass success in transferring 6 new technologies from the ZR factory. Organized and
grew organization to enable it to support a 25K wafers per week factory with enough advance time
to allow the new engineers to skill up. Mentored section managers and engineers on the new
products to allow timely qualifications and proper process setup.
ON Semiconductor ZR Fab, Phoenix Az.,
January 2007 to December 2007 as the Photo Glass Process Engineer. Sustain and improve the
current Photo Glass process. This process is a combination of making the Photo Glass, using a
Photo process to apply the glass, and a Diffusion process to bake out and reflow the glass. To date
I have reduced the cycle time on one of the furnace processes (37 minutes removed) and reduced
many sources of variation in the mixing and application of the glass. Currently working on
combining the Pre Fire and Fire furnace processes into one process to reduce cycle time and
improve process stability. Also working on increasing the availability of the coater tracks,
reducing redo’s, and reducing scrap. Tools used in this process are atmospheric furnaces,
SVG8800 tracks, P&E 660 aligners, bake ovens, and various manual wet etches/cleans. This
factory can run up to 20,000 6” wafer starts per week with a mix of 9+ technologies.
ON Semiconductor Front End QA & Operational Excellence, Phoenix Az.
January 2006 to January 2007 as the Special Cause Event Reduction (SCER) Global Champion
and CADET Business Project Manager. SCER position is working on preventing Special Cause
Events and minimizing their impact to the company when they do occur. This is being
accomplished by information sharing, root cause issue fixing, and systems improvement. The
team also started utilizing the Best Practices Implementation (BPI) system to help with the fan-out
and fan-in of the issues and fixes. The core team is composed of members from each factory
(front end and back end) in the ON global organization. This is being accomplished by
information sharing, root cause issue fixing, and systems improvement. CADET is an event
capture system that has been deployed in COM1 from Gresham. This system enables the use of
event capture to drive resource allocation (via an RPN system) and continuous improvement.
Work is almost complete in redeveloping the CADET system for a global application that will be
fanned out to all ON Semiconductor factories for standardization and information sharing. This

3. global application is being made using the inputs of all of our global factories and working with
the ERDC team.
ON Semiconductor ONPY2 Fab, Piestany Slovakia
September 2004 to December 2005 as the 18V Bipolar Transfer & ONPY2 Expansion Project
Manager. Transfer of the 18V Bipolar line from the East Greenwich Fab (EG) to the ONPY2 Fab
with the capability to run 250 wafers per week. Team for this project was composed of members
from ONPY2, EG, and ON Corporate. Project meet all milestones per schedule, device yields
were above EG historical and the project came in under budget. While doing the project
management position I also did process setup and qualification work in the Diffusion area to help
support and keep the project on schedule. The processes included oxidations, drives, implant
optimization, RTP, EPI optimization, and wet cleans. In July of 2005, I was also appointed the
project manager for the ONPY2 expansion project. Project was to increase the Analog capacity of
ONPY2 by 400 wafers per week by the end of March, 2006. Over 23 tools were installed, started
up, and qualified with a budget of about four million dollars. When I left the project it was 2
weeks ahead of schedule, all tools hade been started up, and over one million dollars was still left
in the budget. Project required working closely with process engineering, equipment engineering,
facilities engineering, and vendors.
ON Semiconductor, Phoenix Az.
July 2004 – August 2004 as the ON Semiconductor Global Defectivity Reduction Manager
Worked with all the fab defectivity teams to reduce product defectivity issues and customer
returns related to defectivity issues. Lead a global team to setup an online defectvity level
reporting tool. Also took the plans from each of the fabs to setup a current and future defectivity
road map for the company. Did base line and bench marking of various fabs to document each
fabs current capabilities and best practices.
Lion Microelectronics, Hangzhou China
March 2003 – June 2004 as the ON Semiconductor project leader on site for the construction,
startup, qualification, and ramp up of the 6 inch Schottky Wafer Foundry Fab. Organized,
managed, trained, and mentored the whole Lion team from factory startup to factory ramp up and
sustaining. The team consisted of six staff level managers, 30+ engineers, and many supervisors
and operators (50+ individuals). Project was six months behind schedule when I arrived and I
assumed the Operations Manager position to help bring project back on schedule. Project was put
back on schedule and all goals were meet and/or exceeded. Fab was ramped up to 2000 wafer
starts per week average at the time of my departure with yields in the high 90% range and no
quality issues.
ON Semiconductor, Phoenix Az.
January 2002 – February 2003 as Quality Assurance & Manufacturing Excellence Senior Engineer
Responsible for helping both fabs and foundries in dealing with yield issues, scrap problems,
quality and reliability issues, process issues, technology transfers, etc. Part of a newly developed
team of specialists working to obtain company goals and objectives. Helped transfer the
MOSCAP line from the RF1 Motorola fab to the Z/R fab (the Diffusion processes). Lead global
team that developed the Six Sigma book used to launch the new Six Sigma/Black Belt program
emphasis for On Semiconductor.
Thyristor Fab ON Semiconductor, Keelung Taiwan
October 2001 – December 2001 as the Diffusion team leader for Thyristor Transfer Alpha Team
Responsible for identifying the alpha set equipment, removing it from production, shipping it to
Taiwan, reinstalling it, qualifying/characterizing the equipment, and running the qualification lots
To qualify the foundry fab Lite On. Lead a team of two equipment/process engineers form
Mexico and helped with the training and mentoring of the Taiwanese process and equipment
engineers on site. Tools used for this were manual benches for wet cleans and etches, atmospheric
furnaces for oxidations and drives, LPCVD furnaces for BCl3, and atmospheric furnaces for
POCl3.

4. Rectifier 6” Fab & Thyristor Fabs ON Semiconductor, Guadalajara Mexico
March 2001 – October 2001 as Diffusion Process and Maintenance Leader for Thyristor Fab
Lead a team of 5 process engineers, 10 maintenance engineers, and 2 technicians to handle the two
fabs. Team was responsible for scrap reduction (dropped 55% in the area), abort reduction
(dropped to just 2 or less aborts per month), equipment stabilization, and process stabilization
(current
Yields of the Thyristor fab show the impact of this and ongoing efforts). Supervised the
characterizations of the POCL3 and BCL3 processes to help stabilize and reduce scrap resulting
From these two processes. Redefined the PM schedules in the Thyristor fab to reduce scrap and
Aborts (also lead to a $200,000 + cost savings per year due to bad practices on old PM’s). Also
responsible for cycle time reduction, held lot reduction, and all other aspects of production. The
Thyristor area had 60 furnaces and various wet cleans and/or etches. The Thyristor fab was
running 9,000 4” wafer starts per week at the highest point.
Rectifier 6” Fab ON Semiconductor, Guadalajara Mexico
July 2000 – March 2001 as the Diffusion Section Leader
Lead team of 3 process engineers, 5 maintenance engineers, and 4 production leaders (with a staff
of 20 operators) in all aspects of the diffusion area. Reduced scrap to 0.2 scrap per 1000 turns,
reduced cycle time by over 70%, helped with the qualification of the worlds first ever 6”
Thyristors. Pushed process simplification and elimination (got rid of one oxidation step in Auto
Rectifiers and also improved the electrical performance with the change). Pushed process
capacity improvements (one of the main reasons for the excellent improvement of cycle time).
Helped with the development and qualification of TEOS free Schottkys. Helped with the
qualification of the RCA clean for Auto Rectifiers to eliminate the need for the Getter process.
Cost reduction/control and yield improvement projects were also crucial to the overall success of
the fab. The Rectifier area had 20 furnaces, one medium current implanter, and various wet cleans
and/or etches. The fab was running 5,000 6” wafer starts per week at the highest point.
Rectifier 6” Fab Motorola SPS, Guadalajara Mexico
July 1999 – July 2000 as Diffusion Process Engineer and Specialist
Part of team sent down to help bring up the new 6” Rectifier fab. Responsibilities included
training the new engineers, transferring the technologies (6” Ultra fast Rectifiers, 6” Schottky
Diodes, 6” Auto Rectifiers, and later the first 6” Thyristor), running the qualification lots,
characterizing the equipment, teaching the maintenance engineers the PM’s, etc. Developed the
6” process for the TEOS, Nitride, Oxidation, BCL3, POCL3, and Thyristor Boron drive processes.
Helped develop the 6” processes for the Pt diffusion, Al Sinter, Post Metal Anneal, Getter, Born
Redistribution, Phosphorus Redistribution, Cleans (Piranha, RCA, HF, Mega sonic, etc.), Boron
Spin, and Ni Pt Anneal processes. Helped to institute anti scrap and misprocessing elimination
programs in the diffusion area. Helped to train and certify the new operators in the area.
Zener/Rectifier Motorola SPS, Phoenix Az.
January 1998 – July 1999 as the Diffusion Process Engineering Section Manager
Responsible for leading three engineers and four technicians in successful projects for the
following: scrap reduction, process improvements, cycle time reduction, cost reductions, QS 9000
qualification, equipment up time, and equipment qualification/fab expansion. The area consists of
64 furnaces (atmospheric and LPCVD), one high current implanter, and various wet cleans and/or
etches. The fab is a high production facility (18,000 + 4” wafer starts per week) running three
different technologies (Zener Diodes, Schottky Diodes, and Ultra fast Rectifiers). Interact with all
levels of the organization to meet fab goals and generate market share.
Zener/Rectifier Motorola SPS, Phoenix Az.
July 1995 – January 1998 as a Diffusion Process Engineer
Responsible for the following processes: Boron and Phosphorous diffusion, Platinum diffusion,
BCL3 LPCVD wafer doping, Boron Spin-on Glass Doping, Low Temperature Metal Anneals, Al
Alloy junction formation, Thermal Oxidation (wet and dry), TEOS and Nitride LPCVD thin films,
Phosphorous Getter, various wet cleans and/or etches, ion implant, and various pieces of

5. metrology equipment. Have a good working knowledge of DOE. Have done many process
improvements, qualifications, consolidations, characterizations, and optimizations. Helped to get
the area set up for the 6” conversion of the line. Have worked successfully on scrap reduction,
equipment standardization, cycle time improvements, through put increases, PROMIS
implementation/programming, capacity increases, and equipment qualifications/characterizations.
Brought in and trained three process technicians, mentored two summer interns, and one COOP.
Involved in identifying and implementing new equipment for the fab expansion/scrap reduction.
Received the Extra Mile Award for work done on the new BCL3 system.
CDI (INTEL FAB 6 Laminar Airflow Project), Tempe Az.
January 1995 – July 1995 (10 hours per week)
Collect and compile airflow/particle/pressure data on clean room. Use data to improve the laminar
airflow plus helped to spot problem areas, make improvements, and suggestions for
improvements. Improve and update documentation on the entire clean room and supporting areas.
IMAG, Tempe Az.
August 1994 – July 1995 (26 hours per week)
Test technician for prototypes and sample analysis. Also responsible for failure analysis and
corrective action reports to customers, training of floor personnel in testing procedures, technical
support for Costa Rica and Mexico facilities, customer correspondence to resolve problems with
merchandise, research on new procedures/products for production, product design, customer
sample analysis, prototype/customer sample builds, and product optimization.
SKILLS Literate in PORMIS, PROMIS procedure building, JMP, and various
Furnace controller languages (TMX, SEMY, & SCSA).
Have moderate proficiency using Microsoft Project software.
Can speak, read, and write Spanish to a moderate degree of proficiency.
Can speak Chinese (Mandarin) at a beginner degree of proficiency and am currently studying the
language.

6. metrology equipment. Have a good working knowledge of DOE. Have done many process
improvements, qualifications, consolidations, characterizations, and optimizations. Helped to get
the area set up for the 6” conversion of the line. Have worked successfully on scrap reduction,
equipment standardization, cycle time improvements, through put increases, PROMIS
implementation/programming, capacity increases, and equipment qualifications/characterizations.
Brought in and trained three process technicians, mentored two summer interns, and one COOP.
Involved in identifying and implementing new equipment for the fab expansion/scrap reduction.
Received the Extra Mile Award for work done on the new BCL3 system.
CDI (INTEL FAB 6 Laminar Airflow Project), Tempe Az.
January 1995 – July 1995 (10 hours per week)
Collect and compile airflow/particle/pressure data on clean room. Use data to improve the laminar
airflow plus helped to spot problem areas, make improvements, and suggestions for
improvements. Improve and update documentation on the entire clean room and supporting areas.
IMAG, Tempe Az.
August 1994 – July 1995 (26 hours per week)
Test technician for prototypes and sample analysis. Also responsible for failure analysis and
corrective action reports to customers, training of floor personnel in testing procedures, technical
support for Costa Rica and Mexico facilities, customer correspondence to resolve problems with
merchandise, research on new procedures/products for production, product design, customer
sample analysis, prototype/customer sample builds, and product optimization.
SKILLS Literate in PORMIS, PROMIS procedure building, JMP, and various
Furnace controller languages (TMX, SEMY, & SCSA).
Have moderate proficiency using Microsoft Project software.
Can speak, read, and write Spanish to a moderate degree of proficiency.
Can speak Chinese (Mandarin) at a beginner degree of proficiency and am currently studying the
language.