1. ?
A semantic model for VHDL-AMS
Natividad MartıĢnez Madrid, Peter T. Breuer, Carlos Delgado Kloos
Universidad Carlos III de Madrid
<nmadrid,ptb,cdk>@it.uc3m.es
CHARME ā97, MontreĢal, Canada - October 1997 1
2. Objectives ?
ā¢ explain behaviour of VHDL-AMS processes
ā not a detailed syntactic mapping
ā provide sufficient primitives
ā¢ present an underlying model that . . .
ā extends existing model for VHDL
CHARME ā97, MontreĢal, Canada - October 1997 2
3. Content of the talk ?
ā¢ Introduction
ā¢ A process algebraic analysis
ā¢ Semantics
ā¢ The analog solver with example
CHARME ā97, MontreĢal, Canada - October 1997 3
4. Main idea ?
VHDL semantics analog extension
imperative
discrete-event
diff. equations
real time domain
declarative
continuous-time
Ö Ö
INTEGRATION
CHARME ā97, MontreĢal, Canada - October 1997 4
5. Name space division & Properties ?
VARIABLES assigned
instantaneously
not scheduled
SIGNALS at least Ī“-delayed preemptively
scheduled
QUANTITIES assigned
instantaneously
governed by diff. eqns.
PROCESSES invariant invariant
CHARME ā97, MontreĢal, Canada - October 1997 5
7. Semantic Domains ?
WorldLine = Time ā State
State = Id ā V alue
VHDL Statements
Semantics = (WorldLine, Time) ā (WorldLine, Time)
Time = Int
VHDL-AMS Statements
Semantics = (EqnSet, WorldLine, Time) ā (EqnSet, WorldLine, Time)
Time = Real
CHARME ā97, MontreĢal, Canada - October 1997 7
8. Parallel decomposition ?
LRM view of basic VHDL compositionality:
ā¢ processes in parallel (+ kernel)
ā¢ process body loops continuously
ā¢ imperative commands in process body run sequentially
Our view:
ā¢ no kernel
CHARME ā97, MontreĢal, Canada - October 1997 8
16. Analog solution ?
Bouncing ball example
ds
dt = v
dv
dt = āg Ā± av2
Local approximation s(t) = 1
v(t) = āgt
origin at
s = 1
v = 0
t = 0
Linear approximation (s, v) = (s0, v0) + (t ā t0)(v0, āg Ā± av2
0)
Recursion
(s, v)(t0,s0,v0)(t) ā¼
ļ£±
ļ£²
ļ£³
(s0, v0) + (t ā t0)(v0, āg Ā± av2
0) t ā [t0, t1)
(s, v)(t1,s1,v1)(t)
s1 = s0 + v0āt
v1 = v0 + (āg Ā± av2
0)āt
t1 = t0 + āt
CHARME ā97, MontreĢal, Canada - October 1997 15
17. Example ?
proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]
ds/dt == v;
dv/dt == -g + if v<0 then a else -a end * v * v;
begin
wait until s < 0;
v := -v;
s := 0 ;
end
āt = 0.02
CHARME ā97, MontreĢal, Canada - October 1997 16
18. Example Cont. ?
proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]
ds/dt == v;
dv/dt == -g + if v<0 then a else -a end * v * v;
begin
wait until s < 0;
v := 1.4142 * (g * s + 0.5 * v * v)**0.5 ;
s := 0 ;
end
g ā 0 + vā²2
2 =
g ā s + v2
2
āt = 0.06
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19. Example Cont. (II) ?
Height
Speed
āt = 0.06
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20. Unresolved areas ?
ā¢ Implementation of the parallel composition of pro-
cesses if quantities are shared between processes
ā¢ Errors in the analog solver may require us to rewrite
our program
ā¢ The proper execution of the analog solver in Ī“ time
when the processes are in parallel
CHARME ā97, MontreĢal, Canada - October 1997 19
21. Conclusion ?
ā¢ What? Extension of our VHDL semantics to cover
VHDL-AMS
ā¢ How? Embedding of the VHDL semantics in a bigger,
continuous time domain, which contains an oracular
analog solver
ā¢ Why? Clarify the draft standard document
CHARME ā97, MontreĢal, Canada - October 1997 20