VHDL Half Adder

1. First Declare Half Adder
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-- Company:
-- Engineer:
--
-- Create Date: 10:43:41 07/18/2012
-- Design Name:
-- Module Name: half_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

2. ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity half_adder is
Port ( A : in STD_LOGIC;B : in STD_LOGIC;C : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end half_adder;
architecture Behavioral of half_adder is
begin
Sum <= A xor B;
Cout <= A and B;
end Behavioral;
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-- Company:
-- Engineer:
--
-- Create Date: 10:51:44 07/18/2012

3. -- Design Name:
-- Module Name: FullAdd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FullAdd is

4. Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end FullAdd;
architecture Behavioral of FullAdd is
Component half_adder
port (A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end Component ;
signal sum1,carry1,sum2,carry2 : std_logic;
begin
half_adder1 : half_adder port map(
a=>a,
b=>b,
sum=>sum1,
carry=> carry1);

5. half_adder2 : half_adder port map(
a=>sum1,
b=>c,
sum=>sum,
carry=> carry2);
Carry<= carry1 or carry2;
end Behavioral;

6. half_adder2 : half_adder port map(
a=>sum1,
b=>c,
sum=>sum,
carry=> carry2);
Carry<= carry1 or carry2;
end Behavioral;