1. Nains Jain
Contact: +91 7406749244 / +91 9039862343
Email: nainsjain@gmail.com
ADDRESS: SRI RAM PG –Marathalli near multiplex (560037)
SYNOPSIS
A Creative and Analytically skilled Hardware and Software Professional with more than 1 Year 3
months of experience in IC Testing and Software Testing in Electronic and Software domain. Love
to take Initiative and achieve goals which are aligned to organization's road map.
EMPLOYMENT HISTORY
Organization Name: “TESSOLVE SEMICONDUCTOR Pvt. Ltd” (Sep ’2014- till now)
Location : Bangalore
Designation : IC/ VLSI Test Engineer
Project First
Title : REMORA (FSM90xx)
ATE – Verigy93000
Role: Phasing Test Engineer
BLOCK – JTAG Blocks
DESCRIPTION: The Qualcomm FSM90xx family is a single-carrier device targeting residential,
low-end enterprise and SOHO(Small office/home office) small cells. The FSM90xx 28nm system-
on-chip (SoC) is designed for neighborhood and small and medium business (SMB). It leverages
Qualcomm’s air link technology leadership to expand the capabilities, significantly lower cost and
improve power efficiency of high-performance LTE small cells. It has been designed for easy
integration with existing products including residential broadband gateways and SMB Wi-Fi routers,
so that software applications can take advantage of both cellular and Wi-Fi radios to deliver a better
end-user experience.
Phasing
Phase 0: Verifying vectors at any Voltage & Frequency.
Phase1 : Verifying vectors at Target Voltage, Frequency and Room Temp on Nominal
Materials. It is first step to prove that the design, fabrication and vector are Right. Collect the
data Vmin/Fmax, Shmoo’s.
Phase 2: Verifying vectors at Across the Voltages (LV, NV and HV), Temp (Room, Cold and
HOT), Speed and Target frequency on Nominal Materials. It is used to Screening and
Sampling the Device.
Phase 3: Verifying vectors at Across the Voltages, Temp, Speed and Target frequency on Splits
(SSS, SS, SF, FFF, FF and FS) Materials. It is used to Screening and Sampling the Device.
Project Second
Title: Estel _Shift299-74HCT299
ATE- Verigy 93000
2. Tools Used: Smartest, Eclipse
Role: IC Test Engineer
DC-Par metrics Test- Continuity Test, Leakage Test, IddQ static and DPS Short.
AC-Par metrics Test- Set-up and Hold Time, Propagation Delay, Transition Time.
Functional Testing – Shift left, Shift Right, Parallel load and Hold Data
First Company
Organization Name: “IBM Global Services
Location : Bangalore
Designation : Manual Test Engineer
Project
Title: MANTFE Tiger-8031
Tools Used: QC & QMS
Team Name: PTM
Role: Manual Test Engineer
Description: Write Test Plane, Write Test Cases, Functional and End -2 Testing, Prepare
Tractability Matrix, Prepare data log.
Academic Detail
Technical Abilities
Testing Skills : IC-Automation Testing(ATE) and Manual Testing
DFT : SAF, PDF, TDF, BST, D Algorithm and BIST
Operating System : Windows Family, UNIX and LINUX
Programming Language : C, C++, SQL, Embedded C and Arduino Language
Algorithm : Data Structure
Soft-Tool’s : Smartest Verigy93000, Eagle -Soft, Express PCB, and Turbo C
Automation Testing by “Tessolve Semiconductor Pvt Ltd. Bangalore”
Degree University/Board Percentage
B.E (ECE)
TRUBA COLLEGE OF ENGINEERING &
TECHNOLOGY
75%
H.S.C SURYODAYA H.S.SCHOOL 75%
S.S.C SURYODAYA H.S.SCHOOL 80.4%
3. Good Knowledge of ATE ( Verigy 93000) and Tool Smartest
Good Knowledge of Test Program creation and Test flow.
Good Understanding of Result Analysis Tools (Error Map and Timing Diagram)
Good Knowledge of Debug Tools (SHMOO Tool and Pin Margin)
Good Understanding of Error log.
Manual Testing by “Q-Spider Technology Bangalore”
Good Knowledge of SDLC
Good Knowledge of WBT and BBT-Function, System and Integration Testing
Good Knowledge of Acceptance, Smoke, Ad-hoc, Globalization, Compatibility, Reliability,
Recovery, Regression, Usability and Accessibility Testing
Good Understanding of Test Plane and Test Case
Good Knowledge of STLC and Defect Life Cycle
Subject of Interest
Language -C
Data structure
Digital Electronic
Electronic Device & Circuit
Network Theory
Professional Skills
Ability to work in a Team.
An Objective working person.
Well-Disciplined and Dedicated to work.
Co-curriculum Activities
Participated in Junkyard
Participate in Paper Presentation
Participated in Cricket Team
Personal Details
Name Nains Jain
Father’s Name Mr. Mahendra Jain
Date of birth 05-08-1991
Languages Known English, Hindi
Address 106, Gandhi Ward Deori Kalan Dist.- Sougar M.P (470226)
Declaration
I declare that the information furnished above is true to best of my knowledge and I bear the
responsibility for the correctness of the particulars
DATE:
NAME: NAINS JAIN