1. ACADEMIC DETAILS
WORK EXPERIENCE
JEAN JACOB
Flat No: 416, Sycon Cressida
Horamavu main road, Bangalore
Email: jjeanjacob@gmail.com
Mob: +91 8861267026
1. Texas Instruments (Sep 2014 – present)
Worked as part of digital team for Successive Approximation Register Analog-to-Digital
Converters (SAR ADC) with upto 2 Msps throughput and 18 bit resolution.
1. Mainly involved in verification of digital controller (SAR) and interface of the SAR ADC
which included creating the testplan, bringing up the testbench (systemverilog-based)
and coding testcases for :
a. Checking the digital interface protocol (SPI/I2C) features and modes including
advanced features to support the high throughput rate and resolution.
b. Verifying the register programming capabilities and associated functionalities
such as data packet configuration (for example, resolution and parity) and
number of analog input channels.
c. Checking the converted data and measuring integral and differential non-linearity
2. Worked on automating various tasks in the verification effort. For example, created a
perl script to run simulations with multiple options such as RTL/GLS,
standalone/regression and multiple frequencies.
3. Defined constraints and synthesized the controller/interface.
4. Briefly worked on RTL design and layout of the controller/interface.
2. LSI Corporation (June 2008 – July 2011)
Integrated ARM-based processor subsystems with multiple cores, memories and on-chip debug
hardware for hard disk drive SoC's.
1. Created detailed test plans and testcases for verifying subsystem functionality.
2. Synthesized CPU subsystems to meet timing requirements with minimum area
overheads.
3. Ensured timing closure of the synthesized netlist using static timing analysis.
Year Degree/Exam Institute GPA/Marks
2012-2014 M.Tech in VLSI Design Tools and Technology IIT Delhi 8.76
2004-2008 B.Tech in Electronics and Communication NIT Calicut 7.49
2003 CBSE Marian Junior College 88.4
2001 CBSE Marian Junior College 88.6

2. TECHNICAL SKILLS
IIT DELHI - PROJECTS
IIT DELHI - COURSES
EXAM SCORES
OTHER INTERESTS
4. Generated test vectors for post-silicon validation of the design on ATE with focus on
exercising timing-critical processor-memory paths.
5. Joint inventor in a power management controller for an embedded memory which was
awarded a patent (US patent no : 8713340)
6. Received a DFT award for quick isolation, root-causing and bypassing of a post-silicon
bug
7. Received a SPOT award for making contributions to the processor subsystem
development efforts.
1. HDL’s: System Verilog, Verilog, VHDL
2. Software languages: C++, Perl, ARM assembly, UNIX shells
3. EDA Tools: Cadence NC, Synopsys Design Compiler, Synopsys Prime Time, Cadence
RTL Compiler
1. Behavioral Modeling of the On-Chip AMBA Interconnect: The objective was to
create a behavioral model in systemverilog of a network interconnect supporting the
AMBA protocol suite. This would involve creating the necessary switches and queues
for a configurable number of master/slave interfaces. Traffic pattern statistics would
then be computed and analyzed.
2. Design and implementation of a Network-on-Chip(NoC) subsystem: The subsystem
designed included an NoC router and 2 functional blocks connected to it using network
interfaces. The functional blocks implemented the Open Core Protocol (OCP) interface.
The router was designed to fit into a 4:4 NoC system. It used XY routing and round-
robin arbitration. The design was verified through simulation and then synthesized.
3. Verification of an AXI Memory IP using UVM Methodology: This project, done at
Cadence, involved creating a verification plan for a memory IP with an AXI interface
and creating sequences and systemverilog assertions to implement it in an existing
UVM environment. It also required familiarization with the AXI VIP which was used as a
master, driving transactions to the memory slave.
Architecture of Large Systems, Digital Systems Lab, Functional Verification, Computer
Architecture, Operating Systems, SoC Design & Test, Synthesis of Digital Systems,
Introduction to Programming and Data Structures
GATE: 5 (Rank)
GRE: 333/340
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