A 2.4–3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique

1. A 2.4–3.6-GHz Wideband Sub-harmonically Injection-
Locked PLL with Adaptive Injection Timing Alignment
Technique
ABSTRACT:
This paper proposes a wideband sub harmonically injection-locked PLL (SILPLL)
with adaptive injection timing alignment technique. The SILPLL includes three
main circuit blocks: one-oscillator-period constant-delay (OOPCD) divider,
timing-adjusted phase detector (TPD), and pulse generator (PG). The proposed
injection timing alignment technique can align the injection timing adaptively in a
wide range of the output clock frequency using the two blocks (OOPCD and TPD)
and a falling edge locking scheme of pulses. It can avoid the risk that SILPLL may
lock to the wrong frequency or even fail to lock. The PG block is used for half-
integral injection to relax the tradeoff between the phase noise of SILPLL and the
output frequency resolution. The OOPCD circuit occupies a negligible area. After
the injection timing alignment is finished, the OOPCD is powered off so that no
extra power is consumed. The SILPLL is implemented in the 65-nm 1P9M CMOS
process. It consumes 8.6 mW at 1.2 V supply and occupies an active core area of
1×0.6mm2 . The measured output frequency range is 2.4∼3.6 GHz with an output
frequency resolution of 200 MHz and the phase noise is−127.6 dBc/Hz at an offset
of 1 MHz from a carrier frequency of 3.4 GHz. The rms jitter integrated from 1

2. kHz to 30 MHz is less than 112 fs for all the covered frequency points. Under the
supply voltage range from 1.1 to 1.3 V and the temperature range from −20 °C to
70 °C, the rms jitter variation of all the covered frequency points is less than 27 fs,
which shows good robustness over environmental variation. The proposed
architecture of this paper analysis the logic size, area and power consumption using
Tanner tool.
SOFTWARE IMPLEMENTATION:
 Tanner tool