1. 164 • 2016 IEEE International Solid-State Circuits Conference
ISSCC 2016 / SESSION 9 / HIGH-PERFORMANCE WIRELESS / 9.1
9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD
2×2 MIMO Base-Station Transceiver SoC with
200MHz RF Bandwidth
N. Klemmer1
, S. Akhtar1
, V. Srinivasan1
, P. Litmanen1
, H. Arora1
,
S. Uppathil1
, S. Kaylor1
, A. Akour1
, V. Wang1
, M. Fares1
, F. Dulger1
,
A. Frank1
, D. Ghosh1
, S. Madhavapeddi1
, H. Safiri1
, J. Mehta1
,
A. Jain1
, H. Choo1
, E. Zhang1
, C. Sestok1
, C. Fernando1
,
Rajagopal K.A.2
, S. Ramakrishnan2
, V. Sinari2
, V. Baireddy2
1
Texas Instruments, Dallas, TX,
2
Texas Instruments, Bangalore, India
Increasing mobile data demands are pushing cellular network capacity. Massive
MIMO base stations with large antenna arrays and smaller cell sizes demand
higher integration in radio transceivers than what is available [1].
We present a 45nm CMOS transceiver SoC with 4x5Gbps SerDes interface,
supporting all 3GPP bands from 400MHz to 4GHz with 200MHz instantaneous
RF bandwidth (BW). The SoC (Fig. 9.1.1) includes two transmitters (TX), two
receivers (RX), and one high-BW receiver (FBRX) for TX digital pre-distortion
feedback (DPD), antenna tuning or network listening. Three integrated RF PLLs
provide independent LO frequencies. Digital processing includes ADC decimation,
DAC interpolation, filtering, and automatic RX gain control. Calibration,
compensation, synchronization, and built-in-self-test with RF loop-back are
integrated. The SoC consumes 5W/6.5W in TDD/FDD modes at maximum
TX/RX/FBRX bandwidths of 200/100/200MHz and 40Gb/s SerDes I/O rate with
+12dBm TX RF Pout when operating at 2.7GHz. Power consumption scales with
TX power, RF BW, and SerDes rates.
The zero-IF TX (Fig. 9.1.2) incorporates a 14b segmented, current-steering DAC
clocked at nominally 1.8GHz using triple cascode current-mirror structures that
provide low noise and high linearity. The DAC noise is thermally limited and below
the overall TX noise floor of -159dBc/Hz at 40MHz carrier offset. A passive LC
reconstruction filter is used for higher dynamic range and lower power, compared
to the traditional active-RC approach. A wideband LC notch provides 50dBc
filtering of the DAC image and a peaking inductor provides droop correction. A
25% LO, passive voltage-mode mixer is driven by adjustable LO pulse edges,
obtaining better than 55dBc image suppression across 200MHz. A cascode
amplifier (PPA) provides 40dB of linear-in-dB TX power control range and dB-by-
dB DC power scaling. The PPA uses thermometer-coded unit-PPAs for digitally
controlled 1dB gain steps <+/-0.2dB DNL [2]. The number of enabled PPA units
has little impact on the overall input and output impedances, and the phase change
per dB step is <0.2deg. This is essential for beam pattern control in active antenna
array systems. Memory effects are minimized by the quasi-differential cascode
topology, Class-A biasing, and low impedance supply networks (Fig. 9.1.5). TX
noise is attenuated dB-by-dB in the first 20dB gain reduction, before reaching the
noise floor. A wideband external matching network yields high OIP3 and harmonic
filtering. TX ACLR of 54dBc is achieved for a 0dBm 20MHz LTE TM1.1 signal at
2.6GHz without crest-factor reduction (CFR). With reduced baseband signal,
ACLR improves 2dB-by-dB with back-off (IMD3 limited) until the noise floor is
reached (Fig. 9.1.3) and thereafter reduces dB-by-dB with back-off (noise limited).
At -5dBm modulated TX power, 65dBc peak ACLR is achieved. TX LO leakage is
reduced to -70dBm by periodic background calibration using the FBRX for LO
leakage estimation and I/Q-DC addition to the digital TX path.
The RX front-end (Fig. 9.1.2) consists of a programmable attenuator (ATT) with
zero-IF down converter. A switched-resistor ladder network implements 3dB gain
steps with constant 100Ω differential input impedance [3]. The ATT output current
is buffered by a CG-amplifier and steered to a 25% LO passive current-mode
mixer. A CS amplifier in parallel with the ATT provides active noise cancellation.
A 3rd
-order active-RC lowpass filter provides -1dB RF BW settings from 5MHz to
100MHz with 1dB IF gain-control steps. Dynamic range under blocking is
maximized by combining RF ATT and IF gain steps. The ADC uses a continuous-
time ΔΣ modulator [4] with variable clock frequencies up to 3.7GHz for RX spur
mitigation. The ADC consists of two stages for signal conversion and re-
quantization of the 1st stage quantization error, respectively. An inter-stage gain
of 4 suppresses 2nd
-stage noise for a theoretical SNR improvement of 12dB and
improved noise shaping after subtraction in the digital domain. The overall RX NF
is 12.5dB with a peak SNR of 73.5dB in 20MHz RF BW, not accounting for LO
noise. SFDR is limited to 73dB. External LNAs provide for 3GPP sensitivity and
relax the TX-RX isolation requirement to 70dB. Maximum gain in-band RX IIP3
of +13dBm is measured at the BW edge. NF and IIP3 scale dB-by-dB with ATT
control and dynamic range remains constant. IIP2 across +/-50MHz is >50dBm
and limited by matching. RX DC offset is reduced to the LSB-level by de-
embedding and stage-by-stage analog compensation of individual DC offsets
together with digital tracking and subtraction.
The FBRX has 200MHz instantaneous RF BW and is used for observation of
distorted RF PA output signals during TX DPD model adaptation. Higher FBRX
BW is obtained by providing extended baseband and ADC BWs while ensuring
low thermal noise in the clock path (Fig. 9.1.4). While transmitting two/three
LTE20 carriers (40/60MHz), up to 5th
/3rd
-order PA distortion components can be
captured fully within the available 200MHz TX linearization BW.
The local oscillators (LO) use ΔΣ fractional-N PLLs, integrated filters, and three
VCOs spanning from 6 to 11GHz. 400MHz-to-4GHz LO coverage is obtained using
appropriate VCO divider settings. Final divide-by-2 and 25%-duty-cycle circuits
are co-located with the mixers to minimize I/Q quadrature errors. Low phase noise
is achieved by utilizing dual-core VCOs, phase-aligned via a single multi-port coil
[5]. This results in reduced voltage swings and high device reliability. High-Vt
switching core devices reduce the period-fraction of operation in the linear region,
leading to reduced phase noise [6]. AC coupled varactor banks are used and
provide 125°C temperature lock range. A low noise 122.88MHz reference is used
to align with 3GPP symbol rates while keeping PN multiplication and reference
harmonics low. The reference voltages for the active loop-filter OTA and varactor
bias nodes are derived from a common source. Matched frequency responses
transfer reference noise to a common-mode signal across the varactor terminals
and is thereby cancelled. At 2.6GHz LO, the PLLs achieve 100Hz-to-40MHz
integrated, single-sided phase noise of -48dBc with a far-out noise floor of -
159dBc/Hz. The corresponding TX EVM for a 20MHz LTE signal is 0.5%.
A multi-carrier TX using zero-IF architecture suffers from image signals potentially
adjacent to transmitted channels. An initial analog LO pulse alignment engages
TX-FBRX loop-back and image levels are minimized by jointly tuning rising and
falling edges of the 25% TX LO signals. Since image levels depend on temperature
and carrier configuration, occasional background calibrations use the FBRX and
on-chip MCU during DPD-off cycles to lower the wideband image response below
TX ACLR to typically -65dBc, without disruption to the ongoing transmission. The
TX signal is observed at two deliberate FBRX LO phases, allowing the de-
embedding of FBRX and TX image responses and the adaptation of digital FBRX
post- and TX pre-compensation filters (Fig. 9.1.5) [7]. In the RX, background
adaptation of digital post-compensation filters suppresses image signals to -
80dBc.
The 7x7mm2
SoC uses a 45nm low-leakage CMOS process and a 13x13mm2
flip-
chip BGA package. It uses 1.1V, 1.8V and 2.5V/2.7V supplies and contains an
ARM M4F processor for control, calibration and compensation (Fig. 9.1.7).
Acknowledgements:
The authors acknowledge F. Dantoni for system support, A. Banerjee, S.
Finocchiaro, D. Hsieh, S. Joginipally, H. Nagalla, M. Rao, V. Ravinuthula, S.
Sankaran for design help, A. Duraisamy, A. Soundaraj, S. Thangham, B. Wu for
measurements, N. Acharya, S. Aluri, U. Kumar, R. Puri, S. Singhal, S. Velpuri for
verification, and A. Radhakrishnan, S. Sangameswaran for EDA support.
References:
[1] E. G. Larsson et al., “Massive MIMO for Next Generation Wireless Systems,”
IEEE Communications Mag., vol. 52, no. 2, pp. 186-195, Feb. 2014.
[2] S. Akhtar et al., “Analog Path for Triple Band WCDMA Polar Modulated
Transmitter in 90nm CMOS,” IEEE Radio Frequency Integrated Circuits Symp.,
pp. 185-188, 2007.
[3] D.L. Kaczman et al., “A Single-Chip Tri-Band WCDMA/HSDPA Cellular
Transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp.1122-1132, May 2006.
[4] V. Srinivasan et al., “A 20mW 61dB SNDR (60MHz BW) 1b 3rd-Order
Continuous-Time Delta-Sigma Modulator Clocked at 6GHz in 45nm CMOS,”
ISSCC Dig. Tech. Papers, pp. 158-159, Feb. 2012.
[5] Z. Deng et al., “A 4-Port-Inductor-Based VCO Coupling Method for Phase
Noise Reduction,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp.1772-1781, Aug.
2011.
[6] H. Arora et al., “High performance LC-VCOS for 3GPP base station
transceivers,” IEEE 12th Int. New Circuits and Syst. Conf., pp. 417-419, June
2014.
[7] L. Ding et al., “Joint Transmit and Receive I/Q Imbalance Compensation,” US
Pat. 8,311,083, Nov. 13, 2012.
[8] J. Platz et al., “A Direct Up-Conversion Transmitter with Integrated Prescaler
for Reconfigurable Multi-Band/Multi-Standard Base Stations,” IEEE Radio
Frequency Integrated Circuits Symp., pp. 487-490, June 2005.
[9] J. Ryynänen et al., “WCDMA multicarrier receiver for base station
applications,” IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1542-1550, July
2006.
978-1-4673-9467-3/16/$31.00 ©2016 IEEE

2. 165DIGEST OF TECHNICAL PAPERS •
ISSCC 2016 / February 2, 2016 / 8:30 AM
Figure 9.1.1: High level block diagram. Figure 9.1.2: RX RF schematic (top) & TX RF schematic (bottom).
Figure 9.1.3: TX ACLR vs. back-off and PPA gain control (left) and TX output
spectra (1x LTE20, 3x LTE20), (right).
Figure 9.1.5: RX spectrum 1x LTE5 (top) and TX spectra with 1x LTE10 and 10x
LTE20 (bottom). Figure 9.1.6: Comparison table.
Figure 9.1.4: RX NF, IIP3 for RX (left) and LPF bandwidths for RX (right, top)
and FBRX (right, bottom).
…
…
…
DAC
RDAC
CN
LN
CP
LS
DAC
RDAC
CN
LN
CP
LS
I-Path
Q-Path
14b
LOI+
LOQ+
LOI-
LOQ-
VB1
I+
Q+
I-
Q-
VB2
en[511:0] …
…
…
VCAS
TX+
TX-
50
Off-Chip Match
S1a
R1 R1 R1
R2 R2 R2 R2 R3
R1 R1 R1
R2 R2 R2 R2 R3
S2a S3a S9a
S1b S2b S3b S9b
…
…
…
…
RF+
RF-
R0 R0
CGB CGB
CMFB
Q1bQ1a
ref
CK
CK
VB2
S0bS0a
VB1
Q2bQ2a
CK
CK
TX
RX
-30
-25
-20
-15
-10
-5
0
5
-70
-65
-60
-55
-50
-45
-40
-35
-30 -25 -20 -15 -10 -5 0
TXCarrierPower[dBm]
ACLR[dB]
Digital Baseband Back-Off [dB]
20MHZ LTE ACLR 20MHz LTE Pout
-30
-22.5
-15
-7.5
0
7.5
15
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
-40 -35 -30 -25 -20 -15 -10 -5 0
TXCWPower[dBm]
GainError[dB]
TX PPA DGA Setting [dB]
Gain Error (DNL) CW Pout
0dBm TX Pout
0dBm TX Pout (composite)
TX
2.6GHz
TX
2.6GHz
10
15
20
25
30
35
40
45
0 5 10 15 20 25 30
NoiseFigure[dB]
RX Front End RF Attenuation [dB]
Room Hot Cold
10
15
20
25
30
35
40
0 5 10 15 20 25 30
InputIP3[dBm]
RX Front End RF Attenuation [dB]
Room Hot Cold
-70
-60
-50
-40
-30
-20
-10
0
10
1 10 100
NormalizedAttenuation[dB]
RX Baseband Frequency [MHz]
2.5 MHz
5 MHz
10 MHz
20 MHz
40 MHz
50 MHz
-50
-40
-30
-20
-10
0
10
1 10 100
NormalizedAttenuation[dB]
Feedback RX Baseband Frequency [MHz]
10 MHz
20 MHz
40 MHz
60 MHz
80 MHz
100 MHz
RX
2.6GHz
RX
2.6GHz
RX
FBRX
1x LTE5 @ 2.6GHz
Image
Signal
DC
RX
-77.7dBFS
-11.0dBFS
-76.6dBFS
-76.3dBFS
-77.5dBFS
1x LTE10
TX QMC off
TX QMC on
10x LTE20
-2dBmTOT
-53.5dBc
200 MHz
TX
2.6GHzTX
0.9GHz
Specification This work Platz [8] Ryynänen [9] Units
Technology 45nm CMOS 350nm SiGe 250nm SiGe
Architecture zero-IF RX & TX zero-IF TX low-IF RX
TX
Comment
TX only, no DAC, no
digital, no PLL -
Frequency Coverage 400-4000 400-2700 - MHz
Modulation 60MHz (3x LTE20) 5MHz WCDMA -
Frequency 2.6 2.6 - GHz
Power 0 (composite) -3 - dBm
ACLR -54 -59 - dBc
EVM 0.5 (1x LTE20) 2 - %
Noise -159 -154 - dBm/Hz
Power 0.5 (a) 1.1 - W
RX
Comment
With off-chip LNA
(b) -
Incl. LNA, no ADC,
no digital, no PLL
Frequency coverage 400-4000 - 1500-2500 MHz
Setting Max gain - Max gain
Frequency 2.6 - 2 GHz
IF Bandwidth 2.5-50 - 10 MHz
NF 2 (b) - 3 dB
IIP3 –4 (b) - –12 dBm
Power 0.2 (c) - 0.5 (d) W
(a) TX only, without DAC, same content as [8]
(b) External LNA: 18dB gain, 1.1dB NF
(c) RX only, without ADC, same content as [9]
(d) LNA power 35mW de-embedded
9

3. • 2016 IEEE International Solid-State Circuits Conference 978-1-4673-9467-3/16/$31.00 ©2016 IEEE
ISSCC 2016 PAPER CONTINUATIONS
Figure 9.1.7: Die micrograph.
Serdes #1
Serdes #2
Serdes #3
Serdes #4
RX #1
RX PLL
RX #2
FB PLL
TX PLL
FBRX TX #2 TX #1
GPIO
CLK GEN