design and analysis of voltage controlled oscillator


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design is done using virtuoso tool by cadence in 180 and 45 nm

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  • Reversed pn junction can be served as varactor and voltage dependent is expressed as equationdepend on Co zero bias value,VR reversed bias voltage,built in potential
  • design and analysis of voltage controlled oscillator

    1. 1. DESIGN OF VOLTAGECONTROLLED OSCILLATOR(LOW POWER CONSUMPTION AND LOW PHASE NOISE)1Group No.28 Supervised By-Saurabh Kumar Mr.Navaid Zafar RizviVaibhav JindalSharad Sharma
    2. 2. CONTENT• Motivation.• Introduction.• Design of VCO.• Basic parameters of VCO.• Base Paper.• Objective.• Tool Used.• Design Implemented.• Results Achieved.• Future Work & Time Plan.• References. 2
    3. 3. 3MOTIVATION• Now a days communication is most necessary thing inthe world.• Our aim is to make communication device of lowcost, less power consuming and Noise free.• As Voltage Controlled Oscillator is used on both endsof Communication.• Or, we are trying to design a Voltage controlledOscillator which Consumed less power and having alow phase noise
    4. 4. 4INTRODUCTION• A voltage controlled oscillator is a device thatprovides a varying output signal whose frequencycan be adjusted over the range controlled by D.C.voltageVoltage ControlledOscillatorVcont ωout
    5. 5. Specifications of Ideal Voltage Controlled Oscillator1. VCO is of Low Noise.2. Low Power Consumption.3. High Packing Density.4. High Frequency.5. Wide tuning range.5VOLTAGE CONTROLLED OSCILLATOR
    6. 6. • Noise is injected into an oscillator will disturb boththe amplitude and frequency of oscillation.• Amplitude noise is usually unimportant but Phasenoise, on the other hand, is essentially a randomdeviation in frequency which can also be viewed as arandom variation in the zero crossing points of thetime-dependent oscillator waveform..6OSCILLATOR PHASE NOISE
    7. 7. 7• Ring Oscillator Topology• Relaxation Oscillator Topology• Advantages-Easy to fabricateLow powerSmall dice area occupancyWide tuning range.• Disadvantage-As frequency increases phasenoise performance degrades.• LC Tank Oscillator Topology• Crystal Oscillator Topology• Advantages-Low phase noise performance athigh frequency.• Disadvantage-Not suitable in fabricationHigh power consumptionSmall tuning rangeWave form Oscillators Resonant OscillatorsDIFFERENT OSCILLATORS DESIGN
    8. 8. • In this Topology oscillation frequency is decided byL and C used in tank circuit of oscillator.• Oscillation Frequency fosc =• Only Inductor and Capacitor value has to varyoscillation frequency.• It is not easy to vary the value of L in monolithicinductor, but we can change C by using Voltagedependent capacitor (varactors).8LC OSCILLATOR TANK TOPOLOGY
    9. 9. • “Layout Design of LC VCO with Current Mirror Using 0.18μm Technology”• Namrata Prasad and Radheshyam Gamad• Department of Electronics & Instrumentation Engineering, ShriG. S. Institute of Technology and Science, Indore, India.• Presented in Scientific Research Journal on WirelessEngineering and Technology, in 2011.• This paper presents a new design of complementary metal oxidesemiconductor voltage controlled oscillator (CMOS VCO) forimprove tuning range and phase noise with low powerconsumption. 9BASE PAPER
    10. 10. Our objective is to implement our Base paperfirst in 180nm technology and then in 45nmtechnology, and to achieve results better than ourbase paper i.e. lower phase noise. We willaccomplish this task by designing an efficientlayout which requires less metal contacts.10OBJECTIVE
    11. 11. • Cadence Virtuoso.• It is a Circuit simulator tool which provides capabilities ofdesigning the circuit, testing of circuit, designing oflayout and its verification.• It has a feature named Analog Design Environment(ADE).• It also support tools like ASSURA, CALIBAR, ICE andwith the help of these tools we can have different checkson our schematic like DRC, LVS.11TOOL USED
    12. 12. 12VCO DESIGN STEPS IN TOOL• According to designing parameters add a predefinelibrary(gpdk180& gpdk45) to project• Design a schematicMade a symbol for schematic.• Testing and VerificationDraw a test circuit schematic.SimulationAnalysis of Phase noise• Layout DesignTesting and verification
    13. 13. • Easy to learn and enter data.• Simulation set-ups can be reused.• Quick analysis of multiple simulation data.• Cross probing support for both schematics and layouts.• Multiple measurement syntaxes supported.• Batch scripting waveform display.• Supports multiple Y-axes, strip plots, and Smith Charts.• Built-in waveform calculator.13FEATURES OF VIRTUOSO
    14. 14. • Design aims at minimizing the phase noise of oscillatorcircuit.• Circuit is a combination of both cross coupled VCO andbalanced VCO.• Due to the combination of two configuration and a LC tankcircuit it produces lower phase noise.• This configuration also helps in reducing the chip size.• Power consumption is minimized by using two differentcurrent mirrors.14VOLTAGE CONTROLLED OSCILLATOR DESIGN
    15. 15. 15VOLTAGE CONTROLLED OSCILLATOR DESIGN• In first VCO Schematic-Using Current SourceTail has large Capacitance• In Second VCO Schematic-Using NMOSTail Current Source has anoise at 2ω0• In Third VCO Schematic-Using Current MirrorNo large Capacitance
    16. 16. 16180 nm VCO Schematic4 N-MOS4 P-MOS3 1pF Capacitors1 1nH Inductor
    17. 17. 17VCO TEST CIRCUIT
    19. 19. 19SIMULATION RESULTS(POWER CONSUMPTION)Calculated Power Is4.708*10-3
    21. 21. 21SIMULATION RESULTS COMPARE WITH BASE PAPERParameters Namrata Prasad et al Proposed VCOResultsGeneral VCO(Without currentmirror)Propose VCO(With currentmirror)(VCO withCurrentMirror)Operating Voltage 2V 2V 2VTechnology(CMOS) 0.18um 0.18um 0.18umPower Consumption 12.72mW 7.40mW 4.7mWOperating Frequency 3.3GHz 3.3GHz 3.3GHzPhase Noise (dBc/Hz) 63.7 at 100MHz -155.78 at 100MHz -128 at 1MHzPhase Margin 180 180 180
    22. 22. 22LAYOUT
    23. 23. • Layout implementation of present 180nm circuit usingminimum possible metal contacts, which will help inreducing power loss.• Designing of schematic and test circuit of presentcircuitry in 45nm technology and performing testanalyses.• Layout implementation in 45nm technology.• Performing Power and Noise analyses of the circuits.23FUTURE WORK
    24. 24. • Completion of 180nm design---> 1st week of April• Completion of 45nm design ---> 3rd week of April• Completion of final Analyses ---> 4th week of April24TIME PLAN
    25. 25. • Namrata Prasad and Radheshyam Gamad, “LayoutDesign of LC VCO with Current Mirror Using 0.18 μmTechnology”, Scientific Research Journal on WirelessEngineering and Technology, 2011.• N. Prasad, R. S. Gamad and C. B. Kushwah, “Design of a2.2 - 4.0 GHz Low Phase Noise and Low Power LCVCO,” International Journal of Computer andNetwork Security, 2009.• B. Razavi, “Deign of Analog Complementary MOSIntegrated Circuits, Edition 3” Tata McGraw-Hill, Delhi, 2002.• P. Dudulwar, K. Shah, H. Le and J. Singh, “Design andAnalysis of Low Power Low Phase Noise VCO,” 13thIEEE International Conference on Mixed Design ofIntegrated Circuits and Systems,2006.25REFRENCES
    26. 26. Thank You? ? ?26