Indraneel Vijay Suryavanshi has completed his M.Tech in VLSI Design from VIT University, Vellore in 2015 with an 8.56 CGPA. He has a B.E. in Electronics and Telecommunication from Vidya Pratishthan's College of Engineering, Baramati in 2012. He has work experience in VLSI domains including digital design, RTL design and verification, and physical design. He has published papers on low power SRAM design using FinFET transistors and design of a 1-bit full adder using FinFET. His projects include SRAM cell design using FinFET, UART design with physical design flow, and implementation of a RISC

1. VELLORE INSTITUTE OF TECHNOLOGY
VELLORE,TAMILNADU
INDIA
MR. INDRANEEL VIJAY SURYAVANSHI
M.Tech in VLSI Design, Mobile-09226223425/08380984455
At Post-Tasgaon,Tal-Tasgaon,Dist-Sangli, Email: indar1991@gmail.com
Maharashtra-416312.
OBJECTIVE:
To acquire a challenging position in VLSI domain where I can effectively contribute my skills &
boost my knowledge.
EDUCATION:
University/ Board/ Institute Name Degree Stream/Subject Year of
passing
Percentage/C
GPA
VIT University, Vellore M.TECH. VLSI Design 2015 8.56 CGPA
(First Class-
Distinction)
Vidya Pratishthan’s College of
Engineering, Baramati
(Pune University)
B.E. Electronics &
Telecommunication
2012 61.43%
(First Class)
Vivekanand Arts, Sardar
Dalipsingh Commerce & Science
College, Aurangabad
HSC Physics, Chemistry,
Maths, Electronics,
English
2008 76.33%
(First Class-
Distinction)
Guruvarya Dadoji Kondadev
Sainik School, Tasgaon (Kolhapur
Board)
SSC English, Algebra,
Geometry, Science
2006 90.93%
(First Class-
Distinction)
PUBLICATIONS:
[1] “Low Power SRAM Design using Independent Gate FinFET at 30nm Technology”, Paper
published in 2014 First International Conference on Computational Systems and Communications
(ICCSC),17-18 December 2014,Trivandrum, 978-1-4799-6013-2/14/$31.00 ©2014, IEEE.
[2] “Design of 1-bit Full Adder Using FINFET”, International Journal of Applied Engineering Research,
ISSN 0973-4562, Volume 8, Number 19, 2013, Page No. 2403-2406, SCOPUS.
TECHNICAL SKILLS:
 EDA Tools:
 Cadence Tools- Virtuoso Spectre Circuit Simulator, Virtuoso Schematic Editor, NCLaunch,
RTL Compiler, SoC Encounter, Virtuoso Analog Design Environment, Layout Editor, Assura
 Mentor Graphics Tools- ModelSim-Altera 6.6d, Altera-Quartus II
 Hardware Description Language- Verilog HDL
 Scripting Languages- PERL, TCL
 Software Languages- C, JAVA
 FPGA Hardware Kit- Altera Cyclone II Design Kit
 Device Modelling & Simulation Tool- Silvaco TCAD
 Platforms- Windows, Linux
 Thorough knowledge of Static Timing Analysis
 Thorough knowledge of ASIC Design Flow & Physical Design
AREA OF INTEREST:
 Digital Design
 RTL Design & Verification
 Physical Design
 Device Modelling and Simulation(Nano scale devices)

2. PROJECTS:
Circuit Design Projects:
1. SRAM Design using FINFET
Tools Used- Cadence Virtuoso Analog Design Environment, Cadence Virtuoso Spectre Circuit
Simulator
Conventional 6T SRAM cell is implemented using FINFET(30nm). Conventional 6T
orientation is changed for changing threshold voltages of transistors. Leakage power, dynamic
current, dynamic power, access time are measured for conventional 1-bit SRAM cell & modified 1-
bit SRAM cell. Modified 1-bit SRAM cell showed better outcome.
2. Design of 1-bit Full Adder using FINFET
Tools Used- Cadence Virtuoso Analog Design Environment, Cadence Virtuoso Spectre Circuit
Simulator
FINFET (30nm) technology is used to implement addition operation. 1-bit full adder is
implemented using FINFET. Boolean expression is used for implementation. Leakage power,
dynamic current & dynamic power is measured.
Digital Design Projects:
3. UART Design with Physical Design
Tools Used- Cadence RC Compiler, Cadence NCLaunch, Cadence SoC Encounter, ModelSim-Altera
6.6d
The UART is designed using Verilog HDL. It has transmitter module & receiver module. The
data is successfully received on receiver side. Synthesizable code is taken for physical design.
Cadence RC compiler & Cadence encounter tools are used for synthesis,floorplan, placement,
routing.
4. Master Thesis-
Serial-Peripheral Interface Bus Protocol with Built-In-Self-Test Capability
Tools Used- ModelSim-Altera 6.6d, Altera-Quartus II
SPI bus protocol is implemented using Verilog HDL. Additional module is designed &
attached to SPI module, BIST module, to overcome challenges like cost for testing, level of
testing, testing equipment etc. This minimizes effort of testing SPI module separately. FPGA
EP2C20F484C7 is used.
5. Conventional Shift-Add Multiplier & Bypass Zero-Feed A Directly Multiplier(BZ-FAD)
Tools Used- Cadence RC Compiler, Cadence NCLaunch, ModelSim-Altera 6.6d, Altera-Quartus II
Cadence RC compiler tool is used for synthesis, power consumption measurement. Power
consumption of two multipliers is compared. BZ-FAD consumed less power.
6. Implementation of RISC Stored Program Machine
Tools Used- ModelSim-Altera 6.6d, Altera-Quartus II
Machine has modules as, a processing unit, a control unit, a memory. Instructions are
fetched from memory, decoded & executed. The processor is designed using ModelSim software.
FPGA EP2C20F484C7 is used.
Device Modelling Projects:
7. Process Variation Study of Cylindrical Field Effect Transistor
Tools Used- Silvaco TCAD
Cylindrical FET is fabricated virtually using TCAD. Impact of variation of channel doping
concentration, source/drain doping concentration, gate oxide thickness, channel radius and work
function on threshold voltage, Ion current, Ion/Ioff ratio and sub-threshold swing is analysed.
Image Processing Projects:
8. Face Detection in Live Video Stream using OPEN CV
Tools Used- OPEN CV, Linux(Platform Used-Linux Commands)
Linux system is used. Video is taken through a camera on a system. Frames are taken
from video. These frames are processed to detect faces in it.
ACHIEVEMENTS & EXTRA CURRICULAR ACTIVITIES:
 Presented paper on low power SRAM design using independent gate FINFET at international
conference, Trivandrum.
 Presented paper on design of 1-bit full adder using FINFET at SET conference, VIT University Vellore.

3.  Papers published in IEEE(Low power SRAM design) and SCOPUS(1-bit Full Adder design).
 EC-GATE-2013(Graduate Aptitude Test in Engineering) qualified with score of 443.
 Attended seminar on “Robotics and IC engine car” at VPCOE, Baramati, Pune.
 Achieved the gold level in United minds 2011-12 conducted by IIM Bangalore Vista & Unitedworld
School of Business at IIM, Bangalore.
 Winner at district level volleyball game competition, runner-up team at regional level.
 First prize for short drama at intra-college drama competition, Baramati.
DECLARATION:
I hereby declare that the above information is correct up to the best of my knowledge and I bear
responsibility for the correctness of the above mentioned particulars.
PLACE: Bangalore INDRANEEL VIJAY SURYAVANSHI