1. Neeraj Mishra
M. Tech (Microelectronics and VLSI)
Registration No: M.Tech/MeV/13534009/2015
Email: neerajrailtel@gmail.com Indian Institute of Technology Roorkee
Area(s) of Interest: Analog Design and Digital Design/Verification/Validation
Educational Details:
Degree Year of
Passing
Institute/ Board/ University CGPA/ % /
Grade
M. Tech (Microelectronics
and VLSI)
2015 Indian Institute of Technology
Roorkee
7.2
Executive MBA (Project
Management)
2012 Karnataka State Open
University (Distance Mode)
A
B. Tech (Electronics and
Communication Engg)
2008 Institute of Technology and
Management, Gorakhpur
65.45%
Intermediate (XII) 2003 Army School, Gorakhpur 75.2%
SSC (X) 2001 Army School, Gorakhpur 78%
Publication(IEEE VDAT Conf)
Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, and Anand Bulusu,
“Pre-layout Estimation of Performance and Design of Basic Analog Circuits in Stress Enabled
Technologies” IEEE VDAT Conf. 2015 .
Abstract: In stress enabled technologies the drive strength of multi-fingered (MF) transistors
varies with the number of fingers (NF) because of Layout Dependent Effect (LDE). This is an
important issue because MF transistors are widely used in integrated circuits. In this paper, we
investigate performance variability issues in basic analog building blocks, such as current
mirrors, common source amplifiers, and single ended differential amplifiers, designed using MF
transistors. We observe that, due to the layout dependent channel mechanical stress, the analog
performance parameters of these building blocks vary significantly.We model these variations as
a function of NF in MF transistors since performance predictability in analog circuits is
important. Finally, we designed a common source amplifier considering the impact of channel
length on channel stress.
Job Experience (5 Years-Telecom Domain)
Alcaltel Lucent Managed Solution Pvt Ltd
O & M Engineer (March 17, 2011 – April 30, 2013)
Roles:
1. Preventive / Breakdown maintenance of cell sites & OFC media.
2. Implementation of health, safety & well-being policy at sites & daily operations.
3. Operation and maintenance of switch for alarms, faults/ abnormal conditions of BSC & BTS.
4. Knowledge of E1 connection from DDF and from DDF to switch.
5. Call testing on all cell site.
RailTel Corporation of India Ltd (PSU under Ministry of Railways)
Engineer (June 25, 2008 – March 16, 2011)

2. Roles:
1. Leasing of Infrastructure services such as dark fibre, Co location, tower space etc under IP -1
license.
2. TDM leased lines, data IP services & VPN services under ISP, VPN & NLD license.
3. Project related to optical fibre laying.
4. Installation of different STM networks through optical fibre.
Projects
M. Tech Dissertation (Indian Institute of Technology Roorkee)
Mechanical stress aware design and layout of basic analog building blocks (May,14 -June,15)
The impact of mechanical stress on the analog circuit and existing MOSFET model is also
enhanced to capture the effects of stress on mobility and its effect of threshold voltage. With the
enhanced model, the influence of mechanical stress on the performance of real circuits and
establish corresponding optimization strategies.
 The stress effect facilitate the device performance booster as the device size reduces.
 Design of common source amplifier with constant current and its methodology and give
empirical relationship between change in channel length and different parameters eg
required width of driver, gain, transcoductance, output resistance to find the optimum
value.
 Design methodology, designing & modelling of the differential amplifier and give
empirical relationship between change in channel length and different parameters eg
required width of driver & tail, gain, transcoductance, 3-dBfrequency, output resistance
to find the optimum value.
 Design Methodology for designing of the 2 stage operational amplifier and its empirical
relationship between change in channel length and different parameters eg required width
of driver & tail, gain, transcoductance, 3-dBfrequency, output resistance, gain bandwidth,
RHP Zero, output pole to find the optimum value.
Tools Used: TCAD(S-Process), Perl, H-Spice, GNU plot
M. Tech Seminar (Indian Institute of Technology Roorkee)
Impact of systematic variation on analog circuit’s performance
Different from the intentionally introduced stresses to improve circuit performance,
 The shallow-trench-isolation (STI) stress, which is exerted by STI wells on the active area
of devices, is a by-product of the fabrication process and has increasingly significant impact
on the circuit behavior.
 Also we can use eSiC/eSiGe and cESL/tESL (Etch Stop Liner) as the performance booster
to enhance the mobility.
 In this analysis, we studied the impact of systematic variation on the analog circuit, and
existing MOSFET model is also enhanced to capture the effects of stress on mobility, and
its effect on threshold voltage.
 With the enhanced model, we are able to study the influence of layout-dependent stress on
the performance of real circuits and establish corresponding optimization strategies.
Course Dissertation (Indian Institute of Technology Roorkee)
Design of UART using VHDL (January, 2014 - March, 2014)
Universal asynchronous receiver transmitter (UART) is a kind of serial communication protocol,
mostly used for short-distance, low speed, low cost data exchange between computer and
peripherals. UARTs are used for asynchronous serial data communication by converting data from
parallel to serial at transmitter with some extra overhead bits using shift register and vice versa at
receiver.
Tools Used: VHDL

3. Graduation Project (Institute of Technology and Management, Gorakhpur)
Automatic guided vehicle with auto collision sensor & route changer (Dec,07 -June, 08)
This project involves the design of a vehicle with a sensor which senses the obstacle that comes
in the path and then automatically change the position. It is fully guided by the computer. We have
to give the path and the vehicle traces the path automatically to do their work lucidly.
Skills and Achievements
Computer languages Verilog, VHDL, Perl
Software packages Sentaurus TCAD, Tanner tools, SPICE
Academic Achievements 1. AIR 346 in GATE 2013.
2. Qualified to 2nd
round in 3rd
national science Olympiad, 2001-02.
3. AIR 509 in 2nd
national science Olympiad.
Languages Known English (SRW), Hindi (SRW)
Personal Details
Father’s Name Kripa Shankar Mishra
Date of Birth Oct. 18, 1986
Gender/Cat Male/ General
Contact No. 09026133335/09695074838
Permanent Address H No. 348, Near B N Public School, Madhoopur, Surajkund, Gorakhpur -
273015
References
Dr. Bulusu Anand Dr. Brajesh Kumar Kaushik
Associate Professor Associate Professor
IIT Roorkee IIT Roorkee
anandfec@iitr.ernet.in bkk23fec@iitr.ernet.in
+91-1332-245347 +91-1332-628566