1. Hyun Yoon
970 e Vermont Dr., Gilbert AZ 85295
(954)801-2170, yoonhyun@hotmail.com
OBJECTIVE Seeking a challenging circuit designer position in a competitive organization where I
can use my technical and analytical skills.
EDUCATION M.S., Electrical and Computer Engineering. August 1999. University of Florida,
Gainesville, FL.
B.S.,Physics, February 1989. Yonsei University, Korea.
EXPERIENCE Senior Staff IC design Engineer, Freescale Semi. Inc. 9/2010 - present
1. ZigBee and BlueTooth Tranceiver design.
• Build receiver line-up model from LNA to PMA(post mixer amplifier) to estimate
the noise figure for the line-up as well as to define the noise contribution from
individual block.
• Design poly-phase filter to generate I/Q signal from RF side.
• Developed and designed I/Q calibration scheme.
• Designed third order complex GmC filter to remove image signals, in which the
center frequency is 2MHz and bandwidth is 1.8Mhz.
• Define DC offset correction specification and its circuits.
• Design post mixer amplifier. It has 150MHz bandwidth, 1.5nA/
√
Hz noise,
0.5mA current consumption and 8 bit DC offset correction current steering DAC.
• Design 2nd
order baseband filter. Its OTA has 150MHz bandwidth, 2.5nA/
√
Hz
noise, 0.3mA current consumption and 6 bit DC offset correction current steering
DAC.
• Worked as Rx design lead to define the circuit topology and current consumption
within the sensitivity limit.
• Design VCO for Rx LO signal and TX dual port modulation.
• Simulate PLL two port modulation with simulink(modulating divider and VCO
to get flat response over entire modulation bandwidth).
• Design clip detector circuit for automatic gain control loop(AGC).
Staff IC design Engineer, Fujitsu Wireless 5/2009 - 9/2010
1. LTE, multi mode(2G, 3G and UMT) tranceiver(qualified for merchent market):
• Developed the phase noise model simulation in spice to define the noise specs for
individual blocks.
• Designed phase detector, loop filter and programmable dividers for PLL.
• Integrate, simulate and tested a whole fractional synthesizer.
• Designed and simulated functional Verilog AMS models for synthesizer circuit
blocks such as VCO, phase detector, divider, lock monitor, loop filter and regu-
lators.
Staff IC design Engineer, Freescale Semi. Inc. 5/2005 - 5/2009
1. Moto-Talk, 900MHz tranceiver for push to talk application(qualified for merchent
marcket):
• Designed, simulated and tested a 915 MHz LNA with 90 nm CMOS technology.

2. • Designed, simulated and tested a direct conversion passive doubly balanced Mixer
with 90 nm CMOS technology.
• Designed, simulated and tested a divider circuit and a quadrature generation
circuit for Mixer LO.
2. Kaibab, 2.4 GHz tranceiver for a wireless LAN application(qualified):
• Designed, simulated and tested a very low current( less than 1 mA) divider and
buffer for the quadrature generation circuit for Rx/Tx path.
Senior IC design Engineer, Motorola Inc. 3/2000 - 5/2005
1. MC-13377, IF I-Q demodulator in 0.4 um BiCMOS technology (qualified for mer-
chant market):
• Designed and tested a wide band differential LNA working from 50 MHz to 500
MHz with current consumption of less than 3 mA.
• Designed and tested an temperature compensated Automatic gain control(AGC)
circuit with 70 dB gain control range.
• Designed a Power on reset circuit.
• Simulated the full receiver path for MC-13377 chip and fixed problem of gain
variation over temperature by adjusting LNA and Mixer gain over temperature.
• Made a specification spread sheet using Excel, which estimates overall specifica-
tion from the given specifications of an individual block.
• Fixed Mixer DC offset problem.
2. MC-Sidewinder, 3G tri-mode (GSM, WCDMA, EDGE) direct conversion transmit-
ter in 0.18 um BiCMOS process (qualified for merchant market):
• Designed and tested a current cutback circuit for MC-sidewinder which generates
various shape of current to save the current in low power transmit case.
• Worked on Momentum simulation for the inductor of the VCO using ADS and
compared it with measurement.
• Designed and tested an automatic gain control circuit for MC-sidewinder chip,
which has 70 gain control range.
3. MC-Capella, Wireless LAN application (cancelled):
• Integrated and simulated an 8 bits pipeline ADC. It comprises three stages(4,3,3)
pipelined converters, with digital error correction.
• Designed a high speed fully differential OPAMP for switched capacitor used in
ADC.
• Designed a 10 bit accurate sample and hold circuit.
Publications • Zhenbiao Li, H. Yoon Feng-Jung Huang, O, K. K. ”5.8 GHz CMOS T/R switch
with high and low substrate resistances in a 0.18-/spl um CMOS process” Mi-
crowave and wireless component letter, IEEE, Volume 13 issue 1, Jan. 2003.
• Hyun Yoon, K. Kim, K. O, ”The measurement of Interference effects between
dipole antenna and packaging metal plate on various silicon substrate” Interna-
tional symposium on antennas and propagation, 2000.
• Daniel Bravo, Hyun Yoon, Kihong Kim, Brian Floyd, and K. O, ”Estimation of
Signal to Noise Ratio for On-Chip wireless clock signal distribution” International
Interconnection symposium, 2000.

3. • Kihong Kim, Hyun Yoon, ”On-Chip Wireless Interconnection with Integrated
Antennas”, International Electron Device Meeting, 2000.
• K.K. O, K. Kim, B. Floyd, and H. Yoon, ”A Feasibility Study for Inter and In-
tra Chip Wireless Clock Signal Distribution using Microwave” IMPS Advanced
Technology Workshop on Next Generation IC and Package Design, 1998.
CAD
Test Equippment
HSpice, PSpice, Cadence, Verilog-AMS, Veloce-RF, Matlab, SimuLink, HP-ADS. Vec-
tor Network Analyzer, Spectrum Analyzer, PLL Analyzer, and other HP high frequency
equipments.