Logic gates

Digital Electronics
Dr. Manjunatha. P
manjup.jnnce@gmail.com
Professor
Dept. of ECE
J.N.N. College of Engineering, Shimoga
August 4, 2018

Overview Overview
Semiconductor Basics
Logic Gates
1 Truth table
2 Clock waveform
3 IC pin details
AIPMT/JEE/CET Papers
Dr. Manjunatha. P (JNNCE) Digital Electronics August 4, 2018 2 / 67

Classification of materials Classification of materials
Classification of materials
Classification Of materials based on resistivity/conductivity
Materials Resistivity Ω Ohm meter Conductivity σ Siemen per meter
Metals 10−2 − 10−8Ωm 102 − 108Sm−1
Semiconductors 10−5 − 106Ωm 105 − 10−6Sm−1
Insulators 1011 − 1019Ωm 102 − 10−11Sm−19
Classification Of materials based on energy bands
Inside the crystal each electron has a unique position and no two electrons see exactly the
same pattern of surrounding charges.
Hence each electron will have a different energy level.
These different energy levels with continuous energy variation form energy bands.
The energy band which including the energy levels of the valence electrons is called the
valence band.
The energy band above the valence band is called the conduction band.
The gap between the top of the valence band and bottom of the conduction band is
called the energy band gap (Energy gap Eg ).

Metals Semiconductors Insulators
ElectronEnergies
Conduction Band
Valence Band
vE
cE
0gE
3 eVgE
3 eVgE <
Figure 1
In metals, conduction and valance bands overlap each other.
In semiconductors small band gap (Eg < 3eV ) exists between conduction and valance
band.
In Insulators large band gap (Eg > 3eV ) exists between conduction and valance band.

Figure 2: Diode Characteristics

Figure 3

Figure 4: Zener diode Characteristics

Figure 5: Photodiode Characteristics

Figure 6: Solar cell Characteristics

Figure 7: Half-wave-rectiﬁer

Figure 8: Center tap full wave-rectiﬁer

Figure 9: full wave-rectiﬁer

Figure 10: Block diagram of a generalised communication system.

Figure 11: Block diagram of a generalised communication system.

Figure 12

LOGIC GATES Introduction
NOT gate
NOT gate produces an inverted version of the input at its output. It has one input and
one output. This is also known as an inverter. Its symbol and truth table.
A Y
NOT gate
Figure 13
Table 1: Truth Table
NOT gate
Input Output
A Y = A
0 1
1 0
Figure 14
Figure 15

AND Gate
An AND gate has two or more inputs and one output. The output Y is 1 only when all
the inputs are 1. The logic symbol and truth table are shown in Figure
A
AND Gate
B
Y
Figure 16
AND Gate
Input Output
A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)
Figure 17
Figure 18

NAND Gate
An NAND gate has two or more inputs and one output. The output Y is 0 only when all
the inputs are 1. The logic symbol and truth table are shown in Figure. NAND and NOR
gates are called Universal Gates since by using these gates any basic gates can be realised.
A
AND
B
Y
INVERTER
A
B
NAND Gate
Y
Figure 19
NAND Gate
Input Output
A B Y = A.B
0 0 1
0 1 1
1 0 1
1 1 0
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)
Figure 20
Figure 21

OR Gate
An OR gate has two or more inputs and one output. The output Y is 1 when anyone of
the inputs are 1. The logic symbol and truth table are shown in Figure
B
A
Y
OR Gate
Figure 22
OR Gate
Input Output
A B Y = A + B
0 0 0
0 1 1
1 0 1
1 1 1
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)
Figure 23
Figure 24

NOR Gate
An NOR gate has two or more inputs and one output. The output Y is 1 only when all
Y
INVERTER
A
B
A
B
Y
NOR GateOR
Figure 25
NOR Gate
Input Output
A B Y = A + B
0 0 1
0 1 0
1 0 0
1 1 0
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)
Figure 26
Figure 27Dr. Manjunatha. P (JNNCE) Digital Electronics August 4, 2018 20 / 67

EX-OR Gate
An EX-OR gate has two or more inputs and one output. The output Y is 0 when all the
inputs are 0 or 1. The logic symbol and truth table are shown in Figure
A
B
Y
EX-OR Gate
Figure 28
EX-OR Gate
Input Output
A B Y = A ⊕ B
0 0 0
0 1 1
1 0 1
1 1 0
Figure 29
Figure 30

EX-NOR Gate
An NOR gate has two or more inputs and one output. The output Y is 1 only when all
A
B
Y
EX-NOR Gate
Figure 31
EX-NOR Gate
Input Output
A B Y = A ⊕ B
0 0 1
0 1 0
1 0 0
1 1 1
Figure 32 Figure 33

EX-OR Gate using NAND gates
A
B
Y
AB
( )A AB
( )B AB
( ) ( )A AB B AB
Figure 34
Y = A(AB) B(AB) = A(AB) + B(AB) = A(A + B) + B(A + B)
Y = A(AB) B(AB)
= A(AB) + B(AB)
= A(A + B) + B(A + B) = AA + AB + BA + BB
= AA + AB

(i) (ii)
(iii) (iv)

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)

(i) (ii)
(iii) (iv)
(i) (ii)
(iii) (iv)
A
B
Y
A
Y
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)
A
(Input)
1
0
1
0
B
(Input)
Y
(Output)

NOT gate using
NAND and NOR
A Y
NOT gate

AND analogy
AC
S2
S1
S1 S2 Bulb
OFF OFF OFF
OFF ON OFF
ON OFF OFF
ON ON ON
OR analogy
AC
S2S1
S1 S2 Bulb
OFF OFF OFF
OFF ON ON
ON OFF ON
ON ON ON

A B C Y1 Y2 Y3 Y4
0 0 0 0 0 1 1
0 0 1 1 0 0 1
0 1 0 1 0 0 1
0 1 1 1 0 0 1
1 0 0 1 0 0 1
1 0 1 1 0 0 1
1 1 0 1 0 0 1
1 1 1 1 1 0 0

LOGIC GATES AIPMT/NEET/JEE
NEET 2018-17 : In the combination of the following gates output Y can be written in terms of
inputs A and B is
A
B
Y
Figure 35
(1) A.B + A.B (2) A.B + A.B
(3) A.B (4) A + B
Solution:

NEET 2018-17 : In the combination of the following gates output Y can be written in terms of
inputs A and B is
A
B
Y
Figure 35
(1) A.B + A.B (2) A.B + A.B
(3) A.B (4) A + B
Solution: Ans: (2)A.B + A.B

NEET 2018-16: In a p-n junction diode, change in temperature due to heating
1 does not affect resistance of p-n junction
2 affects only forward resistance
3 affects only reverse resistance
4 affects the overall V-I characteristics of p-n junction
Solution:

NEET 2018-16: In a p-n junction diode, change in temperature due to heating
1 does not affect resistance of p-n junction
2 affects only forward resistance
3 affects only reverse resistance
4 affects the overall V-I characteristics of p-n junction
Solution: Ans: (4)

NEET 2017-147 : Which one of the following represents forward bias diode?
-4 V -3 V
0 V -2 V
-2 V +2 V
3 V 5 V
(1)
(2)
(3)
(4)
R
R
R
R
Figure 36
Solution:

NEET 2017-147 : Which one of the following represents forward bias diode?
-4 V -3 V
0 V -2 V
-2 V +2 V
3 V 5 V
(1)
(2)
(3)
(4)
R
R
R
R
Figure 36
Solution: Ans: (4)

AIPMT 2017-142 : The given electrical network is equivalent to
A
B
Y
Figure 37
(1) OR gate (2)NOR gate
(3) NOT gate (4) AND gate
Solution:

AIPMT 2017-142 : The given electrical network is equivalent to
A
B
Y
Figure 37
(1) OR gate (2)NOR gate
(3) NOT gate (4) AND gate
Solution: Ans: (2)
NOR gate

AIPMT 2016-34 : To get output 1 for the following circuit, the correct choice for the input is
A
C
B
Y
Figure 38
(1) A=0, B=1, C=0 (2) A=1, B=0, C=0
(3) A=1, B=1, C=0 (4) A=1, B=0, C=1
Solution:

AIPMT 2016-34 : To get output 1 for the following circuit, the correct choice for the input is
A
C
B
Y
Figure 38
(1) A=0, B=1, C=0 (2) A=1, B=0, C=0
(3) A=1, B=1, C=0 (4) A=1, B=0, C=1
Solution: Ans: (4)
The circuit output Y is
Y = (A + B)C
C should be 1 and A or B is 1. This condition is satisﬁed by option (4)

NEET-2016-23: If a, b, c, d are inputs to a gate and x is its output, then, as per the following
time graph, the gate is:
d
c
1
x
b
a
0
1
0
Figure 39
The logic circuit gate is :
(1) AND gate (2) NAND gate (3)NOR gate (4)OR gate

NEET-2016-23: If a, b, c, d are inputs to a gate and x is its output, then, as per the following
time graph, the gate is:
d
c
1
x
b
a
0
1
0
Figure 39
(1) AND gate (2) NAND gate (3)NOR gate (4)OR gate
Ans: (4)

AIPMT 2016-34-Code-APW,2012-99 : To get output 1 for the following circuit, the correct
choice for the input is
A
C
B
Y
Figure 40
(1) A=0, B=1, C=0 (2) A=1, B=0, C=0
(3) A=1, B=1, C=0 (4) A=1, B=0, C=1
Solution:

AIPMT 2016-34-Code-APW,2012-99 : To get output 1 for the following circuit, the correct
choice for the input is
A
C
B
Y
Figure 40
(1) A=0, B=1, C=0 (2) A=1, B=0, C=0
(3) A=1, B=1, C=0 (4) A=1, B=0, C=1
Solution:
Ans: (4)
The circuit output Y is
Y = (A + B)C
C should be 1 and A or B is 1. This condition is satisﬁed by option (4)

AIPMT 2016-13-CODE-APW: Consider the junction diode as ideal. The value of current
ﬂowing through AB is. Figure 41
A 1 kΩ B
+ 4 v - 6 v
Figure 41
(1) 0 A (2) 10−2 A (3) 10−1 A (4) 10−3 A

AIPMT 2016-13-CODE-APW: Consider the junction diode as ideal. The value of current
ﬂowing through AB is. Figure 41
A 1 kΩ B
+ 4 v - 6 v
Figure 41
(1) 0 A (2) 10−2 A (3) 10−1 A (4) 10−3 A
Solution: The diode is ideal means its internal resistance and its junction voltage is zero. The
diode is forward biased. Its anode terminal is of + 4V and its cathode terminal is of - 6 V.
Therefore total forward biased voltage to the diode is 10V. Current ﬂowing in the resistance is
I =
10
1000
= 10−2
A
Correct option is (2)

AIPMT 2015-150-CODE-APW: In the given ﬁgure a diode is connected to an external
resistance of R = 100Ω and an e.m.f. of 3.5 V. If the barrier potential across diode is 0.5 V the
current in the circuit will be
100 Ω
3.5 V
D
R
Figure 42
(1) 35 mA (2) 30 mA (3) 40 mA (4) 20 mA

AIPMT 2015-150-CODE-APW: In the given ﬁgure a diode is connected to an external
resistance of R = 100Ω and an e.m.f. of 3.5 V. If the barrier potential across diode is 0.5 V the
current in the circuit will be
100 Ω
3.5 V
D
R
Figure 42
(1) 35 mA (2) 30 mA (3) 40 mA (4) 20 mA
Solution:
Ans: (2)
The eﬀective forward voltage across diode is 3.5V-0.5V=3V. The current through circuit is
I =
3
100
= 30 mA

AIPMT 2014-157-CODE-Q: The barrier potential of PN junction depends upon circuit will be
(a) type of semi conductor material
(b) amount of doping
(c) temperature
Which of the following is correct:
(1) (b) only (2) (b) and (c) only
(3) (a), (b) and (c) only (4) (a) and (b) only

AIPMT 2014-157-CODE-Q: The barrier potential of PN junction depends upon circuit will be
(a) type of semi conductor material
(b) amount of doping
(c) temperature
Which of the following is correct:
(1) (b) only (2) (b) and (c) only
(3) (a), (b) and (c) only (4) (a) and (b) only
Ans: (1):amount of doping

AIPMT 2013-45: The output (X) of the logic circuit shown in Figure will be
A
B
X
Figure 43
(1) X = A B (2) X = AB
(3) X = AB (4) X = A + B

AIPMT 2013-45: The output (X) of the logic circuit shown in Figure will be
A
B
X
Figure 43
(1) X = A B (2) X = AB
(3) X = AB (4) X = A + B
Solution:
Ans: (3)
The ﬁrst NAND gate output is X = AB and the second gate output is X = AB = AB

AIPMT 2012-99 2010-28: To get an output Y = 1 from the circuit shown below, the input
must be: Figure 44
A
C
B
Y
Figure 44
A B C
1 0 1 0
2 0 0 1
3 1 0 1
4 1 0 0

AIPMT 2012-99 2010-28: To get an output Y = 1 from the circuit shown below, the input
must be: Figure 44
A
C
B
Y
Figure 44
A B C
1 0 1 0
2 0 0 1
3 1 0 1
4 1 0 0
Ans: (3)

AIPMT 2011-50: Symbolic representation of four logic gates are shown as in Figure 45
(i) (ii)
(iii) (iv)
Figure 45
Pick out which ones are for AND, NAND and NOT gates respectively
(1) (ii), (iv) and (iii) (2) (ii), (iii) and (iv)
(3) (iii), (ii) and (i) (4) (iii), (ii) and (iv)

(i) (ii)
(iii) (iv)
Figure 45
Pick out which ones are for AND, NAND and NOT gates respectively
(1) (ii), (iv) and (iii) (2) (ii), (iii) and (iv)
(3) (iii), (ii) and (i) (4) (iii), (ii) and (iv)
Ans: (1)

(i) (ii)
(iii) (iv)
Figure 46
Pick out which ones are for OR, NOT and NAND gates respectively
(1) (iv), (i) and (iii) (2) (iv), (ii) and (i)
(3) (i), (iii) and (iv) (4) (iii), (iv) and (ii)

(i) (ii)
(iii) (iv)
Figure 46
Pick out which ones are for OR, NOT and NAND gates respectively
(1) (iv), (i) and (iii) (2) (iv), (ii) and (i)
(3) (i), (iii) and (iv) (4) (iii), (iv) and (ii)
Solution:
Ans: (2)

AIPMT 2008-49: The circuit 47 is equivalent to
Figure 47
(1) OR gate (2) AND gate (3) NAND gate (4)NOR gate
Solution:

AIPMT 2008-49: The circuit 47 is equivalent to
Figure 47
(1) OR gate (2) AND gate (3) NAND gate (4)NOR gate
Solution: Ans: (4)

JEE 2016-24: Choose the correct statement:
(1) In amplitude modulation the amplitude of the high frequency carrier wave is
made to vary in proportion to the amplitude of the audio signal.
(2) In amplitude modulation the frequency of the high frequency carrier wave is
(3) In frequency modulation the amplitude of the high frequency carrier wave is
made to vary in proportion to the frequency of the audio signal.

JEE 2016-24: Choose the correct statement:
(1) In amplitude modulation the amplitude of the high frequency carrier wave is
(2) In amplitude modulation the frequency of the high frequency carrier wave is
made to vary in proportion to the frequency of the audio signal.
Solution: Ans: (1)

LOGIC GATES JEE
JEE-2018-27: The reading of the ammeter for a silicon diode in the given circuit is
200 Ω
3 V
D
Figure 48
(1) 0 (2) 15 mA (3)11.5 mA (4)13.5 mA

LOGIC GATES JEE
JEE-2018-27: The reading of the ammeter for a silicon diode in the given circuit is
200 Ω
3 V
D
Figure 48
(1) 0 (2) 15 mA (3)11.5 mA (4)13.5 mA
Ans: (3)
I =
V − VJ
R
=
3 − 0.7
200
=
2.3
200
=
2300
200
mA = 11.5mA

LOGIC GATES JEE
JEE-2018-27 Online: Truth table for the following digital circuit will be
X
Y
Z
Figure 49
(1)
x y z
0 0 0
0 1 0
1 0 0
1 1 1
(2)
x y z
0 0 1
0 1 1
1 0 1
1 1 0
(3)
x y z
0 0 1
0 1 1
1 0 1
1 1 1
(4)
x y z
0 0 0
0 1 1
1 0 1
1 1 1

LOGIC GATES JEE
JEE-2018-27 Online: Truth table for the following digital circuit will be
X
Y
Z
Figure 49
(1)
x y z
0 0 0
0 1 0
1 0 0
1 1 1
(2)
x y z
0 0 1
0 1 1
1 0 1
1 1 0
(3)
x y z
0 0 1
0 1 1
1 0 1
1 1 1
(4)
x y z
0 0 0
0 1 1
1 0 1
1 1 1
Ans: (3)

LOGIC GATES JEE
JEE 2016-29: Identify the semiconductor devices whose characteristics are given below, in the
order (a), (b), (c), (d):

Figure 50
(1) Simple diode, Zener diode, Solar cell, Light dependent resistance.
(2) Zener diode, Simple diode, Light dependent resistance, Solar cell.
(3) Solar cell, Light dependent resistance, Zener diode, Simple diode.
(4) Zener diode, Solar cell, Simple diode, Light dependent resistance.

LOGIC GATES JEE
JEE 2016-29: Identify the semiconductor devices whose characteristics are given below, in the
order (a), (b), (c), (d):

Figure 50
(1) Simple diode, Zener diode, Solar cell, Light dependent resistance.
(2) Zener diode, Simple diode, Light dependent resistance, Solar cell.
(3) Solar cell, Light dependent resistance, Zener diode, Simple diode.
(4) Zener diode, Solar cell, Simple diode, Light dependent resistance.
Solution:
Ans: (1)

LOGIC GATES JEE
JEE 2015-29: A signal of 5 kHz frequency is amplitude modulated on a carrier wave of
frequency 2 MHz. The frequencies of the resultant signal is/are : the circuit will be
(1) 2 MHz only (2) 2005 kHz, and 1995 kHz
(3) 2005 kHz, 2000 kHz and 1995 kHz
(4) 2000 kHz and 1995 kHz

LOGIC GATES JEE
JEE 2015-29: A signal of 5 kHz frequency is amplitude modulated on a carrier wave of
frequency 2 MHz. The frequencies of the resultant signal is/are : the circuit will be
(1) 2 MHz only (2) 2005 kHz, and 1995 kHz
(3) 2005 kHz, 2000 kHz and 1995 kHz
(4) 2000 kHz and 1995 kHz
Solution: Ans: (3)
A signal of 5 kHz frequency is amplitude modulated on a carrier wave of frequency 2 MHz. The
frequencies of the resultant signal can be therefore 2005 Hz, 2000 Hz, 1995 Hz.

LOGIC GATES JEE
JEE 2014-13: The forward biased diode connection is:
-3 V -3 V
+ 2 V -2 V
2 V 4 V
-2 V +2 V
(1)
(2)
(3)
(4)
Figure 51

LOGIC GATES JEE
JEE 2014-13: The forward biased diode connection is:
-3 V -3 V
+ 2 V -2 V
2 V 4 V
-2 V +2 V
(1)
(2)
(3)
(4)
Figure 51
Solution: Ans: (3)

LOGIC GATES JEE
JEE 2014-14: During the propagation of electromagnetic waves in a medium :
(1) Electric energy density is equal to the magnetic energy density.
(2) Both electric and magnetic energy densities are zero.
(3) Electric energy density is double of the magnetic energy density.
(4) Electric energy density is half of the magnetic density.

LOGIC GATES JEE
JEE 2014-14: During the propagation of electromagnetic waves in a medium :
(1) Electric energy density is equal to the magnetic energy density.
(2) Both electric and magnetic energy densities are zero.
(3) Electric energy density is double of the magnetic energy density.
(4) Electric energy density is half of the magnetic density.
Solution: Ans: (1)

LOGIC GATES JEE
JEE 2014-14: Match I (Electromagnetic wave type) with List-II (its association/application) and
select the correct option from the choices given below the lists:
a Infrared waves (i) To treat muscular strain
b Radio waves (ii) For broad casting
c X-rays (iii) To detect fracture of bones
d Ultraviolet rays (iv) Absorbed by the ozone layer
of the atmosphere

LOGIC GATES JEE
JEE 2014-14: Match I (Electromagnetic wave type) with List-II (its association/application) and
select the correct option from the choices given below the lists:
a Infrared waves (i) To treat muscular strain
b Radio waves (ii) For broad casting
c X-rays (iii) To detect fracture of bones
d Ultraviolet rays (iv) Absorbed by the ozone layer
of the atmosphere
a b c d
(1) (iv) (iii) (ii) (i)
(2) (i) (ii) (iv) (iii)
(3) (iii) (ii) (i) (iv)
(4) (i) (ii) (iii) (iv)
Solution: Ans: (4)

Logic-gates CET
CET 2018-47 In CE ampliﬁer, the input ac signal to be ampliﬁed is applied across?
A Forward biased emitter-base junction
B Reverse biased collector-base junction
C Reverse biased emitter-base junction
D Forward biased collector-base junction

Logic-gates CET
CET 2018-47 In CE ampliﬁer, the input ac signal to be ampliﬁed is applied across?
A Forward biased emitter-base junction
B Reverse biased collector-base junction
C Reverse biased emitter-base junction
D Forward biased collector-base junction
Solution: A: Forward biased emitter-base junction
Figure 52

Logic-gates CET
CET 2018-31 In Karnataka, the normal domestic power supply AC is 220 V, 50 HZ. Here
220 V and 50 Hz refer to
A Peak value of voltage and frequency
B rms value of voltage and frequency
C Mean value of voltage and frequency
D Peak value of voltage and angular frequency

Logic-gates CET
Solution: B
CET 2018-14 Ohm’s Law is applicable to
A Diode
B Transistor
C Electrolyte
D Conductor

Logic-gates CET
Solution: B
CET 2018-14 Ohm’s Law is applicable to
A Diode
B Transistor
C Electrolyte
D Conductor
Solution: D

Logic-gates CET
CET 2018-48 If A = 1 and B = 0, then in terms of Boolean algebra, A + B =
A B
B B
C A
D A

Logic-gates CET
CET 2018-48 If A = 1 and B = 0, then in terms of Boolean algebra, A + B =
A B
B B
C A
D A
Solution: B or C, B and C

Logic-gates CET
CET 2017-56 Which of the following semi-conducting devices is used as voltage regulator ?
A Photo diode
B LASER diode
C Zener diode
D Solar cell

Logic-gates CET
A Photo diode
B LASER diode
C Zener diode
D Solar cell
Solution: C: Zener diode

Logic-gates CET
A Photo diode
B LASER diode
C Zener diode
D Solar cell
CET 2017-57 In the three parts of a transistor, Emitter is of

Logic-gates CET
A Photo diode
B LASER diode
C Zener diode
D Solar cell
A moderate size and heavily doped
B large size and lightly doped
C thin size and heavily doped
D large size and moderately doped

Logic-gates CET
A Photo diode
B LASER diode
C Zener diode
D Solar cell
A moderate size and heavily doped
B large size and lightly doped
C thin size and heavily doped
D large size and moderately doped
Solution: (A)

Logic-gates CET
CET 2017-59 Which of the following logic gate is considered as universal.
(A) (B)
(C) (D)
A
B
Y
A
A
A
B
B
Y
Y
Y
Figure 53

Logic-gates CET
CET 2017-59 Which of the following logic gate is considered as universal.
(A) (B)
(C) (D)
A
B
Y
A
A
A
B
B
Y
Y
Y
Figure 53
Solution: (D) NAND gate

Logic-gates CET
CET 2017-60 A basic communication system consists of
(A) Transmitter
(b) Information source
(c) User of information
(d) Channel
(e) Receiver
The correct sequence of the arrangement is
(A) a, b, c, d and e
(B) b, a, d, e and c
(C) b, d, a, c and e
(d) Channel
(e) b, e, a, d and c

Logic-gates CET
CET 2017-60 A basic communication system consists of
(A) Transmitter
(b) Information source
(c) User of information
(d) Channel
(e) Receiver
The correct sequence of the arrangement is
(A) a, b, c, d and e
(B) b, a, d, e and c
(C) b, d, a, c and e
(d) Channel
(e) b, e, a, d and c
Solution: (B)

Logic-gates CET
CET 2016-60 Identify the logic operation carried out by the following circuit.
A
B
Y
Figure 54
(1) AND (2) NAND (3) NOR (4) OR

Logic-gates CET
CET 2016-60 Identify the logic operation carried out by the following circuit.
A
B
Y
Figure 54
(1) AND (2) NAND (3) NOR (4) OR
Solution: (4) OR gate
Y = A .B = A + B = A + B

Logic-gates CET
CET 2015-59 The given truth table is for.
Input1 Input2 Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
(1) AND gate (2) OR gate (3) NAND gate (4) NOR gate

Logic-gates CET
CET 2015-59 The given truth table is for.
Input1 Input2 Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
(1) AND gate (2) OR gate (3) NAND gate (4) NOR gate
Solution: (3) NAND gate

Logic-gates CET
CET 2014-34 For the given digital circuit, identify the logic gate it represents.
Y
A
B
Figure 55
(1) OR gate (2)NOR gate (3) NAND gate (4) AND gate

Logic-gates CET
CET 2014-34 For the given digital circuit, identify the logic gate it represents.
Y
A
B
Figure 55
(1) OR gate (2)NOR gate (3) NAND gate (4) AND gate
Solution: (4) AND gate
Y = A + B = A.B = A.B

Logic-gates CET
CET 2013-58 The output of an OR gate is connected to both the inputs of a NAND gate.
The combination will serve as
(1) AND gate (2)NOT gate (3) NAND gate (4)NOR gate
Solution:
Y
A
B
Figure 56

Logic-gates CET
CET 2013-58 The output of an OR gate is connected to both the inputs of a NAND gate.
The combination will serve as
(1) AND gate (2)NOT gate (3) NAND gate (4)NOR gate
Solution:
Y
A
B
Figure 56
(4) NOR gate
Y = A + B = A.B

Logic-gates CET
CET 2012-58 The following truth table with A and B as inputs is for ——- gate
A B Output
1 0 1
1 1 0
0 1 1
0 0 0
(1) AND gate (2) OR gate (3) XOR gate (4) NOR gate

Logic-gates CET
A B Output
1 0 1
1 1 0
0 1 1
0 0 0
(1) AND gate (2) OR gate (3) XOR gate (4) NOR gate
Solution: (3) XOR gate

Logic-gates CET
CET 2011-59 The output of given logic circuit is ——-
(1) A.(B+C) (2)A.(B.C)
(3) (A+B).(A+C) (4) A+B+C
Y
A
B
C
Figure 57

Logic-gates CET
CET 2011-59 The output of given logic circuit is ——-
(1) A.(B+C) (2)A.(B.C)
(3) (A+B).(A+C) (4) A+B+C
Y
A
B
C
Figure 57
Solution: (3)

Logic-gates CET
CET 2010-59 Identify the logic operation performed by the circuit given here.
Y
A
B
Figure 58
(1) NOT (2)NAND (3)OR (4)NOR

Logic-gates CET
Y
A
B
Figure 58
(1) NOT (2)NAND (3)OR (4)NOR
Solution: (3) OR gate
Y = A + B = A + B

Logic-gates CET
CET 2009-26 In the following combination of logic gates, the outputs of A,B and C are
respectively
0
1
1
0
1
1
1
1
(A)
(B)
(C)
Figure 59
(1) 0,1,0 (2)1,1,0 (3)1,0,1 (4)0,1,1

Logic-gates CET
CET 2009-26 In the following combination of logic gates, the outputs of A,B and C are
respectively
0
1
1
0
1
1
1
1
(A)
(B)
(C)
Figure 59
(1) 0,1,0 (2)1,1,0 (3)1,0,1 (4)0,1,1
Solution: (2) 1,1,0

Logic-gates CET
CET 2008-45 To get an output y=1 from the circuit shown, the inputs of A,B and C are
respectively
Y
A
B
C
Figure 60
(1) 0,1,0 (2)1,0,0 (3)1,0,1 (4)1,1,0

Logic-gates CET
CET 2008-45 To get an output y=1 from the circuit shown, the inputs of A,B and C are
respectively
Y
A
B
C
Figure 60
(1) 0,1,0 (2)1,0,0 (3)1,0,1 (4)1,1,0
Solution: (3) 1,0,1

Logic-gates CET
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
(1) NAND (2) XOR gate (3) AND (4) NOR

Logic-gates CET
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
(1) NAND (2) XOR gate (3) AND (4) NOR
Solution: (1) NAND gate

Logic-gates CET
Y
A
B
A
B
Figure 61
(1) NOT (2)AND (3)OR (4)NAND
Y = A + B = A.B = A.B

Logic-gates CET
Y
A
B
A
B
Figure 61
(1) NOT (2)AND (3)OR (4)NAND
Y = A + B = A.B = A.B
Ans: (4) NAND

Logic gates

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Logic gates