2. SYNCHRONOUS COUNTER.
If all the flip-flops receive the same clock signal, then that
counter is called as Synchronous
If all the flip flop are Clocked synchronously
The resulting circuit is known as synchronous counter
3.
4. TYPES OF SYNCHRONOUS COUNTER
• Synchronous up counter
• Synchronous down counter
• Synchronous up/ down counter
5. Down counter counts the numbers in decreasing order.
This is similar to an up counter but is should decrease its count.
So inputs of JK flip- flop are connected to the inverted Q (Q’) .
The 4 bit down counter shown in below diagram is designed by
using JK flip flop. The same external clock pulse is connected to
all the flip flops.
Synchronous down counter.
6. As the counter has to count down the sequence, initially all the
inputs will be in high state as they have to count down the
sequence. It will start with 1111 and ends with 0000, similar to
the up counter
In the down counter it should be remembered that, preceding
flip flop will toggles only if front flip flop produces low logic at
its output.
10. 4-BIT SYNCHRONOUS COUNTER
• Because this 4-bit synchronous counter counts sequentially on every clock
pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ).
Therefore, this type of counter is also known as a 4-bit Synchronous Up
Counter.
• However, we can easily construct a 4-bit Synchronous Down Counter by
connecting the AND gates to the Q output of the flip-flops as shown to
produce a waveform timing diagram the reverse of the above. Here the
counter starts with all of its outputs HIGH ( 1111 ) and it counts down on
the application of each clock pulse to zero, ( 0000 ) before repeating again.
11. SYNCHRONOUS UP/DOWN COUNTER
The above two counters can be implemented in a single counter called up
down counter.This can be selected from its input.
The design of up/ down counter with JK flip flops is shown below
The up/ down counter has “Up” and “Down” count modes by having 2
input AND gates, which are used to detect the appropriate bit conditions
for counting operation.
OR gates are used to combine the outputs of AND gate, from each JK flip
flop.
12. We provide a up/ down control line which enables upper or lower series of
AND gates to pass the outputs of JK flip flops, Q , Q’ to the next stage of
flip flop, in the cascaded arrangement.
If the up /down control line is set to HIGH, then the top AND gates are in
enable state and the circuit acts as UP counter. If the up /down control line
is set to low, then the bottom AND gates are in enable state and the circuit
acts as DOWN counter.
15. • This counter has two modes of counting i.e. up counting and
down counting.
• There is a mode switch which switches between the two modes
of the counter. When the mode M = 0 it counts up & when mode
M = 1 then it counts down.
16. APPLICATION FOR SYNCHRONOUS COUNTER
• Commons used in home appliances like washing machine,
microwave own, Time schedule led indicator, key board
controller etc.
• They are also used in machine moving control.
• Mostly used in digital clocks and multiplexing circuits.
17. • Alarm Clock, Set AC Timer, Set time in camera to take the
picture, flashing light indicator in automobiles, car parking
control etc.
• It is also used in digital to analog converters
• The UP/DOWN counter can be used as a self-reversing counter
18. ADVANTAGES & DISADVANTAGE OF
SYNCHRONOUS COUNTER
• Very easy to design this circuit because we may set the same clock pulse
for all gates.
• They are faster as the the propagation delay are small as compared to
asynchronous counters.
• There are no counting errors as compared to asynchronous counters.
• Performance is much better, liable and portable circuit.