THIS TOPIC NAMED BJT & ITS BIASING OF BASIC ELECTRONICS.

1. BASIC ELECTRONICS(3110016)
ASSIGNMENT-2
Created By,
 KAJALIYA CHARCHIL C.
 SEM-2
 INFORMATION TECHNOLOGY
 170210116025
Guidance by,
NEHA JOSHI Ma’am

2. TOPICS/QUESTIONS SET-I
1) Why biasing is important in transistor? Explain voltage
divider bias with diagram.
2) Draw the circuit of transistor in CE configuration. Sketch
the output characteristics and explain active, saturation
and cutoff regions.
3) Explain Unipolar device.
4) Draw the symbol of NPN and PNP transistor. What is use
of transistor?
5) State advantage of transistor
6) Derive the relation between current gain α and β.
7) Draw and explain input and output characteristic of
transistor in common emitter configuration.
8) What is stability factor? Explain in brief.
2

3. Q-1. Why biasing is important in transistor? Explain voltage divider
bias with diagram.
Ans:
• A biasing is required to activate the transistor and prevents it to either to saturation mode
or cut-off mode. Transiator biasing is the process of setting a transistors DC operating
voltage or current conditions to the correct level so that any AC input signal can be
amplified correctly by the transistor.
A circuit which is used to establish a stable operating point is the self-biasing circuit shown
in Fig. 2.3.1
3

4. • In this circuit, the biasing is provided by three resistors : R, R2 and RE
• The resistors R, and R, act as a potential divider giving a fixed voltage to point
B which is base.
• If collector current increases due to change in temperature or change in the
emitter current I also increases and voltage drop cross RE reducing the voltage
difference between base and emitter (VaE)
• Due to reduction in VeE, base current lg and hence collector current le also
reduces. Therefore, we can say that negative feedback exists in the voitage
diode the increases, Fig. Voltage divider bias circuit.
• This reduction in collector current Ic compensates for the original change in
Ic.
• Fig. shows Thevenin's equivalent circuit of voltage divider bias. Here, R, and
R2 are replaced by Rb and VT. where Rb is the parallel combination of R1 and
R2 and Vt is the Thevenin's voltage. Rb can be calculated as
4

5. 5

6. Q-2. Draw the circuit of transistor in CE configuration. Sketch the
output characteristics and explain active, saturation and cutoff
regions.
👉. In this configuration input is applied between base and emitter, and output is taken from collector
and emitter. Here, emitter of the transistor is common to both, input and output circuits, and hence
the name common emitter configuration.
Common emitter configurations for both npn and pnp transistors are shown in Fig. 2.4.6 (a) and 2.4.6
(b), respectively.
Ans.

7.  Input Characteristics of CE Configuration
• The input voltage in the CE configuration is the base-emitter voltage and the output
voltage is the collector-emitter voltage. The input current is lb and the output current is l
• Input characteristics is the curve between input voltage Vbe (base-emitter voltage and
input current Ib (base curent) at constant collector-emitter voltage, Vbe. The base
current is taken along Y-axis and base emitter voltage Vbe is taken along X-axis. Fig 24.7
shows the input characteristics of a typical transistor in common-emitter configuration.

8. From this characteristics we observe the following important points:
1. The input resistance is the ratio of change in base-emitter voltage ( Vbe) lo the resulting
change in base current ( Ib) at constant collector emitter voltage Vce h is given by,
2. After the cut-in voltage, the base current (Ib) increases rapidly with small increise in base-
emitter voltage (VBE). Thus the dynamic input resistance is small in CE configuration.
3. For a fixed value of VBE, Ib decreases as Vce is increased.
 Output Characteristics of CE Configuration
1. This characteristics shows the relation between the collector current lc and collector
voltage VCE for various fixed values of Ib. This characteristics is often called collector
characterstics. A typical family of output characteristics for an n-p-n transistor in CE
configuration is shown in Fig. 2.4.8
2. The value of Bdc of the transistor can be found at any point on the characteristics by
taking the ratio lc to Ib at that point, i.e. B lc /lb. This is known as D.C. beta for the
transistor.
3. From the output characteristics, we can see that change in collector-emitter voltage ( Vce)
causes the little change in the collector current ( Ic) for constant base cumnt Ib. Thus the
output dynamic resistance is high in CE configuration. 8

10. Q-3. Explain Unipolar device.
Ans:
• Unipolar Device : We know that in BJT, the current is carried by both
electrons and holes, and hence the name "bipolar" junction
transistor. However in FET current is carried by only one type of
charge particles, either electrons or hole Hence FET is called unipolar
device.
• Like BJT, the parameters of FET are also temperature dependent. In
FET, as temperature increases drain resistance also increases,
reducing the drain current Thus unlike BJT, thermal runaway does
not occur with FET. Thus we can say that FET is more temperature
stable as compared to the BJT.
• FET has very high input impedance. Typically, it is in the range of one
to several megaohms. Because FETs have higher input impedance
than BJT they are preferred in amplifier where high input impedance
is required.
• FETS require less space than that for BJTs, hence they are preferred
in integrate circuits.

11.  Uses of transistor
Transistor can be used as an amplifier and switch.
Transistor can be used as an amplifier. It is used as a current and voltage
amplifier.
As a switch, transistor is used in SMPS (Switch Mode Power Supply) and
digital circuits.
Transistors are used in oscillator circuits and feedback amplifiers
Q-4. Draw the symbol of NPN and PNP transistor. What is use of
transistor?

12. Q-5. State advantage of transistor.
Ans.
👉 Advantages of Transistor
• The key advantages that have allowed transistors to replace
vacuum tubes in most applications are :
1. Very small size and weight, reducing equipment size
2. Low operating voltages
3. Lower costs
4. Low power consumption
5. Higher efficiency
6. Very low sensitivity to mechanical shock and vibration
7. Very long life.
12

13. Q-6. Derive the relation between current gain α and β.
Ans.

14. Q-7. Draw and explain input and output characteristic of
transistor in common emitter configuration.
• In this configuration input is applied between base and
emitter, and output is taken from collector and emitter. Here,
emitter of the transistor is common to both input and output
circuits, and hence the name common emitter configuration.
• Common emitter configurations for both npn and pnp
transistors are shown in Fig. (a) and (b), respectively.
Ans.
14

15.  Input characteristics of CE CONFIGURATION
Ans:
• The input voltage in the CE configuration is the base-emitter
voltage and the output voltage is the collector-emitter voltage. The
input current is lb and the output current is lc.
• Input characteristics is the curve between input voltage VRE (base-
emitter voltage) and input current In (base current) at constant
collector-emitter voltage, VCE The base current is taken along Y-
axis and base emitter voltage Vse is taken along X-axis. Fig. shows
the input characteristics of a typical transistor in common-emitter
configuration. 15

16. • The input resistance is the ratio of change in base emitter
voltage (🔺Vbe ) to the resulting change in base current (🔺
Ib) at constant collector emitter voltage Vce. It is given by,
• After the cut-in voltage, the base current (Ib) increases
rapidly with small increase in base-emitter voltage (Vbe) .
Thus the dynamic input resistance is small in CE
configuration
• For a fixed value of VBE, Ib decreases as Vce is increased.
16

17.  OUTPUT CHARACTERISTICS OF CE CONFIGURATION
• 1.This characteristics shows the relation between the
collector current ic and collector voltage VCEfor various fixed
values of Ig. This characteristics is often called collector
characteristics. A typical family of output characteristics for
an n-p-n transistor in CE configuration is shown in Fig. 2.4.8.
17

18. • The value of Bdc of the transistor can be found at any point
on the characteristics by taking the ratio Ic to IB at that
point, i.e. Bdc = Ic /Ib. This is known as D.C.beta for the
transistor.
• 3. From the output characteristics, we can see that change in
collector-emitter voltage (AVCE) causes the little change in
the collector current (IC) for constant base current Ig. Thus
the output dynamic resistance is high in CE configuration.
18

19. 8. What is stability factor? Explain in brief.
Ans:-
• In order to compare the stability provided by these circuits,
one term is raised allied stability factor, which indicates degree
of change in operating point due to variation in temperature.
Since there are three variables which are temperature
dependent, we can define three stability factors as below:
19

20.  Key points for stability factor :
• 1. Ideally, stability factor should be perfectly zero to keep
operating point stable.
• 2 Practically stability factor should have the value as
minimum as possible. Thermal stability of a circuit is
assessed by deriving a stability factor, S.
• 3. Stability factor indicates the degree of change in
operating point due to variation in temperature.
20

21. TOPICS/QUESTIONS SET-II
9) What are the different method for biasing the transistor. Explain any
two method with necessary circuit diagram.
10) Draw a fixed bias circuit, write the advantages and disadvantages of
fixed bias circuit.
11) Explain DC load line and Q-point for any transistor Configuration.
12) For npn transistor, which of the transistor currents is always the
largest? Which is always the smallest? Which two currents are
relatively close in magnitude?
13) Label the three regions of operation on a bipolar junction transistor
14) Explain the voltage divider bias circuit in detail.
15) Explain the selection of a Q point for a transistor bias circuit and
discuss the limitations on the output voltage swing.
16) Explain about DC load line and Bias point of transistor.
21

22. Q-9.What are the different method for biasing the transistor.
Explain any two method with necessary circuit diagram.
Ans :-
• Different methods for biasing the transistor are :
• 1 Base(fixed) bias.
• 2.Emitter feedback bias
• 3.Collector to base bias.
• 4.Voltage divider bias
1.Base Bias
• The Fig. 2.6.1 shows the base bias circuit. It is also called fixed
bias circuit. It is the simplest d.c. bias configuration. For the d.c.
analysis we can replace capacitor with an open circuit because
the reactance of a capacitor for d.c.is Xc =1/2*3.14*
fC=1/2*3.14* (0) C= infinite
22

23. • The d.c. equivalent of base bias circuit is shown in Fig. 2.6.1 (b)
 Collector Circuit
• Applying Kirchhoff's voltage law (KVL) to the base circuit shown in Fig.
2.6.2 we get,
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24. 24

25. • It is important to note that since the base current is controlled
by the value of Rb and Ic is related to Ib by a constant B, the
magnitude of Ic is not a function of the resistance Rc.
• Changing Rc to any level will not affect the level of IB or Ic as
long as we Remain in the active region of the device. However,
the change in Rc will change the value of VCE.
• VCE = Vc-VE.
• where. Vc Collector voltage and VE Emitter voltage Similarly,
25

26.  2. Voltage divider bias
A circuit which is used to establish a stable operating point is the self-
biasing circuit shown in Fig.
• In this circuit, the biasing is provided by three resistors : R, R2 and RE
• The resistors R, and R, act as a potential divider giving a fixed voltage to point B
which is base.
26

27. • If collector current increases due to change in temperature or change in the
emitter current I also increases and voltage drop cross RE reducing the voltage
difference between base and emitter (VaE)
• Due to reduction in VeE, base current lg and hence collector current le also
reduces. Therefore, we can say that negative feedback exists in the . Voltage
divider bias
• This reduction in collector current Ic compensates for the original change in Ic.
• Fig. shows Thevenin's equivalent circuit of voltage divider bias. Here, R, and R2
are replaced by Rb and VT. where Rb is the parallel combination of R1 and R2 and
Vt is the Thevenin's voltage. Rb can be calculated as
27

28. 28

29. Q-10.Draw a fixed bias circuit, write the advantages and
disadvantages of fixed bias circuit
• Base bias
• The Fig. shows the fixed bias circuit for pnp transistor. Here, the
voltage polarities and current directions are reversed than that of
npn transistor fixed bias circuit. However, the equations applied for
the analysis of npn transistor fixed bias circuit can be applied for the
analysis of pnp transistor fixed bias circuit.
29

30.  Advantages of Fixed Blas Circuit
• This is a simple circuit which uses very few components.
• .The operating point can be fixed anywhere in the active region of
the characteristics by simply changing the value of Rp. Thus, it
provides maximum Bexibility in the design.
 Disadvantages of Fixed Blas Circult
• This circuit does not provide any check on the collector current
which increases with the rise in temperature. i.e. thermal stability
is not provided by this circuit. So the operating point is not
maintained.
• Ic = βIb +Iceo
• Since Ic = βIb and Ic is already fixed; Iç depends on β which
changes unit to unit and shifts the operating point.
• • Thus stabilization of operating point is very poor in the fixed bias
circuit.
30

31. Q-11 Explain DC load line and Q-point for any transistor
Configuration.
 Definition :
• The d.c. load line is the line drawn on the output characteristics of CE
amplifier considering only d.c. operating conditions and the slope of
the line is -1/RC. where Rc is the load resistance.
• Applying KVL to the collector circuit we have
• Vcc-lcRc-V CE = 0
• Rearranging the terms in above equation we get,
• Ic = [ -1/Rc]Vce + Vcc/Rc
31

32. • If we compare this equation with equation of straight line y = mx + c, where m is the
slope of the line and c is the intercept on Y-axis, then we can draw a straight line on
the graph of Ie versus VCE which is having slope - 1/Rc and Y-intercept Vec/Rc. To
determine the two points on the line we assume VCE = Vcc and VCE = 0.
• When VCE = Vcc ; c = 0 and we get a point A and
(b)When VCE = 0 ; lc = Vcc/Rc and we get a point B
The Fig. shows the output characteristics of a common emitter configuration
with points A and B and line drawn between them, The line drawn between points A
andB is called d.c. load line.
The 'd.c.' word indicates that only d.c. conditions are considered,
Ie. inputs signal is assumed to be zero.
32

33.  Q-Point
• Applying Kirchhoff's voltage law to the base. circuit of Fig, we get,
• VBB - IBRB - VBE = 0
• Ib = (Vbb – Vbe)/Rb
• VBB >> VBE, Ib = Vbb/ Rb
• • If we assume, VBR = 10 V and RR = 5 K then IB = 2 mA. Now, if we draw
the characteristic curve for this value of I ; then intersection of this curve
and d.c. load line is the operating point. This point is the fixed point on
the characteristics, so it is called quiescent point or Q point (Quiescent
means quiet, still, inactive). For different values of In, we have different
intersection points such as P , Q and R. All these points are quiescent33

34. Q-12 For npn transistor, which of the transistor currents is
always the largest? Which is always the smallest? Which two
currents are relatively close in magnitude?
Ans.
• The emitter current IE is always the largest one.
• The base current IB is always the smallest.
• The collector current IC and emitter current IE are
relatively close in magnitude.
34

35. Q-13.Label the three regions of operation on a bipolar
junction transistor.
Ans:
 REGIONS OF OPERATION :
• Biasing is the process of applying external voltages to the transistor.
• Depending upon external bias voltage polarities applied to two
junctions of the transistor it can be operated in one of the four
regions :
• 1) Active region 2) Cut-off region and
• 3) Saturation region 4) Inverse active.
35

36. Q-14.Explain the voltage divider bias circuit in detail.
Ans:
• A circuit which is used to establish a stable operating point is the self-
biasing circuit shown in Fig.
• In this circuit, the biasing is provided by three resistors : R, R2 and RE
36

37. • The resistors R, and R, act as a potential divider giving a fixed
voltage to point B which is base.
• If collector current increases due to change in temperature or
change in the emitter current I also increases and voltage drop cross
RE reducing the voltage difference between base and emitter (VaE)
• Due to reduction in VeE, base current lg and hence collector
current le also reduces. Therefore, we can say that negative
feedback exists in the . Voltage divider bias
• This reduction in collector current Ic compensates for the original
change in Ic.
• Fig. shows Thevenin's equivalent circuit of voltage divider bias.
Here, R, and R2 are replaced by Rb and VT. where Rb is the parallel
combination of R1 and R2 and Vt is the Thevenin's voltage. Rb can be
calculated as
37

38. 38

39. Q-15.Explain the selection of a Q point for a transistor bias circuit and
discuss the limitations on the output voltage swing.
Ans.
• For a transistor circuit to amplify it must be properly biased with dc voltages. The dc
operating point between saturation and cutoff is called the Q-point. The goal is to set
the Q-point such that that it does not go into saturation or cutoff when an a ac signal is
applied.
39

40.  Output voltage swing:
• Output Voltage Swing defines how close the op-amp output can be driven to rail to rail
(either power rail: VDD or VSS) under defined operating conditions where the op-
amp still can function correctly.
• The key to comparing voltage output swing specifications is to determine the amount
of current that the amplifier is sinking or sourcing. The smaller the output short circuit
current is, the closer the amplifier will swing to the rail. The voltage output swing
capability of an op-amp is dependent on the op-amp output stage design and the load
current.
• Recall that the collector characteristic curves graphically show the relationship of
collector current and VCE for different base currents. With the dc load line
superimposed across the collector curves for this particular transistor we see
that 30 mA of collector current is best for maximum amplification, giving equal
amount above and below the Q-point. Note that this is three different scenarios of
collector current being viewed simultaneously.
40

41. Q-16.Explain about DC load line and Bias point of transistor.
Ans:
Definition :
• The d.c. load line is the line drawn on the output
characteristics of CE amplifier considering only d.c.
operating conditions and the slope of the line is - Ro where
Rc is the load resistance.
41

42. • Applying KVL to the collector circuit we have,
Vcc-ICRC-VCE = 0
• Rearranging the terms in above equation we Get,
Ic = - Vce/Rc + Vcc/Rc
• If we compare this equation with equation of straight line y = mx
+ C, where mis the slope of the line and c is the intercept on Y-
axis, then we can draw a straight line on the graph of I versus
VCE which is having slope - 1/Rc and Y-intercept Voc/R To
determine the two points on the line we assume VCE = Vcc and
VCE = 0.
42

43. • The Fig. 5.2.2 shows the output characteristics of a common emitter
configuration with points A and B and line drawn between them. The line
drawn between points A and we get a point B = Vcc/Rc called d.c. load line.
• The 'd.c.' word indicates that only dc conditions are considered, in. inputs signal
is assumed to be zero.
43

44.  Q-Point
• Applying Kirchhoff's voltage law to the base circuit of Fig, we get,
VBB - IBRB - VBE = 0
Ib = (Vbb – Vbe)/Rb
VBB >> VBE, Ib = Vbb/ Rb
• If we assume, VBR = 10 V and RR = 5 K then IB = 2 mA. Now, if we draw the
characteristic curve for this value of I ; then intersection of this curve and d.c. load
line is the operating point. This point is the fixed point on the characteristics, so it is
called quiescent point or Q point (Quiescent means quiet, still, inactive). For
different values of In, we have different intersection points such as P , Q and R. All
these points are quiescent points.
 Conditions for Saturation and Active Region
• To identify the operating region of transistor we can observe certain conditions. These
For saturation,
:For saturation: Ib> Ic/ βdc
: For active region : VCE> VCE (sat)
44

45.  Criteria for Selection of Operating Point
• The operating point can be selected at three different positions
on the d.c. load line Near saturation region, near cut-off region or
at the centre, i.e.. in the active region. The selection of operating
point will depend on its application. When transistor is used as an
amplifier, the Q-point should be selected at the centre of the d.c.
load line to prevent any possible distortion in the amplified
output signal. in case of switching operation, the operating point
should be in the saturation region tor ON-operation and it should
in cut-off region for OFF-operation.
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46. THANK YOU
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