2. DEN LAB
Steps to create project and execute in Modelsim
1: Open Modelsim
2: Go in menu : File-new-project
3: Give name to project – there should not be any space in the
name
4: POP UP window appears for new file
5: Click on create new file
6: Name your VHDL file –Check workspace
7: Click—OK and CANCEL/CLOSE
8: Double click on VHDL File
9: Editor Window Opens
10: Write your VHDL Program
11: Save
12: Compile
3. DEN LAB
13: Debug for error if any
14: Simulate
15: File is divided in three parts—i) Architecture, ii) package ieee,
iii) Package
16: Click on ARCHITECTURE
17: Go to view – signals
18: Signal names will appear in a pop up window.
Signal values can be changed here –
select the signal by click ---- go to edit—force—Click---POP UP
window appears—enter values
19: Back to –architecture—right click on architecture—click on add to
wave—waveform window opens.
Click RUN
Verify output
When you enter another set of signal values, do not press ADD TO
WAVE again, instead RUN directly.
4. DEN LAB
PROGRAM is of this type:
library ieee;
use ieee.std_logic_1164.all;
entity Nitin is
port(A: in std_logic;
B: in std_logic;
C: out std_logic);
end Nitin;
architecture Nitin_arch of Nitin is
begin
C<= A and B;
end Nitin_arch;
6. DEN LAB
Left Hand Side: All in PENCIL (Blank side)
(left top corner)
( Date here) Experiment No. ____
AIM: --
Software Used:-
Diagram:-
Truth Table:-
Result:-
Conclusion:-
Right Hand Side: All in INK (Ruled side) (page no)
(right top corner)
Experiment No. _____ (Date here)
AIM:--
Software used:-
Procedure/Discussion:
Program:-(As word document print)
Result:
Conclusion:
Instruction: Do Not Start Next Experiment from back side of the end of previous experiment.
Start with a new page.
Use only one shade of BLUE INK through out the journal.
Leave
some
margin
here
on
LHS
7. DEN LAB
Instruction: Do Not Start Next Experiment from back side of the end of previous experiment.
Start with a new page.
Use only one shade of BLUE INK through out the journal.
Follow all the instructions given to you time to time.
9. DEN LAB
For NOT using NAND: Y<=X nand X;
For AND using NAND: Z<= X nand Y;
P<= Z nand Z;
For OR using NAND: X<= A nand A;
Y<= B nand B;
Z<= X nand Y;
For NOT using NOR: Y<=X NOR X;
For OR using NOR : Z<= X NOR Y;
P<= Z NOR Z;
For AND using NOR : X<= A NOR A;
Y<= B NOR B;
Z<= X NOR Y;
11. DEN LAB
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity s_4x1mux is
port(a,b,c,d : in std_logic;
S0,s1 : in std_logic;
q : out std_logic);
end s_4x1mux;
Architecture s_4x1mux1 of s_4x1mux is
Begin
Process(a,b,c,d,s0,s1)
Begin
If s0 ='0' and s1 ='0' then q <= a;
Elsif s0 ='1' and s1 ='0' then q <= b;
elsif s0 ='0' and s1='1' then q <= c;
else q <=d;
end if;
End process;
End s_4x1mux1;
12. DEN LAB
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity s_16x1mux is
port(a:in std_logic_vector(15 downto 0);
s: in std_logic_vector(3 downto 0);
Z:out std_logic);
End s_16x1mux;
Architecture s_16x1mux1 of s_16x1mux is
signal z1,z2,z3,z4:std_logic;
component s_4x1mux
port(a,b,c,d,s0,s1:in std_logic;
Q:out std_logic);
End component;
13. DEN LAB
Begin
M1: s_4x1mux port
map(a(0),a(1),a(2),a(3),s(0),s(1),z1);
m2: s_4x1mux port
map(a(4),a(5),a(6),a(7),s(0),s(1),z2);
m3: s_4x1mux port
map(a(8),a(9),a(10),a(11),s(0),s(1),z3);
m4: s_4x1mux port
map(a(12),a(13),a(14),a(15),s(0),s(1),z4);
m5: s_4x1mux port
map(z1,z2,z3,z4,s(2),s(3),z);
End s_16x1mux1;
17. DEN LAB
library ieee;
use ieee.std_logic_1164.all;
entity demux_1to4 is
port(
F: in std_logic;
s0,s1 : in std_logic;
a,b,c,d : out std_logic);
end demux_1to4;
architecture bhy of demux_1to4 is
begin
process (F,s0,s1)
begin
if (s0=’0’ and s1 =’0’) then
a<= F;
elsif (s0=’1’ and s1=’0’) then
b<= F;
elsif (s0=’0’ and s1=’1’) then
c<=F;
else
d<=F;
end if;
end process;
end bhy;
