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Computer Architecture
CAT2002
Prof.Ashwini Mate
Assistant Professor
CSE AIML
COURSE OBJECTIVES
The objective of this course is to familiarize the prospective
engineers with:
1. Concepts of computer architecture by developing
understanding of various functional units, components of
computers and working of all the modules.
2. Design principles of modern computers including memory,
bus system, input/output operation, interrupt handling
mechanism and parallelization.
COURSE OUTCOMES
On Successful completion of course, students will be able to:
1. Demonstrate the understanding about the functional units of
a digital computer system.
2. Execute complete instruction on different types of bus
architectures with control signal generation.
3. Analyse memory, multiprocessor and multicore architectures
and their implications in parallel computing.
SYLLABUS
• UNIT I : Basic Structure of Computers: Functional units of
computer, basic operational conceptsInstruction, processor
and memory, operating steps, address, Big- and Little-endian
assignments, Instructions set architecture of a CPU-
Instruction Formats, Instruction sequencing, addressing
modes, and instruction set classification, subroutine &
parameter passing, expanding opcode, RISC and CISC.
• UNIT II : Basic Processing Unit and Data Representation:
Basic Concepts- Instruction execution, Bus architecture- One
bus and Multi-bus, Execution of a Complete Instruction,
sequencing of control signals, Hardwired control, Micro-
programmed Control. Floating point numbers-
representation, guard bits and rounding.
• UNIT III : Memory & Input/output: Cache memory, Cache size
vs. block size, mapping functions, replacement algorithms,
Cache read/write policy, Virtual Memory, I/O mapped I/O and
memories mapped I/O, interrupt and interrupt handling
mechanisms, vectored interrupts, synchronous vs.
asynchronous data transfer, Bus Arbitration, Direct Memory
Access
• UNIT IV : Pipelining: Basic concepts of pipelining, throughput
and speedup, Introduction of Parallel Computing: SISD, MISD,
SIMD, MIMD
TEXT BOOKS
• 1. V.C.Hamacher, Z.G.Vranesic and S.G.Zaky; Computer
Organization;
• 5th edition; Tata McGraw Hill, 2002. 2. W. Stallings;
Computer Organization & Architecture; PHI publication;
2001.
• 3. J. P. Hayes; Computer Architecture & Organization; 3rd
edition; McGraw-Hill; 1998.
REFERENCE BOOKS
• 1. M Mano; Computer System and Architecture;
PHI publication; 1993.
• 2. A. S. Tanenbaum; Structured Computer
Organization; Prentice Hall of India Ltd.

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Computer Architecture.pptx

  • 2. COURSE OBJECTIVES The objective of this course is to familiarize the prospective engineers with: 1. Concepts of computer architecture by developing understanding of various functional units, components of computers and working of all the modules. 2. Design principles of modern computers including memory, bus system, input/output operation, interrupt handling mechanism and parallelization.
  • 3. COURSE OUTCOMES On Successful completion of course, students will be able to: 1. Demonstrate the understanding about the functional units of a digital computer system. 2. Execute complete instruction on different types of bus architectures with control signal generation. 3. Analyse memory, multiprocessor and multicore architectures and their implications in parallel computing.
  • 4. SYLLABUS • UNIT I : Basic Structure of Computers: Functional units of computer, basic operational conceptsInstruction, processor and memory, operating steps, address, Big- and Little-endian assignments, Instructions set architecture of a CPU- Instruction Formats, Instruction sequencing, addressing modes, and instruction set classification, subroutine & parameter passing, expanding opcode, RISC and CISC. • UNIT II : Basic Processing Unit and Data Representation: Basic Concepts- Instruction execution, Bus architecture- One bus and Multi-bus, Execution of a Complete Instruction, sequencing of control signals, Hardwired control, Micro- programmed Control. Floating point numbers- representation, guard bits and rounding.
  • 5. • UNIT III : Memory & Input/output: Cache memory, Cache size vs. block size, mapping functions, replacement algorithms, Cache read/write policy, Virtual Memory, I/O mapped I/O and memories mapped I/O, interrupt and interrupt handling mechanisms, vectored interrupts, synchronous vs. asynchronous data transfer, Bus Arbitration, Direct Memory Access • UNIT IV : Pipelining: Basic concepts of pipelining, throughput and speedup, Introduction of Parallel Computing: SISD, MISD, SIMD, MIMD
  • 6. TEXT BOOKS • 1. V.C.Hamacher, Z.G.Vranesic and S.G.Zaky; Computer Organization; • 5th edition; Tata McGraw Hill, 2002. 2. W. Stallings; Computer Organization & Architecture; PHI publication; 2001. • 3. J. P. Hayes; Computer Architecture & Organization; 3rd edition; McGraw-Hill; 1998.
  • 7. REFERENCE BOOKS • 1. M Mano; Computer System and Architecture; PHI publication; 1993. • 2. A. S. Tanenbaum; Structured Computer Organization; Prentice Hall of India Ltd.