This document describes an experiment to implement a VHDL decoder design onto an FPGA board. The experiment involves:
1. Designing a 2-to-4 decoder using VHDL code and simulating the design functionally and for timing. The VHDL code is then synthesized and the design is implemented onto an FPGA board.
2. Designing a 3-to-8 decoder using two 2-to-4 decoders as components in VHDL code. The 3-to-8 decoder design is also simulated and implemented onto the FPGA board.
3. Testing and verifying the decoder designs by observing the LED outputs on the FPGA board in response to switch inputs. Results
Kroening et al, v2c a verilog to c translatorsce,bhopal
The document describes v2c, a tool that translates Verilog to C. v2c accepts synthesizable Verilog as input and generates equivalent C code called a "software netlist". The translation is based on Verilog's synthesis semantics and preserves cycle accuracy and bit precision. The generated C code can then be used for hardware property verification, co-verification, simulation, and equivalence checking by leveraging software verification techniques.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
This document discusses a lecture on combinational logic building blocks and data flow modeling of combinational logic in VHDL. It covers topics like fixed shifters and rotators, basic gates, multiplexers, decoders, adders, comparators, buffers, encoders, and uses an example of a multiplier logic unit to describe combinational logic using the data flow VHDL design style. Slides include VHDL code examples for various combinational logic components like full adders, multiplexers, decoders, comparators, and a priority encoder.
This document provides an overview of VHDL and FPGA design using VHDL. It discusses the required and recommended reading materials, gives a brief history of VHDL, and covers some VHDL fundamentals including entity declaration, architecture, libraries, port modes, and the STD_LOGIC data type. Tips are provided on formatting, naming conventions, and increasing readability and portability of VHDL designs.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
VLSI lab manual Part A, VTU 7the sem KIT-tipturPramod Kumar S
This document provides procedures for digital and analog VLSI design experiments using CAD tools. It includes the VLSI design flow, prerequisites for using the tools, verification using simulation, and synthesis. Experiments cover digital logic gates, flip-flops, adders, counters, and analog circuits like inverters, amplifiers, and data converters. The goal is to introduce students to computer-aided design of digital and analog VLSI systems.
VLSI lab manual Part B, VTU 7the sem KIT-tipturPramod Kumar S
This document provides information about VLSI design procedures for an analog design flow. It includes details on initial procedures for using Cadence tools, steps for design entry including schematic entry, symbol creation and test circuit creation. It also describes simulation procedures using ADE-L and layout procedures using Layout-XL. An example inverter design is provided with steps for schematic entry, simulation and layout. Key Cadence tools used are listed as Virtuoso schematic editor, ADE-L, Spectre and Virtuoso layout suite.
Kroening et al, v2c a verilog to c translatorsce,bhopal
The document describes v2c, a tool that translates Verilog to C. v2c accepts synthesizable Verilog as input and generates equivalent C code called a "software netlist". The translation is based on Verilog's synthesis semantics and preserves cycle accuracy and bit precision. The generated C code can then be used for hardware property verification, co-verification, simulation, and equivalence checking by leveraging software verification techniques.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
This document discusses a lecture on combinational logic building blocks and data flow modeling of combinational logic in VHDL. It covers topics like fixed shifters and rotators, basic gates, multiplexers, decoders, adders, comparators, buffers, encoders, and uses an example of a multiplier logic unit to describe combinational logic using the data flow VHDL design style. Slides include VHDL code examples for various combinational logic components like full adders, multiplexers, decoders, comparators, and a priority encoder.
This document provides an overview of VHDL and FPGA design using VHDL. It discusses the required and recommended reading materials, gives a brief history of VHDL, and covers some VHDL fundamentals including entity declaration, architecture, libraries, port modes, and the STD_LOGIC data type. Tips are provided on formatting, naming conventions, and increasing readability and portability of VHDL designs.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
VLSI lab manual Part A, VTU 7the sem KIT-tipturPramod Kumar S
This document provides procedures for digital and analog VLSI design experiments using CAD tools. It includes the VLSI design flow, prerequisites for using the tools, verification using simulation, and synthesis. Experiments cover digital logic gates, flip-flops, adders, counters, and analog circuits like inverters, amplifiers, and data converters. The goal is to introduce students to computer-aided design of digital and analog VLSI systems.
VLSI lab manual Part B, VTU 7the sem KIT-tipturPramod Kumar S
This document provides information about VLSI design procedures for an analog design flow. It includes details on initial procedures for using Cadence tools, steps for design entry including schematic entry, symbol creation and test circuit creation. It also describes simulation procedures using ADE-L and layout procedures using Layout-XL. An example inverter design is provided with steps for schematic entry, simulation and layout. Key Cadence tools used are listed as Virtuoso schematic editor, ADE-L, Spectre and Virtuoso layout suite.
This document provides an introduction to VHDL, including:
- VHDL allows modeling and developing digital systems through modules that can be reused, with in/out ports and behavioral or structural specification.
- Models can be tested through simulation and used for synthesis.
- There are three ways to specify models: dataflow, behavioral, and structural. Behavioral models describe algorithms, structural models compose subsystems.
- A test bench applies inputs to verify a model's outputs through simulation.
Verilog HDL (Hardware Description Language) Training Course for self-taught instructional. User should be familiar with basic digital and logic design. Helpful to have a Verilog simulator while going through examples.
Verilog Tutorial - Verilog HDL Tutorial with ExamplesE2MATRIX
E2MATRIX Research Lab
Opp Phagwara Bus Stand, Backside Axis Bank,
Parmar Complex, Phagwara Punjab (India).
Contact : +91 9041262727
web: www.e2matrix.com -- email: support@e2matrix.com
Simulation tools typically accept full set of Verilog language constructs
Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools
Synthesis tools typically accept only a subset of the full Verilog language constructs
In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics
There are other restrictions not detailed here, see [2].
The Module Concept
Basic design unit
Modules are:
Declared
Instantiated
Modules declarations cannot be nested
This document provides an overview of part 2 of a course on specification languages. It discusses model based system design using SystemC. It introduces object oriented techniques for designing hardware systems and provides hands-on experience with SystemC. The material for part 2 includes slides, the SystemC language reference manual, and an exercise on building a functional model of a JPEG encoder/decoder in SystemC. It discusses key aspects of functional modeling in SystemC including modules, ports, processes, channels and the simulation engine.
1. The document describes the syllabus for the VLSI Design Laboratory course for the academic year 2017-2018 at Erode Sengunthar Engineering College.
2. The syllabus includes experiments involving HDL-based design and simulation of basic components like counters and adders using FPGA tools. It also includes layout design and simulation of basic CMOS gates using CAD tools.
3. The listed experiments will be carried out in two cycles. Cycle 1 involves the implementation of components like adders, multipliers and counters on FPGA. Cycle 2 involves the design and simulation of CMOS gates using EDA tools and their layout using other CAD tools.
This document contains slides from a lecture on Verilog hardware description language. It introduces Verilog and compares it to other HDLs like VHDL. It discusses both structural and behavioral modeling in Verilog. Structural models describe a design using primitive components and their interconnections, while behavioral models describe the input-output function of a design. The document provides examples of modeling combinational logic like an AND gate and sequential logic like a 4-bit comparator using behavioral and structural Verilog. It also covers Verilog syntax like modules, ports, continuous assignments, always blocks, if/case statements.
This Presentation covers most of VHDL designing basic from scratch.
click the below link for contents
http://eutectics.blogspot.com/2014/01/how-to-design-programs-using-vhdl-all.html
This document discusses gate level modeling in Verilog HDL. It covers structural modeling using gate primitives like AND, OR, NOT, etc. It describes how to instantiate gates and model combinational logic circuits. It discusses inertial and transport delays. It also covers hazards that can occur in gate networks and their effects. The document outlines objectives like describing structural modeling, gate primitives, modeling gates, specifying delays, and hazards and their effects.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.
A brief history
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC it self stands for "Very High Speen Intergrated Circuit" BTW).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
This document provides examples of VHDL code for modeling basic logic gates and multiplexers. It begins with syntax for VHDL programs and then provides behavioral VHDL code for modeling common logic gates like AND, OR, NOR, NAND, XOR and XNOR gates. It also provides code for half adder, full adder, half subtractor and full subtractor. The document further contains VHDL code examples to model a 4-to-1 multiplexer and 1-to-4 demultiplexer using different types of statements like if-else, case, when-else and with-select.
The document provides an introduction to VHDL and discusses VHDL design flows. It outlines a course on digital system design with VHDL, including lectures on VHDL coding styles, finite state machines, and FPGA components. Example topics covered are the history of VHDL, VHDL design flows, behavioral and structural coding styles, and a cryptographic coprocessor case study.
This document discusses basic concepts in Verilog HDL including lexical conventions, data types, and system tasks and compiler directives. It covers topics such as keywords, operators, numbers, comments, nets, registers, vectors, integer/real/time data types, arrays, memories, parameters, and strings. Examples of system tasks like $display, $monitor, $stop, and $finish are provided along with examples of compiler directives like `define and `include.
The document describes designing and simulating various combinational circuits using Verilog HDL. It includes the design of an 8-bit adder, 4-bit multiplier, 3-to-8 address decoder, and 2-to-1 multiplexer. Verilog code and test benches are provided for each circuit. The circuits are simulated and waveforms are generated to verify the design and functionality.
This document provides an introduction to VHDL including:
- An overview of the goals which are to further the author's knowledge of VHDL, provide history, and introduce syntax and concepts.
- A brief history of VHDL including its origins in the 1970s and standardization in the 1980s and beyond.
- Examples of VHDL code including a 4-to-1 multiplexer, 8-bit shifter, and testbenches with explanations of the code.
The document describes designing all basic logic gates including AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. It provides the circuit symbol, logic table, and function of each gate. The aim is to design the basic logic gates using Verilog code, synthesize them using the Xilinx ISE simulator, and verify the outputs through simulation test benches. The document includes the Verilog code, RTL schematic, technology schematic, and simulations of the basic logic gates.
This document provides an overview of System Verilog concepts including simulation and synthesis, modules and primitives, styles, data types, operators, and more. Key points covered include the module concept as the basic design unit, module declaration syntax, module instantiation, different styles like structural, RTL/dataflow and behavioral, data types for nets and registers, number representation formats, and basic Verilog operators. The document serves as a tutorial introduction to essential System Verilog language constructs.
VHDL is a hardware description language used to model digital circuits. It allows modeling at different levels of abstraction like behavioral, dataflow, and structural. VHDL supports design reuse through libraries and packages. Key benefits include being public standard, technology independent, and supporting design hierarchy, simulation, synthesis and documentation. The basic units in VHDL are entities which define the interface and architectures which describe the internal implementation. Architectures contain concurrent statements that execute in parallel and sequential statements in processes that execute sequentially.
Report contains digital and analog design flow procedures in detail, working, Simulation and Synthesize mapped output. Full custom Schematic and layout design by using virtuoso encounter cadence tool.
The document provides an introduction to VHDL including its origins, domains of description, abstraction levels, modeling styles, and examples of behavioral and structural descriptions. It discusses key VHDL concepts such as entities, architectures, concurrency, hierarchy, and modeling at different levels of abstraction using both behavioral and structural descriptions. Examples include behavioral descriptions of basic components like an AND gate, full adder, D flip-flop, and 4-to-1 multiplexer as well as structural descriptions of a 4-bit adder and 4-bit comparator.
This document provides an overview of hardware description language (HDL) and VHDL. It begins with an introduction to HDLs and why they are needed to model digital hardware. It then presents an example VHDL code for an even parity detector circuit to demonstrate basic VHDL concepts like entities, architectures, signals, and concurrent statements. Finally, it discusses how VHDL fits into the digital design flow from coding to simulation to synthesis.
Connected cars are fast becoming a reality and has the potential to change the way businesses are run. A connected car facilitates devices inside the car to connect with the computing and application servers and use computing power to access real time information and data. Use cases are explained for Transportation, Healthcare and Education fields along with the business models.
IoT in Automobile industry by Shri Kaushal Jani, Project Head, Amiraj College of Engg & Technology, Ahmedabad
presented at All India Seminar on #IoT - Trends that affect Lives at The Institution of Engineers (I) Gujarat State Center
This document provides an introduction to VHDL, including:
- VHDL allows modeling and developing digital systems through modules that can be reused, with in/out ports and behavioral or structural specification.
- Models can be tested through simulation and used for synthesis.
- There are three ways to specify models: dataflow, behavioral, and structural. Behavioral models describe algorithms, structural models compose subsystems.
- A test bench applies inputs to verify a model's outputs through simulation.
Verilog HDL (Hardware Description Language) Training Course for self-taught instructional. User should be familiar with basic digital and logic design. Helpful to have a Verilog simulator while going through examples.
Verilog Tutorial - Verilog HDL Tutorial with ExamplesE2MATRIX
E2MATRIX Research Lab
Opp Phagwara Bus Stand, Backside Axis Bank,
Parmar Complex, Phagwara Punjab (India).
Contact : +91 9041262727
web: www.e2matrix.com -- email: support@e2matrix.com
Simulation tools typically accept full set of Verilog language constructs
Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools
Synthesis tools typically accept only a subset of the full Verilog language constructs
In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics
There are other restrictions not detailed here, see [2].
The Module Concept
Basic design unit
Modules are:
Declared
Instantiated
Modules declarations cannot be nested
This document provides an overview of part 2 of a course on specification languages. It discusses model based system design using SystemC. It introduces object oriented techniques for designing hardware systems and provides hands-on experience with SystemC. The material for part 2 includes slides, the SystemC language reference manual, and an exercise on building a functional model of a JPEG encoder/decoder in SystemC. It discusses key aspects of functional modeling in SystemC including modules, ports, processes, channels and the simulation engine.
1. The document describes the syllabus for the VLSI Design Laboratory course for the academic year 2017-2018 at Erode Sengunthar Engineering College.
2. The syllabus includes experiments involving HDL-based design and simulation of basic components like counters and adders using FPGA tools. It also includes layout design and simulation of basic CMOS gates using CAD tools.
3. The listed experiments will be carried out in two cycles. Cycle 1 involves the implementation of components like adders, multipliers and counters on FPGA. Cycle 2 involves the design and simulation of CMOS gates using EDA tools and their layout using other CAD tools.
This document contains slides from a lecture on Verilog hardware description language. It introduces Verilog and compares it to other HDLs like VHDL. It discusses both structural and behavioral modeling in Verilog. Structural models describe a design using primitive components and their interconnections, while behavioral models describe the input-output function of a design. The document provides examples of modeling combinational logic like an AND gate and sequential logic like a 4-bit comparator using behavioral and structural Verilog. It also covers Verilog syntax like modules, ports, continuous assignments, always blocks, if/case statements.
This Presentation covers most of VHDL designing basic from scratch.
click the below link for contents
http://eutectics.blogspot.com/2014/01/how-to-design-programs-using-vhdl-all.html
This document discusses gate level modeling in Verilog HDL. It covers structural modeling using gate primitives like AND, OR, NOT, etc. It describes how to instantiate gates and model combinational logic circuits. It discusses inertial and transport delays. It also covers hazards that can occur in gate networks and their effects. The document outlines objectives like describing structural modeling, gate primitives, modeling gates, specifying delays, and hazards and their effects.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.
A brief history
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC it self stands for "Very High Speen Intergrated Circuit" BTW).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
This document provides examples of VHDL code for modeling basic logic gates and multiplexers. It begins with syntax for VHDL programs and then provides behavioral VHDL code for modeling common logic gates like AND, OR, NOR, NAND, XOR and XNOR gates. It also provides code for half adder, full adder, half subtractor and full subtractor. The document further contains VHDL code examples to model a 4-to-1 multiplexer and 1-to-4 demultiplexer using different types of statements like if-else, case, when-else and with-select.
The document provides an introduction to VHDL and discusses VHDL design flows. It outlines a course on digital system design with VHDL, including lectures on VHDL coding styles, finite state machines, and FPGA components. Example topics covered are the history of VHDL, VHDL design flows, behavioral and structural coding styles, and a cryptographic coprocessor case study.
This document discusses basic concepts in Verilog HDL including lexical conventions, data types, and system tasks and compiler directives. It covers topics such as keywords, operators, numbers, comments, nets, registers, vectors, integer/real/time data types, arrays, memories, parameters, and strings. Examples of system tasks like $display, $monitor, $stop, and $finish are provided along with examples of compiler directives like `define and `include.
The document describes designing and simulating various combinational circuits using Verilog HDL. It includes the design of an 8-bit adder, 4-bit multiplier, 3-to-8 address decoder, and 2-to-1 multiplexer. Verilog code and test benches are provided for each circuit. The circuits are simulated and waveforms are generated to verify the design and functionality.
This document provides an introduction to VHDL including:
- An overview of the goals which are to further the author's knowledge of VHDL, provide history, and introduce syntax and concepts.
- A brief history of VHDL including its origins in the 1970s and standardization in the 1980s and beyond.
- Examples of VHDL code including a 4-to-1 multiplexer, 8-bit shifter, and testbenches with explanations of the code.
The document describes designing all basic logic gates including AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. It provides the circuit symbol, logic table, and function of each gate. The aim is to design the basic logic gates using Verilog code, synthesize them using the Xilinx ISE simulator, and verify the outputs through simulation test benches. The document includes the Verilog code, RTL schematic, technology schematic, and simulations of the basic logic gates.
This document provides an overview of System Verilog concepts including simulation and synthesis, modules and primitives, styles, data types, operators, and more. Key points covered include the module concept as the basic design unit, module declaration syntax, module instantiation, different styles like structural, RTL/dataflow and behavioral, data types for nets and registers, number representation formats, and basic Verilog operators. The document serves as a tutorial introduction to essential System Verilog language constructs.
VHDL is a hardware description language used to model digital circuits. It allows modeling at different levels of abstraction like behavioral, dataflow, and structural. VHDL supports design reuse through libraries and packages. Key benefits include being public standard, technology independent, and supporting design hierarchy, simulation, synthesis and documentation. The basic units in VHDL are entities which define the interface and architectures which describe the internal implementation. Architectures contain concurrent statements that execute in parallel and sequential statements in processes that execute sequentially.
Report contains digital and analog design flow procedures in detail, working, Simulation and Synthesize mapped output. Full custom Schematic and layout design by using virtuoso encounter cadence tool.
The document provides an introduction to VHDL including its origins, domains of description, abstraction levels, modeling styles, and examples of behavioral and structural descriptions. It discusses key VHDL concepts such as entities, architectures, concurrency, hierarchy, and modeling at different levels of abstraction using both behavioral and structural descriptions. Examples include behavioral descriptions of basic components like an AND gate, full adder, D flip-flop, and 4-to-1 multiplexer as well as structural descriptions of a 4-bit adder and 4-bit comparator.
This document provides an overview of hardware description language (HDL) and VHDL. It begins with an introduction to HDLs and why they are needed to model digital hardware. It then presents an example VHDL code for an even parity detector circuit to demonstrate basic VHDL concepts like entities, architectures, signals, and concurrent statements. Finally, it discusses how VHDL fits into the digital design flow from coding to simulation to synthesis.
Connected cars are fast becoming a reality and has the potential to change the way businesses are run. A connected car facilitates devices inside the car to connect with the computing and application servers and use computing power to access real time information and data. Use cases are explained for Transportation, Healthcare and Education fields along with the business models.
IoT in Automobile industry by Shri Kaushal Jani, Project Head, Amiraj College of Engg & Technology, Ahmedabad
presented at All India Seminar on #IoT - Trends that affect Lives at The Institution of Engineers (I) Gujarat State Center
I guess everyone have little knowledge about connected car technology as it has been newly introduced to auto industry. This presentation explains some common features of it i.e. Music app, Navigation, Automotive system diagnosis, Bluetooth, Road-side assistance, Hands-free control, Contextual help, Parking help, App manager, 4G Wi-Fi hotspot, ADAS etc. The most demanded features of connected car are the In-car safety features and vehicle-to-vehicle safety features. Check out for details.
The Internet of Cars - Towards the Future of the Connected CarJorgen Thelin
No doubt you have heard the phrase “Internet of Things” and the new buzzword “IoT” been used more and more these days, but what does that mean in practice? The Tesla Model S is probably the most well-connected car on the planet at the moment, and in this presentation we will use that vehicle as a case study of some practical usage of IoT concepts and technology that is already being applied to modern automobiles.How far away are we from a future “Internet of Cars” and what will be the social and privacy impacts of more connected-car scenarios?
Covering the state of the internet-connected automobile, with the experts at Strategy Analytics and IBM. We discuss:
- The challenges of the connected car
- Creating an optimal connected experience
- IBM enabling technologies
This document outlines key concepts in customer-driven marketing strategy, including market segmentation, targeting, differentiation, and positioning. It discusses how companies divide large markets into smaller segments and how to evaluate and select target market segments. It also covers identifying competitive advantages, developing positioning strategies, and communicating the chosen position to deliver value to target customers.
This document provides an overview of customer-driven marketing strategies, including market segmentation, targeting, differentiation, and positioning. It discusses how segmentation involves dividing the market into meaningful and measurable segments based on variables like geography, demographics, behaviors, and benefits sought. Effective targeting requires evaluating segments and selecting ones for the company to focus on based on factors like size, growth, and fit with objectives. Differentiation and positioning involve identifying competitive advantages to build a unique value proposition and position for targeted segments. The key aspects of a customer-driven strategy are measuring segments, choosing the right targets, and communicating a clear unique value or position.
This document describes an experiment on digital circuit design using VHDL and the Altera Quartus II software. The objectives are to learn VHDL design entry and simulation in Quartus II. It outlines designing a half adder and full adder circuit in VHDL, including obtaining the truth tables, deriving the Boolean expressions, writing the VHDL code, and simulating the designs functionally and for timing. Students are asked questions about the half adder and full adder designs, as well as general questions about digital design flows and VHDL.
This document provides an overview of getting started with Vivado, Xilinx's IDE for FPGA design and implementation. It describes how to create a Vivado project targeting a Nexys4 DDR board, add VHDL source files to implement a simple 2-input logic AND gate, add a user constraints file to map design pins to board pins, run synthesis, implementation and bitstream generation to create a programming file, and use the hardware manager to download the bitstream and verify the design functionality on the board. The objectives are to create a Vivado project from HDL sources targeting a specific FPGA, constrain pin locations, synthesize, implement and generate a bitstream to program the FPGA.
This PDF serves as a practical guide to microprocessors and controllers for electrical engineering students at Sarvajanik College of Engineering and Technology (SCET GTU). It goes beyond theory, offering practical solutions and applications tailored to the SCET GTU curriculum.
This resource aims to equip students with the skills to implement and utilize microprocessors and controllers effectively in real-world electrical engineering projects.
The document describes using an IP core in a Xilinx FPGA design. Specifically, it discusses:
1) Creating an adder/subtractor IP core using the Xilinx CORE Generator.
2) Connecting the IP core as a component in a top-level VHDL file.
3) Synthesizing and programming the design onto a Spartan 3E FPGA board to test the four-bit adder/subtractor functionality.
This document provides a tutorial on creating a simple project in Xilinx ISE 9.2. It involves starting a new project, selecting device properties, adding and writing a VHDL source file with inputs, outputs, and a counter, creating a constraint file, generating a configuration file, and uploading the configuration to an FPGA device. The overall process demonstrates how to set up a basic project from start to loading a design on an FPGA.
This document provides an overview of the VHDL design flow process from modeling a digital system in VHDL to implementing it in an FPGA. It describes 5 main steps: 1) design entry using a hardware description language like VHDL, 2) functional simulation to verify logical behavior, 3) synthesis to convert the design to logic gates and components, 4) implementation which places and routes the design in the target FPGA, and 5) generating a configuration bitstream file to download to the FPGA. It then guides the reader through an example of designing an 8-bit up/down counter using this flow in Xilinx tools including writing VHDL code, simulating in ModelSim, and synthesizing and
This document provides instructions for generating patterns on LEDs using an 8051 microcontroller. It describes using ports on the 8051 as output ports to interface with LEDs. A delay subroutine is created using loops to generate delays. The code is tested using Proteus simulation software. The document also provides steps for programming the 8051 chip using a SmartPro programmer and debugging techniques for microcontroller programs. The lab tasks involve blinking LEDs in different patterns with a 100ms delay between patterns.
This document provides an overview of Verilog, including:
- Verilog is a hardware description language used to describe digital systems at different levels including switch, gate, and register transfer levels.
- It discusses the basics of Verilog, common simulation tools, design methodology, modules, ports, data types, assignments, primitives, test benches, and provides a tutorial for using Active-HDL for simulation.
The document provides instructions for using a Xilinx Virtex-II Pro development board with FPGA for a computer organization course lab. It describes the components on the board, cautions for safety and backups, and steps to create a basic Verilog project in Xilinx ISE to program the FPGA to connect the on-board switches to LEDs.
This book is written by Mr.Joseph Attard, a Senior lecturer II working at Malta College for Arts Science and Technology on the island of Malta. In this book, Joseph shared a lot of content on how to work with MYIR's Z-turn board, starting from simply creating a project in Vivado to flash an LED, continuing to Detecting Switch inputs, all the way to interfacing the Xilinx Zynq 7 System on Chip to multiple analogue sensors through multiple XADC channels. All the above-mentioned interfacing is done from both the ARM Cortex A9, commonly known as the Processing System and the Artix 7 FPGA, commonly known as Programmable Logic, both residing within the Zynq 7000 SoC.
15LLP108_Demo4_LedBlinking.pdf1. Introduction In D.docxfelicidaddinwoodie
15LLP108_Demo4_LedBlinking.pdf
1. Introduction
In Demo3, we have learned how to read sensor values of light, temperature and humidity of a node
and output these values to the console. In this demonstration, we will use the code from Demo3 and
learn how to turn on/off the LEDs and make them blinking regularly on the sensor node XM1000,
meanwhile to count how many times the LED has blinked and output the count to the console.
2. Timer
In order to make the blue LED on the XM1000 sensor node to blink in every half second (i.e. On 0.5S
and Off 0.5S), we also need a timer. Follow the instructions in Demo3 for configure and reset a timer.
We aslo need to create an infinite while() loop so that it runs our functions repeatedly, such as
counting the times the LED has blinked, output the counter’s value and actually turn on or off the
LEDs to make it blinking.
Please follow timer and while() loop structure in Demo3.
3. LED Blinking
To get access to the LED functionalities in Contiki, we need to include the LED header file in the
source code:
#include "leds.h" // file is in directory /home/user/contiki/core/dev
After the process begin, we have to initialise the LEDs on the sensor node by calling the following
function:
leds_init(); // Initialise the LEDs
And finally we can turn on, off, or blink the LEDs by the following functions:
void leds_on(unsigned char leds);
void leds_off(unsigned char leds);
void leds_toggle(unsigned char leds);
void leds_invert(unsigned char leds);
For example, if you want to blink the Blue LED, yon need to call the toggle function as:
void leds_toggle(LEDS_BLUE); // Toggle the blue LED
4. Exercise
Modify the program from Demo3 with periodic timer to make the BLUE led blinking in every half
second, also to count the blinking times and output the counted number to the console.
Can your change the code so that the BLUE LED is lighted for 1 second and off for 0.5 second
periodically?
15LLP108 – Internet of Things and Applications
Lab Session 2: Demo 4 – LED Blinking
Prepared by Xiyu Shi
5. Source code
Here is the source code for reference
#include "contiki.h"
#include "leds.h"
#include <stdio.h> /* for printf() */
static struct etimer timer;
/*____________________________________________________*/
PROCESS(led_blinking_process, "LED Blinking Process");
PROCESS(LED_process, "LED process");
AUTOSTART_PROCESSES(&LED_process);
/*____________________________________________________*/
PROCESS_THREAD(LED_process, ev, data)
{
static int count = 0;
PROCESS_BEGIN();
etimer_set(&timer, CLOCK_CONF_SECOND/2); // 0.5S timer
leds_init(); // intialise the LEDs
while(1) {
PROCESS_WAIT_EVENT_UNTIL(ev==PROCESS_EVENT_TIMER); // wait for timer event
count++; // count the blinking times
process_start(&led_blinking_process, NULL); // to blink the BLUE Led
printf("Count: %d\n", count); // output the counte ...
We are one of the best embedded systems training institute for advance courses. We are the pioneer of the embedded system training in Pune & Pcmc with the expertise of over 16 years. we are working in the field training & development of embedded systems & currently we are also working on live projects as per the requirements of clients. though we provide many different courses & training in embedded all aim at giving good practical knowledge to students as well help them in their career.
We are one of the best embedded systems training institute for advance courses. We are the pioneer of the embedded system training in Pune & Pcmc with the expertise of over 16 years. we are working in the field training & development of embedded systems & currently we are also working on live projects as per the requirements of clients. though we provide many different courses & training in embedded all aim at giving good practical knowledge to students as well help them in their career.
This document provides a tutorial on Verilog HDL (Hardware Description Language). It discusses that HDLs like Verilog and VHDL are used to describe hardware using code. Verilog allows designers to describe designs at different levels of abstraction. Digital systems are highly complex, and Verilog provides a software platform for designers to express their designs with behavioral constructs. A Verilog program can be converted to a description used to manufacture chips like VLSI. The document then covers various Verilog topics like modules, ports, data types, always blocks, structural modeling, dataflow modeling, and behavioral modeling.
CCFE is the fusion research arm of the United Kingdom Atomic Energy Authority. This work was funded by the RCUK Energy Programme [grant number EP/I501045]. Developing new Zynq based instruments using Koheron-SDK graham.naylor@ccfe.ac.uk provides an overview of developing instruments using the Koheron SDK on Zynq FPGAs including setting up the SDK, writing IP cores, defining instruments, building and testing on the Red Pitaya board, and developing a web interface.
The Principle Of Ultrasound Imaging SystemMelissa Luster
The document describes a project to design an audio amplifier system that incorporates digital delay effects, where the system uses an FPGA platform to implement the design and includes components like sensors, ADCs, and DACs to acquire analog audio signals, convert them to digital, process them with digital delay effects using the FPGA, and convert them back to analog for output. The goal is to add effects like reverb and echo to the audio in real-time using programmable digital logic on the FPGA rather than traditional analog circuitry for such effects.
This document provides a user's guide for implementing digital logic designs on Altera's UP 1 Educational Board using their MAX+plus II CAD software. It introduces a 4-bit binary counter design example to demonstrate the design process. The steps covered include entering the design schematically, performing functional simulation, synthesizing the design for the FPGA, and downloading the design onto the UP 1 board. The guide is organized into chapters that cover general information about the UP 1 board and MAX+plus II tools, the binary counter example, and combining schematic and hardware description language approaches.
This document provides instructions for creating and simulating a counter design using the Xilinx ISE design suite. It describes how to start ISE, create a new project, add a VHDL source file to define the counter module, generate a testbench waveform to simulate the design, and view the simulation results. Key steps include using language templates to add behavioral code to the counter, initializing timing settings for the testbench, and generating expected output values to create a self-checking testbench.
Filter designandanalysisusingmicrowaveofficeEmad S. Ahmed
This document provides supplementary information for a module that introduces RF/microwave filter design using the CAD tool Microwave Office (MWO). It describes the specific steps shown in setting up a low-pass filter project in MWO and provides instructions for a band-pass filter design project. It also includes step-by-step instructions for obtaining a student version of MWO.
This slide is special for master students (MIBS & MIFB) in UUM. Also useful for readers who are interested in the topic of contemporary Islamic banking.
How to Setup Warehouse & Location in Odoo 17 InventoryCeline George
In this slide, we'll explore how to set up warehouses and locations in Odoo 17 Inventory. This will help us manage our stock effectively, track inventory levels, and streamline warehouse operations.
ISO/IEC 27001, ISO/IEC 42001, and GDPR: Best Practices for Implementation and...PECB
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This presentation includes basic of PCOS their pathology and treatment and also Ayurveda correlation of PCOS and Ayurvedic line of treatment mentioned in classics.
How to Fix the Import Error in the Odoo 17Celine George
An import error occurs when a program fails to import a module or library, disrupting its execution. In languages like Python, this issue arises when the specified module cannot be found or accessed, hindering the program's functionality. Resolving import errors is crucial for maintaining smooth software operation and uninterrupted development processes.
How to Manage Your Lost Opportunities in Odoo 17 CRMCeline George
Odoo 17 CRM allows us to track why we lose sales opportunities with "Lost Reasons." This helps analyze our sales process and identify areas for improvement. Here's how to configure lost reasons in Odoo 17 CRM
বাংলাদেশের অর্থনৈতিক সমীক্ষা ২০২৪ [Bangladesh Economic Review 2024 Bangla.pdf] কম্পিউটার , ট্যাব ও স্মার্ট ফোন ভার্সন সহ সম্পূর্ণ বাংলা ই-বুক বা pdf বই " সুচিপত্র ...বুকমার্ক মেনু 🔖 ও হাইপার লিংক মেনু 📝👆 যুক্ত ..
আমাদের সবার জন্য খুব খুব গুরুত্বপূর্ণ একটি বই ..বিসিএস, ব্যাংক, ইউনিভার্সিটি ভর্তি ও যে কোন প্রতিযোগিতা মূলক পরীক্ষার জন্য এর খুব ইম্পরট্যান্ট একটি বিষয় ...তাছাড়া বাংলাদেশের সাম্প্রতিক যে কোন ডাটা বা তথ্য এই বইতে পাবেন ...
তাই একজন নাগরিক হিসাবে এই তথ্য গুলো আপনার জানা প্রয়োজন ...।
বিসিএস ও ব্যাংক এর লিখিত পরীক্ষা ...+এছাড়া মাধ্যমিক ও উচ্চমাধ্যমিকের স্টুডেন্টদের জন্য অনেক কাজে আসবে ...
Strategies for Effective Upskilling is a presentation by Chinwendu Peace in a Your Skill Boost Masterclass organisation by the Excellence Foundation for South Sudan on 08th and 09th June 2024 from 1 PM to 3 PM on each day.
Community pharmacy- Social and preventive pharmacy UNIT 5
Lab mke1503 mee10203 02
1. Faculty of Electrical and Electronic Engineering Page 1/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
AIM: To examine the decoder design using VHDL
1.0 OBJECTIVES
(i) To design decoder using VHDL design entry.
(ii) To configure and implement the design onto FPGA board.
2.0 THEORY
A VHDL code can be implemented using Field Programmable Gate Array (FPGA) board.
Figure 1 shows the general flow for programming HDL and figure 2 presents the process for
downloading a design to the target device. For this lab experiment, we will use
CPLD/FPGA trainer.
Figure 1: General design flow diagram for programming HDL code and downloading to
board/hardware.
3.0 LABORATORY REQUIREMENT:
Personal Computer with Altera Quartus II software
CPLD/FPGA trainer unit
2. Faculty of Electrical and Electronic Engineering Page 2/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
4.0 PROCEDURE
Starting a New Project
1. To start working on a new design, first you have to define a new designed project.
2. Select File | New Project Wizard to start a new project. Press Next. Set the working
directory to be C:No.MatrikLAB2dec2to4. The project must have a name, which
may optionally be the same as the name of the directory.
3. Name your project as dec2to4 and press Next which leads to the window in Figure 2.
In this window the designer can specify which existing files (if any) should be included
in the project. We have no existing files, so click Next.
C:No.MatrikLAB2dec2to4
dec2to4
dec2to4
Figure 2: Specifying the project directory and name
3. Faculty of Electrical and Electronic Engineering Page 3/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
Figure 3: A window for inclusion of design files
Figure 4 Inclusion of other EDA tools
4. Now, the window in Figure 4 appears, which allows the designer to specify third party
CAD tools (i.e. those that are not a part of the Quartus II software) that should be
used.
5. Press Next to go to the Device Family window. Here you can specify the type of
device in which the designed circuit will be implemented. Choose the device family
called Cyclone.
6. Then click Finish.
4. Faculty of Electrical and Electronic Engineering Page 4/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
Part A(1): Design 2 to 4 decoder Using VHDL
In this section, you will use Quartus II to implement logic functions by writing VHDL code.
Decoder is used to decode encoded information. In general, an x to y decoder has x select bits
and y=2x outputs.
Circuit specification
1. The 2 bit select word is denoted by w1w0 and the output lines are y0y1y2y3. Thus, this
is called 2 to 4 decoder.
2. The truth table of 2 to 4 decoder is shown in Table 1. Each select bit w1w0 is
equivalent of decimal number n and activates the output line by yn by setting it to logic
„1‟ level while the remaining lines are held at logic „0‟ values.
Table 1 : Truth table for 2 to 4 decoder
Figure 5: 2 to 4 decoder (a) block diagram and (b)internal circuit
5. Faculty of Electrical and Electronic Engineering Page 5/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
Design Entry
1. Create a new project for the VHDL design in the directory C:LAB2 dec2to4. Name
the new project as dec2to4.
2. Select File | New, choose VHDL File, and click OK. This opens the Text Editor
window. The first step is to specify a name for the file that will be created. Select File |
Save As to open the Save As pop-up window. In the box labeled File name type
dec2to4. (Make sure that the extension is VHDL File).
3. Enter the code shown in Figure 6 into the Text Editor window. (Make sure that entity
name must be same as file name, in this case, dec2to4).
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY dec2to4 IS
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(0 TO 3);
LED_COM : OUT STD_LOGIC);
END dec2to4;
ARCHITECTURE Behavior OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
Enw <= En & w;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS;
LED_COM <= ‘1’;
END Behavior;
Figure 6: VDHL code for 2 to 4 decoder
4. Save the file, by using File | Save or shortcut Ctrl-s.
5. Now synthesize your code by select Processing | Start | Start Analysis and
Synthesis.
6. Run the Compiler by selecting Processing | Start Compilation. Successful (or
unsuccessful) compilation is indicated in a pop-up box. View the report by selecting
Processing | Compilation Report. If the compilation is unsuccessful, expand the
Analysis & Synthesis part of the report and then select Messages to have the
6. Faculty of Electrical and Electronic Engineering Page 6/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
Messages displayed. Double-click on the first error message or select Errors.
Quartus II software responds By opening the VHDL file and highlighting the statement
which is affected by the error. Correct the error and recompile the design.
7. Perform the functional and timing simulation, verify and discuss your result in the
report. Before the circuit can be simulated, it is necessary to create the desired
waveforms, called test vectors, to represent the input signals.
a. Open the Waveform Editor window by selecting File | New. Click on the Other
Files tab. Choose Vector Waveform File and click OK.
b. The Waveform Editor window will appear. Save the file under the name
dec2to4.vwf.
c. Set the desired simulation to run from 0 to 160 ns by selecting Edit | End Time
and entering 160 ns in the dialog box that pops up. Select View | Fit in Window
to display the entire simulation range of 0 to 160 ns in the window.
d. Next, you must include the input and output nodes of the circuit to be simulated.
This is done by using the Node Finder utility. Click Edit | Insert Node or Bus to
open the Insert Node or Bus window.
e. Click Node Finder… button to list out all nodes in the circuit. Since we are
interested in input and output pins, set the filter to Pins: all. Click the List button
to find the input and output nodes.
f. Set the variation of inputs.
g. A circuit can be simulated in two ways. The simplest way is to assume that logic
elements and interconnection wires are perfect, thus causing no delay in
propagation of signals through the circuit. This is called functional simulation. To
perform the functional simulation, select Assignments | Setting to open the
Settings window. On the left side of this window, click on Simulator and choose
Functional as the simulation mode. Click OK and save the waveform as
dec2to4.vwf.
h. To complete the set up of the simulator select the command Processing |
Generate Functional Simulation Netlist.
i. Run the simulation process by select Processing | Start Simulation. After the
simulation process is completed, press open to view the simulation result.
j. Repeat step g and i for timing simulation.
(Q1) Sketch functional simulation waveform for VHDL code in figure 6. (2 marks)
(Q2) Sketch timing simulation waveform for VHDL code in figure 6. (2 marks)
(Q3) Analyze the results for both functional and timing simulations. (10 marks)
7. Faculty of Electrical and Electronic Engineering Page 7/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
Part A(2): Download 2 to 4 decoder code on CPLD/FPGA board.
Floorplan
8. Go back to the “dec2to4.vhd” file.
9. Select the FLEX10K – EPF10K10TC144-4 device by selecting Assignment | Device
from the menu bar. Next, assign pin numbers to all of the input and output nodes using
Table 2 as a reference.
Table 2 – Pin assignments for dec2to4
Node Type Node Pin Number Device
En 47 SW1
INPUTS w0 48 SW2
w1 49 SW3
y0 20 L12
y1 19 L11
OUTPUT y2 18 L10
y3 17 L9
LED_COM 141 LED_COM
10. To assign a pin, select Assignment | Pins. The pin assignment window will
appear. To assign pin number 51 to node “SW1”, Select the pin number 51 in
“Location” text box and type “SW1” in the “pin name” text box. Repeat the pin
assignment process for the other nodes.
11. Then, compile the design.
Download and Test
12. Start the programmer by selecting Tools | Programmer to open the programmer
window.
13. Switch on the CPLD/FPGA trainer unit. Next, in the programmer window, click
Hardware Setup button. In the hardware setup window, click the Add Hardware
button. Select ByteBlaster II for hardware type and LPT1 for the port. Next,
highlight the ByteBlaster II and click Select Hardware button. This will enable the
Start button in programmer window.
14. Alternatively, we can click Add File button to add the SRAM Object File (*.sof) (in
this case, “dec2to4.sof”). Next, Click the start button to download the design to
the target hardware.
15. Test and verify the circuit by pressing the SWs push buttons and observing
LEDs.
(Q4) Compute a truth table associated with your observation on LEDs. (8 marks)
(Q5) Write a brief discussion for your experience on the process of realizing 2-to-4
decoder using FPGA. (15 marks)
8. Faculty of Electrical and Electronic Engineering Page 8/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
(Q6) Write a summary for Part A. (5 marks)
Part B(1): Design 3 to 8 Decoder using VHDL
Circuit Specification
3 to 8 decoder can be constructed with two 2 to 4 decoder and other additional gates. This
is done by define the decoder 2 to 4 as a component in the package. The component
declaration allows the entity to be used as a sub circuit in other VHDL code.
Design Entry
1. Create a new project for the VHDL design in the directory C:LAB2dec3to8. Name
the new project as dec3to8.
2. Repeat the procedure in Part A 1 – 6. With the aid of Quartus II, write the VHDL code
using structural modeling that implement the circuit in Figure 7. Save the file as a
dec3to8.vhd.
Figure 7 : 3 to 8 decoder using 2 to 4 decoder circuit
(Q7) Compute VHDL code for implementing the 3-to-8 decoder in Figure 7. (10
marks)
(Q8) Sketch timing simulation waveform for 3-to-8 decoder in Figure 7. (4 marks)
(Q9) Analyze the simulation result. (10 marks)
9. Faculty of Electrical and Electronic Engineering Page 9/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
Part B(2): Download 3 to 8 decoder code on CPLD/FPGA board.
Floorplan
3. Go back to the “dec3to8.vhd” file.
4. Select the FLEX10K – EPF10K10TC144-4 device by selecting Assignment | Device
from the menu bar. Next, assign pin numbers to all of the input and output nodes using
Table 3 as a reference.
Table 3 – Pin assignments for 3 to 8 decoder
Node Type Node Pin Number Device
En 47 SW1
w0 48 SW2
INPUTS
w1 49 SW3
w2 51 SW4
y0 20 L12
y1 19 L11
y2 18 L10
y3 17 L9
OUTPUTS y4 14 L8
y5 13 L7
y6 12 L6
y7 11 L5
LED_COM 141 LED_COM
. 5. To assign a pin, select Assignment | Pins. The pin assignment window will
appear. To assign pin number 47 to node “SW4”, Select the pin number 47 in
“Location” text box and type “SW4” in the “pin name” text box. Repeat the pin
assignment process for the other nodes.
6. Then, compile the design.
7. Download the program by start the programmer by selecting Tools | Programmer to
open the programmer window.
8. Test and verify the circuit by pressing the SWs push buttons and observing LEDs.
(Q10)Compute a truth table associated with your observation on LEDs. (8 marks)
(Q11) Write a brief discussion on your experience for developing 3-to-8 decoder
using FPGA. (15 marks)
(Q12) Write a summary for the task done in Part B. (5 marks)
10. Faculty of Electrical and Electronic Engineering Page 10/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code
QUESTIONS
1. Briefly explain the VHDL code in Fig.1. (4 marks)
Enw <= En & w;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS;
Fig. 1
2. Rewrite the VHDL code in Fig. 1 using conditional assignment statement. (6 marks)
3. State four (4) advantages of using VHDL design entry compared with schematic design
entry. (4 marks)
4. Describe two approaches for declaring a VHDL code as sub-circuit in another VHDL
code. (6 marks)
INSTRUCTION
This report must be completed and submit to the laboratory instructor ONE day after the
laboratory session.
Your report must include all the questions in Question Section.
The report must be compiled with your handwriting.
11. Faculty of Electrical and Electronic Engineering Page 11/11
Department of Computer Engineering Session 2011/2012
Experiment’s Title: FPGA implementation of Semester II
VHDL code