VLSI

1. Introduction to
CMOS VLSI
Design
Lecture 0: Introduction
David Harris
Harvey Mudd College
Spring 2004

2. 0: Introduction Slide 2
CMOS VLSI Design
Administrivia
q Name Tents
q Syllabus
– About the Instructor
– Office Hours & Lab Assistant Hours
– Labs, Problem Sets, and Project
– Grading
– Collaboration
q Textbook
q Cross-cultural Chip Design

3. 0: Introduction Slide 3
CMOS VLSI Design
Introduction
q Integrated circuits: many transistors on one chip.
q Very Large Scale Integration (VLSI): very many
q Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
q Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
q Rest of the course: How to build a good CMOS chip

4. 0: Introduction Slide 4
CMOS VLSI Design
Silicon Lattice
q Transistors are built on a silicon substrate
q Silicon is a Group IV material
q Forms crystal lattice with bonds to four neighbors
Si Si
Si
Si Si
Si
Si Si
Si

5. 0: Introduction Slide 5
CMOS VLSI Design
Dopants
q Silicon is a semiconductor
q Pure silicon has no free carriers and conducts poorly
q Adding dopants increases the conductivity
q Group V: extra electron (n-type)
q Group III: missing electron, called hole (p-type)
As Si
Si
Si Si
Si
Si Si
Si
B Si
Si
Si Si
Si
Si Si
Si
-
+
+
-

6. 0: Introduction Slide 6
CMOS VLSI Design
p-n Junctions
q A junction between p-type and n-type semiconductor
forms a diode.
q Current flows only in one direction
p-type n-type
anode cathode

7. 0: Introduction Slide 7
CMOS VLSI Design
nMOS Transistor
q Four terminals: gate, source, drain, body
q Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
– Even though gate is
no longer made of metal
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+

8. 0: Introduction Slide 8
CMOS VLSI Design
nMOS Operation
q Body is commonly tied to ground (0 V)
q When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S

9. 0: Introduction Slide 9
CMOS VLSI Design
nMOS Operation Cont.
q When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
Gate
Source Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S

10. 0: Introduction Slide 10
CMOS VLSI Design
pMOS Transistor
q Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
SiO2
n
Gate
Source Drain
bulk Si
Polysilicon
p+ p+

11. 0: Introduction Slide 11
CMOS VLSI Design
Power Supply Voltage
q GND = 0 V
q In 1980’s, VDD = 5V
q VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
q VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

12. 0: Introduction Slide 12
CMOS VLSI Design
Transistors as Switches
q We can view MOS transistors as electrically
controlled switches
q Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF

13. 0: Introduction Slide 13
CMOS VLSI Design
CMOS Inverter
1
0
Y
A VDD
A Y
GND
A Y

14. 0: Introduction Slide 14
CMOS VLSI Design
CMOS Inverter
0
1
0
Y
A VDD
A=1 Y=0
GND
ON
OFF
A Y

15. 0: Introduction Slide 15
CMOS VLSI Design
CMOS Inverter
0
1
1
0
Y
A VDD
A=0 Y=1
GND
OFF
ON
A Y

16. 0: Introduction Slide 16
CMOS VLSI Design
CMOS NAND Gate
1
1
0
0
A
1
0
1
0
Y
B
A
B
Y

17. 0: Introduction Slide 17
CMOS VLSI Design
CMOS NAND Gate
1
1
0
0
A
1
0
1
1
0
Y
B
A=0
B=0
Y=1
OFF
ON ON
OFF

18. 0: Introduction Slide 18
CMOS VLSI Design
CMOS NAND Gate
1
1
0
0
A
1
1
0
1
1
0
Y
B
A=0
B=1
Y=1
OFF
OFF ON
ON

19. 0: Introduction Slide 19
CMOS VLSI Design
CMOS NAND Gate
1
1
0
0
A
1
1
1
0
1
1
0
Y
B
A=1
B=0
Y=1
ON
ON OFF
OFF

20. 0: Introduction Slide 20
CMOS VLSI Design
CMOS NAND Gate
1
1
0
0
A
1
1
1
0
0
1
1
0
Y
B
A=1
B=1
Y=0
ON
OFF OFF
ON

21. 0: Introduction Slide 21
CMOS VLSI Design
CMOS NOR Gate
1
1
0
0
A
0
1
0
0
0
1
1
0
Y
B
A
B
Y

22. 0: Introduction Slide 22
CMOS VLSI Design
3-input NAND Gate
q Y pulls low if ALL inputs are 1
q Y pulls high if ANY input is 0

23. 0: Introduction Slide 23
CMOS VLSI Design
3-input NAND Gate
q Y pulls low if ALL inputs are 1
q Y pulls high if ANY input is 0
A
B
Y
C

24. 0: Introduction Slide 24
CMOS VLSI Design
CMOS Fabrication
q CMOS transistors are fabricated on silicon wafer
q Lithography process similar to printing press
q On each step, different materials are deposited or
etched
q Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

25. 0: Introduction Slide 25
CMOS VLSI Design
Inverter Cross-section
q Typically use p-type substrate for nMOS transistors
q Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

26. 0: Introduction Slide 26
CMOS VLSI Design
Well and Substrate Taps
q Substrate must be tied to GND and n-well to VDD
q Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
q Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND VDD
n+
p+
substrate tap well tap
n+ p+

27. 0: Introduction Slide 27
CMOS VLSI Design
Inverter Mask Set
q Transistors and wires are defined by masks
q Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor

28. 0: Introduction Slide 28
CMOS VLSI Design
Detailed Mask Views
q Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well

29. 0: Introduction Slide 29
CMOS VLSI Design
Fabrication Steps
q Start with blank wafer
q Build inverter from the bottom up
q First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate

30. 0: Introduction Slide 30
CMOS VLSI Design
Oxidation
q Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2

31. 0: Introduction Slide 31
CMOS VLSI Design
Photoresist
q Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
p substrate
SiO2
Photoresist

32. 0: Introduction Slide 32
CMOS VLSI Design
Lithography
q Expose photoresist through n-well mask
q Strip off exposed photoresist
p substrate
SiO2
Photoresist

33. 0: Introduction Slide 33
CMOS VLSI Design
Etch
q Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
q Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist

34. 0: Introduction Slide 34
CMOS VLSI Design
Strip Photoresist
q Strip off remaining photoresist
– Use mixture of acids called piranah etch
q Necessary so resist doesn’t melt in next step
p substrate
SiO2

35. 0: Introduction Slide 35
CMOS VLSI Design
n-well
q n-well is formed with diffusion or ion implantation
q Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
q Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
n well
SiO2

36. 0: Introduction Slide 36
CMOS VLSI Design
Strip Oxide
q Strip off the remaining oxide using HF
q Back to bare wafer with n-well
q Subsequent steps involve similar series of steps
p substrate
n well

37. 0: Introduction Slide 37
CMOS VLSI Design
Polysilicon
q Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
q Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well

38. 0: Introduction Slide 38
CMOS VLSI Design
Polysilicon Patterning
q Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well

39. 0: Introduction Slide 39
CMOS VLSI Design
Self-Aligned Process
q Use oxide and masking to expose where n+ dopants
should be diffused or implanted
q N-diffusion forms nMOS source, drain, and n-well
contact
p substrate
n well

40. 0: Introduction Slide 40
CMOS VLSI Design
N-diffusion
q Pattern oxide and form n+ regions
q Self-aligned process where gate blocks diffusion
q Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substrate
n well
n+ Diffusion

41. 0: Introduction Slide 41
CMOS VLSI Design
N-diffusion cont.
q Historically dopants were diffused
q Usually ion implantation today
q But regions are still called diffusion
n well
p substrate
n+
n+ n+

42. 0: Introduction Slide 42
CMOS VLSI Design
N-diffusion cont.
q Strip off oxide to complete patterning step
n well
p substrate
n+
n+ n+

43. 0: Introduction Slide 43
CMOS VLSI Design
P-Diffusion
q Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p substrate
n well
n+
n+ n+
p+
p+
p+

44. 0: Introduction Slide 44
CMOS VLSI Design
Contacts
q Now we need to wire together the devices
q Cover chip with thick field oxide
q Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Contact

45. 0: Introduction Slide 45
CMOS VLSI Design
Metalization
q Sputter on aluminum over whole wafer
q Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal

46. 0: Introduction Slide 46
CMOS VLSI Design
Layout
q Chips are specified with set of masks
q Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
q Feature size f = distance between source and drain
– Set by minimum width of polysilicon
q Feature size improves 30% every 3 years or so
q Normalize for feature size when describing design
rules
q Express rules in terms of λ = f/2
– E.g. λ = 0.3 µm in 0.6 µm process

47. 0: Introduction Slide 47
CMOS VLSI Design
Simplified Design Rules
q Conservative rules to get you started

48. 0: Introduction Slide 48
CMOS VLSI Design
Inverter Layout
q Transistor dimensions specified as Width / Length
– Minimum size is 4λ / 2λ, sometimes called 1 unit
– In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm
long

49. 0: Introduction Slide 49
CMOS VLSI Design
Summary
q MOS Transistors are stack of gate, oxide, silicon
q Can be viewed as electrically controlled switches
q Build logic gates out of switches
q Draw masks to specify layout of transistors
q Now you know everything necessary to start
designing schematics and layout for a simple chip!