24. DFF
always @(posedge clk)
always @(posedge clk)
begin
begin
if (CE)
if (S)
Q = D;
Q = 1'b1;
end
else
Q = D;
end
endmodule
25. 4-bit unsigned Up counter with
asynchronous clear
module counter (C, CLR, Q);
input C, CLR;
output [3:0] Q;
reg [3:0] Q;
always @(posedge C or posedge CLR)
begin
if (CLR)
Q = 4'b0000;
else
Q = Q + 1'b1;
end
endmodule
26. 4-bit unsigned Down counter
with synchronous set
module counter (C, S, Q);
input C, S;
output [3:0] Q;
reg [3:0] Q;
always @(posedge C)
begin
if (S)
Q = 4'b1111;
else
Q = Q - 1'b1;
end
endmodule
27. 4-bit unsigned Up Counter with
asynchronous load
module counter (C, ALOAD, D, Q);
input C, ALOAD;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(posedge C or posedge ALOAD)
begin
if (ALOAD)
Q = D;
else
Q = Q + 1'b1;
end
endmodule
28. 4-bit unsigned Up counter with asyn-
chronous clear and clock enable
module counter (C, CLR, CE, Q);
input C, CLR, CE;
output [3:0] Q;
reg [3:0] Q;
always @(posedge C or posedge CLR)
begin
if (CLR)
Q = 4'b0000;
else
if (CE)
Q = Q + 1'b1;
end
endmodule
29. 8-bit shift-left register
serial in serial out.
module shift (C, SI, SO);
input C,SI;
output SO;
reg [7:0] Q;
always @(posedge C)
begin
Q <= Q << 1; // Q <= {Q[6:1], SI};
Q[0] <= SI;
end
assign SO = Q[7];
endmodule
