microprocessors

1. UNIT – IV
PERIPHERAL INTERFACING
Study of Architecture and programming (interfacing with
8085) of ICs:
(1) 8255 - PPI
(2) 8259 - PIC
(3) 8251 - USART
(4) 8279 - Key board Display controller
(5) 8253 - Timer/ Counter and
(6) A/D and D/A converter

2. Need for an Interfacing
 reading data from an external device
 writing data into another external device

3. -The task of connecting an IO device to a computer
system is greatly achieved by the use of Standard IC’s
known as IO interface circuits, IO Module, IO System,
Peripheral interface adapters, and the like.
-Allows IO devices of widely different characteristics to
be connected to a standard system bus with a minimum of
special-purpose hardware or software.
- programmable.
- intended to act as serial (slow devices) or parallel ports
(multi-bit, bidirectional data path – high speed).

4. Intel 8255 Programmable Peripheral Interface (PPI)
designed for interfacing IO devices with Intel 8085 &
other small µPs.
 40 pin package.
 8 pins connect the 8255 to an 8 bit bidirectional CPU
data bus.
 24 pins are attached to several IO devices and are
programmable in that the functions they perform are
determined by a control word issued by a CPU instruction
and stored internally in the 8255.
 CW can specify a variety of operating modes. (Sync or
Async).

5. 8255 Programmable Peripheral Interface Circuit
Read/Write
Control
Logic
Data bus
READ
Control
Register
CR
Data buffer
WRITE
T
o
C
P
U
Address
lines
A0
A1
T
o
I
O
D
e
v
i
c
e
s
8
–
bit
internal
data
bus
8
8
8
8
8
4
4
A
B
CB
CA
8255
CS

6. Description
 24 pins on the I/O side of the 8255 are divided into
8-bit groups designated A,B and C, each of which can
act as an independent IO port.
 Port C can be further divided into two 4-bit groups
CA and CB and used as status or handshaking lines in
conjunction with A and B ports.
 Two address lines A0 & A1 select one of the three
ports A, B and C for use in an IO operation. (three
addresses).
 The fourth address is used in conjunction with an
output instruction of the form OUT CW to store an 8-
bit user-specified CW in 8255.

7. Port Selection
S.No. CS A1 A0 Port
1 0 0 0 A
2 0 0 1 B
3 0 1 0 C
4 0 1 1 Control Register
5 1 X X 8255 is not selected

8. Control Word
D7 D6 D5 D4 D3 D2 D1 D0
Group B
Port C (Lower –> PC3-PC0)
1= Input ; 0= Output
Port B
1= Input ; 0= Output
Mode Selection
0= Mode 0 ; 1= Mode 1
Group A
Port C (Upper –> PC7-PC4)
1= Input ; 0= Output
Port A
1= Input ; 0= Output
Mode Selection
00= Mode 0 ; 01= Mode 1
1X= Mode 2
0 – BSR Mode
1 – I/O Mode

9. Continued . . .
Functions of CW:
1) It specifies whether A, B and C ports are to act
as input, as output or, in the case of A and B
only, as bidirectional IO ports.
2) It programs certain C lines to generate
handshaking and interrupt signals automatically
in response to actions by an IO device.

10. Modes of Operation
 I/O Mode
 Mode 0-Simple IO Mode
 Mode 1- Handshake Mode
 Mode 2- Bi-directional Mode
Bit Set/Reset Mode

11. To communicate with peripherals through 8255, three
steps are necessary
1) Determine the addresses of the ports A, B and C and
of the control register according to the chip select
logic and address lines A1 and A0.
2) Write a control word in the control register.
3) Write I/O instructions to communicate with
peripherals through ports A, B and C.

12. Mode – 0 : Simple I/O Mode
• Ports A and B are used as two simple 8-bit I/O
ports and Port C as two 4-bit ports.
• Each port can be programmed to function as
simply an input port (or) an output port
• The input/output features in Mode -0 are as
follows,
1) Outputs are latched.
2) Inputs are not latched.
3) Ports do not have handshake or interrupt
capability.

13.  Port A (or) Port B can be set for input (or) output
operation.
 The bits from port C are used as control signals (used for
handshaking).
 The features are,
(1) Two ports (A and B) function as 8-bit I/O ports.
(configured either as input or output ports)
(2) Each port uses three lines from port C as
handshake signals and the remaining signals can be used
for simple I/O functions.
(3) Input and Output data are latched.
(4) Interrupt logic is supported.
Mode – 1 : Handshake Mode

14. Mode-1 Input Control Signals
 STBbar(Strobe)- generated by a peripheral
device to indicate that it has transmitted a byte of
data.
 IBF (Input Buffer Full)- is an acknowledgement
by the 8255 to indicate that the input latch has
received the data byte.
 INTR- used to interrupt the CPU when an input
device is requesting service.
 INTE (Interrupt Enable)- internal flip flop used
to enable (or) disable the generation of the INTR
signal.

15. • Mode-1 Output Control Signals
OBFbar (Output Buffer Full)- is an O/P signal
that goes low when the MPU writes data into the
output latch.
 ACKbar – input signal from a device that must
output a low when the device receives the data
from 8255 ports.
 INTR
 INTE (Interrupt Enable)

16.  Port A is used as a bi-directional port with simultaneous
input and output capability.
 Port C are used for handshake. (Handshaking signals are
used to transfer data between devices whose data transfer
speeds are not same.
Mode – 2 Bi-directional Mode

17.  makes use of only port C.
 any bit of this port can be set (or) reset.
Bit Set/Reset Mode
Control word format in BSR Mode
0 X X X Bit Select S/R
Set=1
Reset=0
BSR Mode
Not used, generally set=0
000 = Bit 0
001 = Bit 1
010 = Bit 2
011 = Bit 3
100 = Bit 4
101 = Bit 5
110 = Bit 6
111 = Bit 7
D6
D7 D0
D5 D4 D3 D2 D1

18. Write initialization instructions for the 8255A to set up—
(i) Port A as I/P port in mode 0.
(ii) Port B as O/P port in mode 1.
(iii) Port C upper as an O/P in mode 0.
Assume address of control word register as 83H.
D7 D6 D5 D4 D3 D2 D1 D0
1
Determination of Control Word
1 0 0
0 0 1 x
0
1 94H
95H
MVI A, #94H
OUT 83H
MVI A, #95H
OUT 83H
or

19. Thank Q