Mod-2 M&M.pptx

UNIT – III
MICROPROCESSOR
PERIPHERAL
INTERFACING

 The varieties of support IC chips for the
peripheral interfacing of the 8086
microprocessor are
1. Programmable Peripheral Interface 8255
2. Keyboard and Display Controller 8279
3. Programmable Interval Timer 8253/8254

PROGRAMMABLE
PERIPHERAL
INTERFACE
(PPI) 8255

PPI – 8255 Introduction
8255 is a widely used programmable, parallel I/O
device
Can be programmed to transfer data under various
conditions, from simple I/O to interrupt I/O
Has 24 I/O pins that can be grouped in two 8 bit
parallel ports: A and B, eight bits as portC.
The 8 bits of port C can be used as individual bits or
be grouped in two 4-bit ports: Cupper (CU) and Clower
(CL)

RD (active low):
Read signal enables the read operation. When this signalis
low, the MPU reads data from a selected I/O port of the
8255
WR (active low):
Write control signal enables the write operation. When this
signal is low, the MPU writes into a selected I/O port or the
control register
RESET (active high):
This signal clears the control register and sets all ports in
the input mode.
CS,A0 andA1:
Device select signals: chip select is connected to a decoded
address and A0 and A1 are generally connected to MPU
address lines respectively

 The CS signal is the master chip select &A1 andA0
specify one of the I/O ports
CS
0
A1
0
A0
0
Selected
Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 X X 8255 is not selected

 It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group Bcontrols
4. Port A, B and C
 Data bus buffer: This is a tristate bidirectional buffer used
to interface the 8255 to system data bus. Data is
transmitted or received by the buffer on execution of input
or output instruction by the CPU.
 Read/Write control logic: This unit accepts control
signals ( RD , WR ) and also inputs from address bus and
issues commands to individual group of control blocks
(Group A, Group B)

 Group A and Group B controls : These blockreceive
control from the CPU and issues commands to their
respective ports.
 Group A – PAand PCU ( PC7–PC4)
 Group B – PB and PCL ( PC3 – PC0)
 Control word register can only be written into & no read
operation of the CW register is allowed.

PortA:
This has an 8 bit latched/buffered O/P and 8 bit input latch. It
can be programmed in 3 modes – mode 0, mode 1 & mode 2.
Port B:
This has an 8 bit latched / buffered O/P and 8 bit input latch. It
can be programmed in mode 0 & mode1.
Port C:
This has an 8 bit latched input buffer and 8 bit output
latched/buffer. This port can be divided into two 4 bit ports and
can be used as control signals for port A and port B. It can be
programmed in mode 0.

Modes of Operation of 8255
1. Bit Set/Reset (BSR) mode is used to set
or reset the bits in port C
2. I/O mode
Mode 0 – simple I/O
Mode 1 – I/O with handshake
Mode 2 – bidirectional I/O data transfer

D2 D1 D0
D7 D6 D5 D4 D3
0/1
Modes of 8255
I/O Mode
BSR Mode
(Bit set/Reset)
For Port C
No effect on
I/O mode
Mode 0
Simple I/O
For ports
A,B and C
Mode 1
Handshake I/O for
ports A and/orB
Port C bits
are used for
handshake
Mode 2
Bidirectional
data bus for
portA
Port B either
in Mode 0 or 1
Port C bits are
used for
handshake

BSR (Bit Set/Reset) Mode
 In this mode any of the 8-bits of port C can be set or reset
depending on D0 of the control word.
 The bit to be set or reset is selected by bit select flags D3,
D2 and D1 of the CWR as shown

Control Word Format in the BSR Mode

 The contents of the control register called the control word
specify an I/O function for each port.
 This register can be accessed to write a control word when A0
& A1 are at logic 1
 Control word register can only be written into and no read
operation of the CW register is allowed.
 Bit D7 of the control register specifies either the I/O function
or the Bit Set/Reset function.
 If Bit D7 =1, bits D6- D1 determine I/O functions in various
mode
 If bit D7 = 0, port C operates in the Bit Set/Reset(BSR)mode.
I/O (Input/output) Mode

Control Word Format in the I/O Mode

 In this mode, ports A and B are used as two simple 8bit
ports and port C as two 4 bit ports.
 Any port can be used as an input or output port
 Each port can be programmed to function as simply an input
port or an output port.
 The input/output features in Mode 0 are
◦ Output ports are latched
◦ Input ports are not latched
◦ 16 different Input/output configurations possible
Mode 0: Simple Input or Output

 The features of this mode are
◦ Two ports (Aand B) function as 8 bit I/O ports. They
can be configured either as input or output ports.
◦ Each port uses three lines from port C as handshake
signals. The remaining two lines of port C can be
used for simple I/O functions.
◦ Input and output data are latched
◦ Interrupt logic is supported.
Mode 1:
Input or Output with handshake

 Ports A and B are configured as inputports
 Port A uses the upper three signals PC3 ,PC4 and PC5 as
handshake signals
 Port B uses the lower three signals PC2, PC1 and PC0 as
handshake signals.
 STB (Strobe Input):
This active low signal is generated by a peripheral device to
indicate that it has transmitted a byte of data. The 8255A in
response to STB, generates IBF and INTR.
 IBF(Input Buffer Full):
This signal is an acknowledgement by the 8255A to indicate
that the input latch has received the data byte. This is reset
when the MPU reads the data
Mode 1: Input Control Signals

 INTR(Interrupt Request):
This is an output signal that may be used to interrupt the
MPU. This signal is generated if STB,IBF and
INTE(Internal flip-flop) are all at logic 1. This is resetby
the falling edge of the RD signal.
 INTE(Interrupt Enable):
This is an internal flip-flop used to enable or disable the
generation of the INTR signal. The two flip flops INTEA
and INTEB are set/reset using the BSR mode. The INTEA is
enabled or disabled through PC4 & INTEB is enabled or
disabled through PC2.
Mode 1: Input Control Signals

 OBF (Output buffer full ) – This status signal,whenever
falls to low, indicates that CPU has written data to the
specified output port. The OBF flip-flop will be set by a
rising edge of WR signal and reset by a low going edge at
the ACK input.
 ACK (Acknowledge input ) – ACK signal acts as an
acknowledgement to be given by an output device. ACK
signal, whenever low, informs the CPU that the data
transferred by the CPU to the output device through the port
is received by the output device.
Mode 1: Output Control Signals

 INTR ( Interrupt request ) – Thus an output signal that
can be used to interrupt the CPU when an output device
acknowledges the data received from the CPU. INTR is set
when ACK, OBF and INTE are 1. It is reset by a falling
edge on WR input.
 INTE(Interrupt Enable):The INTEA and INTEB flags are
controlled by the bit set-reset mode of PC6 and PC2
respectively.
 PC4, PC5 :These two lines can be set up either as input or
output.
Mode 1: Output Control Signals

 The Salient features of Mode 2 of 8255 are listed as
follows:
◦ The single 8-bit port in group A isavailable.
◦ The 8-bit port is bidirectional and additionally a 5-bit
control port is available.
◦ Three I/O lines are available at port C.( PC2 – PC0 )
◦ Inputs and outputs are both latched.
◦ The 5-bit control port C (PC3-PC7) is used for
generating / accepting handshake signals for the 8-bit
data transfer on portA.
Mode 2: Bidirectional Data Transfer

CONTROL WORDFORMATS
Mode 1 Input Mode 1 Output

Mode 2: Bidirectional Input/Output

KEYBOARD
AND
DISPLAY
CONTROLLER
8279

INTRODUCTION
 A programmable keyboard and display interfacingchip.
◦ Scans and encodes up to a 64-key keyboard.
◦ Controls up to a 16-digit numerical display.
Keyboard section has a built-in FIFO 8 character buffer.
 The display is controlled from an internal 16x8 RAM
that stores the coded display information.

PIN DESCRIPTION
 A0: Selects data (0) or control/status (1) for
reads and writes between MP and 8279.
 BD: Output that blanks the displays.
 CLK: Used internally for timing. Max. 3 MHz
 CN/ST: Control/strobe, connected to the
control key on the keyboard.
 CS: Chip select that enables programming,
reading the keyboard, etc.
 DB7-DB0: Consists of bidirectional pins that
connect to data bus on MP.

 IRQ: Interrupt request, becomes 1 when a key is
pressed, data is available.
 OUT A3-A0/B3-B0: Outputs that sends data tothe
most significant/least significant nibble of display.
 RD(WR): Connects to mp RD signal, reads
data/status registers.
 RESET: Connects to system RESET.
 RL7-RL0: Return lines are inputs used to sense
key depression in the keyboard matrix.
 Shift: Shift connects to Shift key on keyboard.
 SL3-SL0: Scan line outputs scan both the
keyboard and displays.
PIN DESCRIPTION

BLOCKS OF 8279
 I/O CONTROLAND DATABUFFERS
 It controls the flow of data to/from the 8279
 I/O section enabled only if CS is low
 CONTROLAND TIMING REGISTERAND TIMING
CONTROL
 It stores the keyboard and display modes and other operating
conditions programmed by CPU
 The registers are written with A0-1 andWR_=0
 SCAN COUNTER
 Two modes of scan 1.scan the key matrix 2.refresh the display
 The keyboard and display both are in the same mode at a time

BLOCK DIAGRAM OF 8279
 RETURN BUFFERS AND KEYBOARD
DEBOUNCE AND CONTROL
 This scans for a key closure row wise
 If a key closure is detected, the keyboard debounceunit
debounces the key entry
 FIFO/SENSOR RAM AND STATUS LOGIC
 In keyboard or Strobed input mode it acts a 8-byte first infirst
out (FIFO) RAM
 DISPLAYADDRESS REGISTERS AND DISPLAY
RAM
 The contents of the registers are automatically updatedby
8279 to accept the next data entry by CPU

MODES OF OPERATION OF 8279
 Modes of operation of 8279 are
1. Input (Keyboard) modes
 Scanned keyboard mode
 Scanned sensor matrix
 Strobed input
2. Output (Display) modes
 Display scan
 Display entry

Input (Keyboard) modes
 Scanned keyboard mode
 In this mode, it allows a key matrix to be interfaced
using either encoded or decoded scans
 Scanned sensor matrix
 In this mode, a sensor array can be interfaced with
8279 using either encoded or decoded scans
 Strobed input
 In this mode, if the control lines goes low, the data
on return lines is stored in the FIFO byte by byte

Output (Display) modes
 Display scan
 In this mode 8279 provides 8 or 16 character
multiplexed displays those can be organized as
dual 4-bit or single 8-bit display units
 Display entry
 8279 allows options for data entry on the displays.
The display data is entered for display either from
the right side or from the left side.

SAMPLE AND HOLD
CIRCUIT
&
MULTIPLEXER

SAMPLE AND HOLD CIRCUIT
&
MULTIPLEXER
 The multiplexer and S&H circuit are
normally used together in a data acquisition
system.
 The MP selects one of the i/p channels
through address lines.
 When S&H control signal is low (i.e. sample
signal) the S&H circuit tracks the analog i/p.
 When the S&H control signal is high (hold
signal) the analog i/p is latched

Interface with MP of MUX after S&H circuit

Interface with MP of S&H circuit after MUX

PROGRAMMABLE
INTERVAL
TIMER 8254
(8253)

 It is a programmable counter/timer chip designed
for use as an Intel microcomputer peripheral
 The 3 counters are 16-bit down counters
independent of each other, and can be easily read by
the CPU.
 All 3 counters are able to operate either in BCD or
in Hexadecimal mode.
 The counter can count either in binary or BCD.
 8254 is an upgraded version of 8253 and they are
pin-compatible
 All modes of operation are software programmable
INTRODUCTION

BLOCK DIAGRAM OF 8253/54
 Three counters (0, 1 & 2)
 Each counters has two i/p signals (CLK & GATE)
and one o/p signal (OUT)
 Data Bus buffer
 Read/Write control logic
 Control word Register
 Control word registers and counters are selected
using A1 andA0 A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control register

DATA BUS BUFFER
The 8-bit bidirectional data buffer interfaces internal circuit of 8254 to
microprocessor. Data is transmitted or received by the buffer upon the
execution of IN or OUT instruction.
READ/WRITE CONTROL LOGIC
It controls the reading and the writing of the counterregisters
The control section has five signals
1. RD_ (Read signal)
2. WR_ (Write signal)
3. CS_ (Chip Select signal)
4. Address lineA1
5. Address lineA0
CONTROL WORD REGISTER
This register is accessed when lines A1 and A0 are at logic 1. It is
used to write a command word which specifies the counter to be
used, its mode is either a Read or Write operation

INTERNAL REGISTER
OPERATION FOR
PROGRAMMING 8253/54
RD_ RW_ A0 A1 Function
1 0 0 0 Load Counter 0
COUNTER 0
0 1 0 0 Read Counter 0
COUNTER 1
COUNTER 2
MODE WORD or
1 0 1 1 Write Mode Word
CONTROL WORD 0 1 1 1 No-operation

Mode
8254 can operate in 6 different modes, and the gate of
a counter is used either to disable or enable counting

6 MODES OF 8253/54
1. MODE 0: Interrupt on Terminal Count
2. MODE 1: Hardware – Retriggerable One-Shot
3. MODE 2: Rate Generator
4. MODE 3: Square-Wave Generator
5. MODE 4: Software Triggered Strobe
6. MODE 5: Hardware Triggered Strobe

MODE 0 : Interrupt on Terminal Count
•In this mode, initially the OUT is low.
•Once the count is loaded in the register, the counter is
decremented every cycle and when the count reaches zero, the
OUT goes high. This can be used as an interrupt
•The OUT remains high until a new count or a command word
is loaded.

MODE 1 : Hardware - Retriggerable one-shot
•In this mode, the OUT is initially high
•When the Gate is triggered, the OUT goes low, and at the end
of the count, the OUT goes high again, thus generating a one-
shot pulse.

MODE 2 : Rate Generator
•This mode is used to generate a pulse equal to the clock period
at a given interval.
•When a count is loaded, the OUT stays high until the count
reaches 1, and then the OUT goes low for one clock period
•The count is reloaded automatically, and the pulse is generated
continuously. The count = 1 is illegal in this mode.

MODE 3 : Square wave generator
• In this mode, when a count is loaded, the OUT is high.
• The count is decremented by two at every clock cycle, and
when it reaches zero, the OUT goes low, and the count is
reloaded again.
• This is repeated continuously; thus a continuous square wave
with period equal to the period of the count is generated
• The frequency of the square wave is equal to the frequency of the clock divided by the count

MODE 4 : Software triggered strobe
•In this mode, the OUT is initially high; it goes low
for one clock period at the end of the count.
•The count must be reloaded for subsequent
outputs.

MODE 5 : Hardware triggered strobe
•This mode is similar to Mode 4, except that it is
triggered by the rising pulse at the gate
•Initially, the OUT is low, and when the Gate pulse
is triggered from low to high, the count begins.
•At the end of the count, the OUT goes low for one
clock period.

DIGITAL-TO-ANALOG CONVERTER
•DACs translate digital information into equivalent
analog voltage or current.
•The main constituents of the DAC are the decoder
network, an analog switch for each digital input, a
buffer amplifier and necessary control logic.
•Three cases
1. Case(i) n=m
2. Case(ii) n>m
3. Case(iii) n<m

MICROPROCESSOR INTERFACE TO DAC
•Case(i) n=m

•Case(i) n>m
26 February M.M.Arun Prasath.,Asst.

•Case(i) n<m

ANALOG
to
DIGITAL
CONVERTORS

ANALOG-TO-DIGITAL CONVERTER
•The ADC takes analog i/p and gives digital signal aso/p.
•The operation deals with the following signals
1. Input voltage – input analog voltage. i/p toADC
2. Start convert – command to start conversion. i/p toADC
3. End of conversion – information that conversion is
complete and the o/p can be read. o/p fromADC
4. Output enable – digital value of analog i/p derived from
conversion. o/p fromADC
A MP can be interfaced to ADC in any of the 3modes
1. Asynchronous mode
2. Synchronous mode
3. Interrupt mode

ADC CHIP CONFIGURATION
26 February 2014 M.M.Arun Prasath.,Asst.

MICROPROCESSOR INTERFACE TOADC
Asynchronous
mode

Asynchronous mode Flowchart

Synchronous
mode

Synchronous mode Flowchart

Interrupt
mode

Interrupt mode Flowchart

CRT TERMINAL
&
PRINTER
INTERFACE

MICROPROCESSOR INTERFACE TO CRT

through
SERIAL/PARALLEL CONVERTOR

through USART

INTERFACE OF PRINTER WITH
MICROPROCESSOR

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