schematic acer 80a

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Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
1 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Sonoma Dothan EAL50_1
LA2362 Schematic

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Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
2 52
Friday, March 11, 2005
2005/03/01 2006/03/01
BT
PCI BUS
SO-DIMM X 1
Dothan
GMCH-M
ATA100
Transformer
LPC BUS
Fan Control X1
RESERVED
& TV-OUT
uFCPGA CPU
IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)
KB910
VGA CONN.
3.3V 24.576MHz
VCORE
USB2.0
HA#(3..31)
Alviso Intel 915 PM/GM
JUSBP2
SST39VF080
PCI-E 16X
Clock Generator
HD#(0..63)
Compal confidential
DC IN
ICS
3.3V 33MHz
5V/3.3V/15V
USBPORT 0
Int.KBD
BANK 0, 1
USBPORT 1
DMI
CDROM
CHARGER
ICH6
3.3V 33MHz
USBPORT 2
ENE CB712
RTL 8110SBL
/ G 8100CL /
100
JUSBP1
USBPORT 3
CRT CONN.
System Bus
USBPORT 4
JUSBP3
609 BGA
X BUS
CardBus
Controller
USBPORT 5
Block Diagram
400 / 533MHz
2.5V 333MHz
VGA
Board
1.5V
100MHz
1257 FC-BGA
AC-LINK
48MHz / 480Mb
USBPORT 6
USBPORT 7
Touch Pad
& RJ45
MINI PCI
Memory
BUS(DDR)
Dual Channel
BATT IN/+2.5V
LED/B
Slot 0
1394
CONN.
HDD
RTL 250
AC97 CODEC
AMP &
Phone/ MIC
Jack 1.8V / 0.9V
1.5V/1.05V(+VCCP)
RESERVED
FIR
SIO
LPC47N217D
JUSBP1
SDIO
CONN.
BT+MDC
ATI VGA
PIO
RESERVED
SO-DIMM X 1
BANK 2, 3
Channel A
3.3V 33MHz
VIA6301
1394
SW LED BD
T/P
Internal GM
External PM

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B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
C
3 52
Friday, March 11, 2005
2005/03/01 2006/03/01
I2C / SMBUS ADDRESSING
External PCI Devices
IDSEL # PIRQ
REQ/GNT #
DEVICE
Cardreader
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
AD17
AD20
AD18
1
3
0
B
E
A
G,H
F
+3VALW
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
State
Signal
ON
+5VALW
+12VALW +3V
+2.5V
+1.25VS
+3VS
+5VS
+1.5VS
+CPU_CORE
+VCCP
ON ON
ON ON ON
ON ON
ON OFF
OFF
OFF
OFF OFF OFF
Power Managment table
CH
A
Ceramic Capacitor Spec
Guide:
1
SL
CODE
0
C0G
9
SJ
B
+-3%
CODE
Symbol F
+40,-20%
+-20%
4
3
G
+20,-10%
X
UK
5
E
B C F
Z
+-0.05PF
Y5V Y5P
CK
V
+-0.1PF
J
X5R
A
Z5U
BJ
+100,-0%
Y5U X7R
P
D
M
+-30%
C
NP0 SH
8 G
H
CJ
+30,-10%
Symbol
I
K Q
+80,-20%
+-5%
7
H
6
+-0.5PF +-1PF
Z5V
+-10%
+-0.25PF
J
Tolerance:
+-2%
N
D
Z5P
2
UJ
Temperature Characteristics:
QT-Build
ST-Build
Bringup-Build 0.1
SST-Build
PCB Rev Data
PT-Build
VERSION ISSUE DATE REMARK
SCHEMATICS VERSION LIST
0.0A First Release
VGA Thermal
ADM1032
SERIAL SENSOR
(CPU)
SMB_EC_CK2
SOURCE
PC87591L
INVERTER BATT
EEPROM
THERMAL
SODIMM CLK CHIP
SMBUS Control Table
ICH_SMBCLK
ICH_SMBDATA
ICH6-M
MINI PCI
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
PC87591L
(LM75)
LCD_DDCCLK
LCD_DDCDATA
Alviso
GM-GP
LCD
SENSOR
THERMAL
AD16 2
@ Depop
1@ EAL51
2@ EAL50
+1.8VS
+2.5VS
+5V
+12V
1@ EAL51 VALUE (DELETE SIO/1394)

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A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
4 52
Friday, March 11, 2005
2005/03/01 2006/03/01
ACIN
+3/5/12VALW
RSMRST#
ON/OFF#
EC_ON#
PWRBTN_OUT#
SYSON
+12/2.5/3/5V
SLP_S3/4/5#
SUSP#
+1.25/1.5/1.8/2.5/3/5VS
VR_ON#
+VCCP
CPU_VID
+CPU_CORE
SYSPOK
Vgate
CPU_RST#
PCIRST/PLTRST#
t<100 us
2<t<3 RTCCLK
t>0
7.856ms
t<110 ms
t<=10 ms
t=100 ms
t=109 ms
t<110 ms
32ms
8.5/2.44/3.792ms
438ms
3/5V 400us 2.5V(1.8ms)
364us
117ms
92.88ms
1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)
2.166ms
1.3ms PGD
5.6ms
726us
815.2us
99ms
1.036ms
61us

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D D
C C
B B
A A
ITP_TDI
ITP_TMS
ITP_TDO
ITP_TRST#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#5
ITP_DBRESET# ITP_TDO
H_RESET#
ITP_TMS
ITP_TDI
ITP_TRST#
ITP_TCK
ITP_DBRESET#
ITP_TCK
ITP_BPM#3
H_PWRGOOD
CLK_ITP_R
CLK_ITP_R#
CLK_ITP#
CLK_ITP
CLK_ITP_R
TEST1
H_RESET#
H_INTR
H_D#27
H_D#19
H_D#16
H_D#8
CLK_CPU_BCLK
H_REQ#4
H_REQ#2
H_A#25
H_D#30
H_D#26
H_D#14
H_D#12
H_A#20
H_FERR#
H_D#56
H_D#5
H_THERMDC
H_RS#2
H_RS#0
H_ADS#
H_A#29
H_A#26
H_A#7
H_A20M#
H_D#41
H_D#29
H_D#24
H_D#21
H_ADSTB#0
H_A#14
H_HIT#
H_BPRI#
H_A#22
H_A#21
H_A#5
H_A#3
H_D#46
H_D#42
H_D#39
ITP_BPM#0
H_BR0#
H_A#28
H_A#23
H_A#15
H_A#13
H_D#58
H_D#37
H_D#0
CLK_CPU_BCLK#
H_A#24
H_A#11
H_A#8
H_INIT#
H_DSTBP#1
H_D#60
H_DRDY#
H_REQ#0
H_A#30
H_A#10
H_DSTBP#3
H_D#57
H_D#48
H_D#47
H_D#28
H_D#22
H_RS#1
H_ADSTB#1
H_A#31
H_A#27
H_A#9
H_NMI
H_D#20
H_D#18
H_D#13
H_DEFER#
H_A#18
H_DSTBN#0
H_D#52
H_D#51
H_D#50
H_D#45
H_D#15
H_D#11
H_D#3
ITP_BPM#3
H_IGNNE#
H_DSTBP#2
H_DSTBN#1
H_D#33
H_D#23
H_D#7
H_D#1
H_REQ#3
H_DSTBP#0
H_D#63
H_D#59
H_D#49
H_D#32
H_D#17
ITP_BPM#2
H_TRDY#
H_HITM#
H_REQ#1
H_D#54
H_D#44
H_D#43
H_D#9
H_D#4
ITP_BPM#1
H_A#19
H_D#53
H_D#40
H_D#36
H_D#2
H_IERR#
CPU_CK_ITP#
CPU_CK_ITP
H_A#12
H_A#6
H_DSTBN#2
H_D#62
H_D#61
H_D#35
H_D#34
H_D#31
H_D#25
H_D#10
H_D#6
H_THERMDA
H_RESET#
H_DSTBN#3
H_D#55
H_D#38
H_LOCK#
H_BNR#
H_A#17
H_A#16
H_A#4
H_DPRSLP#
TEST1
TEST2
ITP_TCK
ITP_TRST#
ITP_TDO
H_CPUSLP#
ITP_TMS
ITP_TDI
ITP_BPM#5
ITP_BPM#4
H_PROCHOT#
H_SMI#
H_STPCLK#
ITP_DBRESET#
H_DPSLP#
H_DBSY#
TEST2
H_PROCHOT#
ITP_BPM#5
ITP_BPM#4
H_A#[3..31]
<8>
H_REQ#[0..4]
<8>
H_ADSTB#0
<8>
H_ADSTB#1
<8>
CLK_ITP
<18>
CLK_ITP#
<18>
CLK_CPU_BCLK
<18>
CLK_CPU_BCLK#
<18>
H_ADS#
<8>
H_BNR#
<8>
H_BR0#
<8>
H_BPRI#
<8>
H_DEFER#
<8>
H_DRDY#
<8>
H_HIT#
<8>
H_HITM#
<8>
H_LOCK#
<8>
H_RESET#
<8>
H_RS#[0..2]
<8>
H_TRDY#
<8>
H_DPSLP#
<20>
H_DPRSLP#
<20>
H_CPUSLP#
<8,20>
H_DBSY#
<8>
H_DPWR#
<8>
H_PWRGOOD
<20>
H_THERMDA
<34>
H_THERMDC
<34>
H_THERMTRIP#
<8,20>
H_A20M# <20>
H_FERR# <20>
H_IGNNE# <20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>
H_STPCLK# <20>
H_SMI# <20>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_DSTBN#[0..3] <8>
H_DSTBP#[0..3] <8>
H_D#[0..63] <8>
PROCHOT# <32>
+VCCP
+VCCP
+VCCP
+3V
+VCCP
+VCCP
+VCCP
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
5 52
Friday, March 11, 2005
2005/03/01 2006/03/01
This shall place near CPU
Add pullups for PWRGOOD and THERMTRIP per INTEL
Place near JITP
Check ITP connector.
Place near JITP 0.5"
Test pad as closed as posible
39.4
T7
PAD
T12
PAD
R100
680_0402_5%
1 2
R110 0_0402_5%
@
1 2
T5 PAD
R464
1K_0402_5%
@
1 2
R87
22.6_0402_1%
1 2
T14
PAD
T15
PAD
R90
54.9_0603_1%
1 2
R79
150_0402_5%
1 2
T17
PAD
R109 0_0402_5%
@ 1 2
R530
1K_0402_5%
@
1 2
R132
1K_0402_5%
1
2
R76
54.9_0603_1%
1 2
T9
PAD
C359
0.1U_0402_10V6K
1
2
R458
200_0402_5%
1 2
T16
PAD
R124
56_0402_5%
1
2
C
B
E
Q6
2SC2411K_SC59
1
2
3
T39 PAD
T13
PAD
T8
PAD
R78
56_0402_5%
1 2
T11
PAD
R745 56_0402_5%
1 2
T4
PAD
R479
37.4_0402_1%
1 2
R112 0_0402_5%
@
1 2
T10
PAD
ADDR GROUP
CONTROL GROUP
HOST CLK
MISC
DATA GROUP
THERMAL
DIODE
LEGACY CPU
Dothan
JCPU1A
TYCO_1612365-1_Dothan
A3#
P4
A4#
U4
A5#
V3
A6#
R3
A7#
V2
A8#
W1
A9#
T4
A10#
W2
A11#
Y4
A12#
Y1
A13#
U1
A14#
AA3
A15#
Y3
A16#
AA2
A17#
AF4
A18#
AC4
A19#
AC7
A20#
AC3
A21#
AD3
A22#
AE4
A23#
AD2
A24#
AB4
A25#
AC6
A26#
AD5
A27#
AE2
A28#
AD6
A29#
AF3
A30#
AE1
A31#
AF1
REQ0#
R2
REQ1#
P3
REQ2#
T2
REQ3#
P1
REQ4#
T1
ADSTB0#
U3
ADSTB1#
AE5
BCLK0
B15
BCLK1
B14
ITP_CLK0
A16
ITP_CLK1
A15
ADS#
N2
BNR#
L1
BPRI#
J3
BR0#
N4
DEFER#
L4
DRDY#
H2
HIT#
K3
HITM#
K4
IERR#
A4
LOCK#
J2
RESET#
B11
RS0#
H1
RS1#
K1
RS2#
L2
TRDY#
M3
BPM0#
C8
BPM1#
B8
BPM2#
A9
BPM3#
C9
DBR#
A7
DBSY#
M2
DPSLP#
B7
DPWR#
C19
PRDY#
A10
PREQ#
B10
PROCHOT#
B17
PWRGOOD
E4
SLP#
A6
TCK
A13
TDI
C12
TDO
A12
TEST1
C5
TEST2
F23
TMS
C11
TRST#
B13
THERMDA
B18
THERMDC
A18
THERMTRIP#
C17
D0# A19
D1# A25
D2# A22
D3# B21
D4#
A24
D5#
B26
D6#
A21
D7#
B20
D8#
C20
D9#
B24
D10#
D24
D11#
E24
D12#
C26
D13#
B23
D14#
E23
D15#
C25
D16#
H23
D17#
G25
D18# L23
D19# M26
D20# H24
D21# F25
D22# G24
D23# J23
D24# M23
D25# J25
D26# L26
D27# N24
D28# M25
D29# H26
D30# N25
D31# K25
D32# Y26
D33# AA24
D34# T25
D35# U23
D36# V23
D37# R24
D38# R26
D39# R23
D40# AA23
D41# U26
D42# V24
D43# U25
D44# V26
D45# Y23
D46#
AA26
D47#
Y25
D48#
AB25
D49#
AC23
D50#
AB24
D51#
AC20
D52#
AC22
D53#
AC25
D54#
AD23
D55#
AE22
D56#
AF23
D57#
AD24
D58#
AF20
D59#
AE21
D60#
AD21
D61#
AF25
D62#
AF22
D63#
AF26
DINV0#
D25
DINV1#
J26
DINV2#
T24
DINV3#
AD20
DSTBN0#
C23
DSTBN1#
K24
DSTBN2#
W25
DSTBN3#
AE24
DSTBP0#
C22
DSTBP1#
L24
DSTBP2#
W24
DSTBP3#
AE25
A20M#
C2
FERR#
D3
IGNNE#
A3
INIT#
B5
LINT0
D1
LINT1
D4
STPCLK#
C6
SMI#
B4
DPRSTP#
G1
R106
27.4_0402_1%
1 2
T19
PAD
R111 0_0402_5%
@ 1 2
R123
56_0402_5%
1
2
R85
150_0402_5%
1 2
T6
PAD
R74
22.6_0402_1%
1 2

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5
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4
3
3
2
2
1
1
D D
C C
B B
A A
COMP0
COMP3
COMP1
COMP2
H_VID0
H_VID5
H_VID3
H_VID4
H_VID2
H_VID1
H_VID1
H_VID0
H_VID2
H_VID5
VSSSENSE
H_VID3
H_VID4
VCCSENSE
H_PSI#
CPU_BSEL0
CPU_BSEL1
VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>
PSI#
<45>
CPU_BSEL0
<18>
CPU_BSEL1
<18>
+VCCP
+CPU_CORE
+VCCA_PROC
+VCCP
+V_CPU_GTLREF
+V_CPU_GTLREF
+1.5VS
+VCCP
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
6 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.
R_B
R_A
For test only ,Cmos output
CPU Voltage ID
SHORT
OPEN OPEN OPEN OPEN OPEN OPEN
Layout close CPU
Layout Note:
500 mil max length
20 mils
20 mils
5 mils
5 mils
R426
0_0402_5%
@
1
2
T31 PAD
T29 PAD
R427
0_0402_5%
@
1
2
R436 0_0402_5%
1
2
R411
10K_0402_5%
@
1
2
R156
27.4_0402_1%
1
2
R424
0_0402_5%
@
1
2
R423
0_0402_5%
@
1
2
T2 PAD
Dothan
POWER, GROUND
JCPU1C
TYCO_1612365-1_Dothan
VCC
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
VCC
AA5
VCC
AA7
VCC
AA9
VCC
AA11
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA19
VCC
AA21
VCC
AB6
VCC
AB8
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB16
VCC
AB18
VCC
AB20
VCC
AB22
VCC
AC9
VCC
AC11
VCC
AC13
VCC
AC15
VCC
AC17
VCC
AC19
VCC
AD8
VCC
AD10
VCC
AD12
VCC
AD14
VCC
AD16
VCC
AD18
VCC
AE9
VCC
AE11
VCC
AE13
VCC
AE15
VCC
AE17
VCC
AE19
VCC
AF8
VCC
AF10
VCC
AF12
VCC
AF14
VCC
AF16
VCC
AF18
VSS
M4
VSS
M5
VSS
M21
VSS
M24
VSS
N3
VSS
N6
VSS
N22
VSS
N23
VSS
N26
VSS
P2
VSS
P5
VSS
P21
VSS
P24
VSS
R1
VSS
R4
VSS
R6
VSS
R22
VSS
R25
VSS
T3
VSS
T5
VSS
T21
VSS
T23
VSS T26
VSS U2
VSS U6
VSS U22
VSS
U24
VSS
V1
VSS
V4
VSS
V5
VSS
V21
VSS
V25
VSS
W3
VSS
W6
VSS
W22
VSS
W23
VSS
W26
VSS
Y2
VSS
Y5
VSS
Y21
VSS Y24
VSS AA1
VSS AA4
VSS AA6
VSS AA8
VSS AA10
VSS AA12
VSS AA14
VSS AA16
VSS AA18
VSS AA20
VSS AA22
VSS AA25
VSS AB3
VSS AB5
VSS AB7
VSS AB9
VSS AB11
VSS AB13
VSS AB15
VSS AB17
VSS AB19
VSS AB21
VSS AB23
VSS AB26
VSS AC2
VSS AC5
VSS AC8
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC21
VSS
AC24
VSS
AD1
VSS
AD4
VSS
AD7
VSS
AD9
VSS
AD11
VSS
AD13
VSS
AD15
VSS
AD17
VSS
AD19
VSS
AD22
VSS
AD25
VSS
AE3
VSS
AE6
VSS
AE8
VSS
AE10
VSS
AE12
VSS
AE14
VSS
AE16
VSS
AE18
VSS
AE20
VSS
AE23
VSS
AE26
VSS
AF2
VSS
AF5
VSS
AF9
VSS
AF11
VSS
AF13
VSS
AF15
VSS
AF17
VSS
AF19
VSS
AF21
VSS
AF24
R410
10K_0402_5%
@
1
2
R435 0_0402_5%
1
2
R437 0_0402_5%
1
2
C516
0.01U_0402_16V7K
1
2
R155
1K_0402_1%
1
2
R425
0_0402_5%
@
1
2
R434 0_0402_5%
1
2
T3 PAD
R409
10K_0402_5%
@
1
2
R417
54.9_0402_1%
1
2
R157
54.9_0402_1%
1
2
T20 PAD
R470
54.9_0402_1%
@
1 2
C150
10U_1206_6.3V6M
1
2
R416
27.4_0402_1%
1
2
R408
10K_0402_5%
@
1
2
J2
PAD-OPEN 2x2m
@
2 1
R412
10K_0402_5%
@
1
2
R465
54.9_0402_1%
@
1 2
Dothan
POWER,
GROUNG,
RESERVED
SIGNALS
AND
NC
JCPU1B
TYCO_1612365-1_Dothan
PSI#
E1
GTLREF
AD26
VCCQ0
P23
VCCQ1
W4
VCCSENSE
AE7
VSSSENSE
AF6
BSEL0
C16
BSEL1
C14
VCCA0
F26
VCCA1
B1
VCCA2
N1
VCCA3
AC26
VCCP
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCC
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VID0
E2
VID1
F2
VID2
F3
VID3
G3
VID4
G4
VID5
H4
COMP0
P25
COMP1
P26
COMP2
AB2
COMP3
AB1
RSVD
AF7
RSVD
B2
RSVD
C3
RSVD
E26
VSS A2
VSS A5
VSS A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS C1
VSS C4
VSS C7
VSS C10
VSS C13
VSS C15
VSS C18
VSS C21
VSS C24
VSS D2
VSS D5
VSS D7
VSS D9
VSS D11
VSS D13
VSS D15
VSS D17
VSS D19
VSS D21
VSS D23
VSS D26
VSS E3
VSS E6
VSS E8
VSS E10
VSS E12
VSS E14
VSS E16
VSS
E18
VSS
E20
VSS
E22
VSS
E25
VSS
F1
VSS
F4
VSS
F5
VSS
F7
VSS
F9
VSS
F11
VSS
F13
VSS
F15
VSS
F17
VSS
F19
VSS
F21
VSS
F24
VSS
G2
VSS
G6
VSS
G22
VSS
G23
VSS
G26
VSS
H3
VSS
H5
VSS
H21
VSS
H25
VSS
J1
VSS
J4
VSS
J6
VSS
J22
VSS
J24
VSS
K2
VSS
K5
VSS
K21
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L22
VSS
L25
VSS
M1
RSVD
AC1
R413
10K_0402_5%
@
1
2
R438 0_0402_5%
1
2
R422
0_0402_5%
@
1
2
R433 0_0402_5%
1
2
R153
2K_0402_1%
1
2

7. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
7 52
Friday, March 11, 2005
2005/03/01 2006/03/01
10uF 1206 X5R -> 85 degree
X7R
High Frequence Decoupling
Near VCORE regulator.
ESR <= 3m ohm
Capacitor > 880 uF
C483
10U_0805_6.3V6M
1
2
+
C358
330U_D2E_2.5VM_R9
1
2
C424
0.1U_0402_10V6K
1
2
C469
10U_0805_6.3V6M
1
2
C109
10U_0805_6.3V6M
1
2
C383
10U_0805_6.3V6M
1
2
C481
10U_0805_6.3V6M
1
2
C105
10U_0805_6.3V6M
1
2
C441
0.1U_0402_10V6K
1
2
C450
0.1U_0402_10V6K
1
2
C669
0.1U_0402_10V6K
1
2
C482
10U_0805_6.3V6M
1
2
C100
10U_0805_6.3V6M
1
2
C113
10U_0805_6.3V6M
1
2
C415
10U_0805_6.3V6M
1
2
C498
0.1U_0402_10V6K
1
2
C91
10U_0805_6.3V6M
1
2
C668
0.1U_0402_10V6K
1
2
C512
10U_0805_6.3V6M
1
2
C92
10U_0805_6.3V6M
1
2
C398
0.1U_0402_10V6K
1
2
C671
0.1U_0402_10V6K
1
2
+
C357
330U_D2E_2.5VM_R9
@
1
2
C470
10U_0805_6.3V6M
1
2
C460
10U_0805_6.3V6M
1
2
C670
0.1U_0402_10V6K
1
2
C416
10U_0805_6.3V6M
1
2
+ C525
150U_D2_6.3VM
1
2
C430
10U_0805_6.3V6M
1
2
C480
10U_0805_6.3V6M
1
2
C664
0.1U_0402_10V6K
1
2
C504
0.1U_0402_10V6K
1
2
C673
0.1U_0402_10V6K
1
2
C507
10U_0805_6.3V6M
1
2
C446
10U_0805_6.3V6M
1
2
C672
0.1U_0402_10V6K
1
2
C667
0.1U_0402_10V6K
1
2
C503
0.1U_0402_10V6K
1
2
C518
10U_0805_6.3V6M
1
2
C421
10U_0805_6.3V6M
1
2
C104
10U_0805_6.3V6M
1
2
+
C377
330U_D2E_2.5VM_R9
1
2
C459
10U_0805_6.3V6M
1
2
C499
0.1U_0402_10V6K
1
2
C108
10U_0805_6.3V6M
1
2
C121
10U_0805_6.3V6M
1
2
+
C378
330U_D2E_2.5VM_R9
1
2
C114
10U_0805_6.3V6M
1
2
C422
10U_0805_6.3V6M
1
2
C463
0.1U_0402_10V6K
1
2
C500
0.1U_0402_10V6K
1
2
C431
10U_0805_6.3V6M
1
2
C522
10U_0805_6.3V6M
1
2
C120
10U_0805_6.3V6M
1
2
C665
0.1U_0402_10V6K
1
2
C99
10U_0805_6.3V6M
1
2
C666
0.1U_0402_10V6K
1
2
C442
10U_0805_6.3V6M
1
2
C502
10U_0805_6.3V6M
1
2
C445
10U_0805_6.3V6M
1
2

8. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_SWNG1
PM_EXTTS#0
PM_EXTTS#1
PLTRST_R#
H_ADSTB#1
H_R_CPUSLP#
H_RS#2
H_RS#0
H_RS#1
H_YSCOMP
H_YRCOMP
H_SWNG0
H_SWNG1
H_SWNG0
PM_EXTTS#0
PM_EXTTS#1
MCH_CLKSEL0
CFG6
CFG5
CFG7
CFG12
CFG13
CFG19
CFG16
CFG18
MCH_CLKSEL1
DDR_SCS#3
DDR_SCS#2
DDR_SCS#0
DDR_SCS#1
DDR_CKE3
DDR_CKE1
DDR_CKE2
DDR_CKE0
DDR_CLK0#
DDR_CLK1#
DDR_CLK3#
DDR_CLK4#
DDR_CLK0
DDR_CLK1
DDR_CLK3
DDR_CLK4
DMI_RXP1
DMI_RXP0
DMI_RXN0
DMI_RXN1
DMI_TXP0
DMI_TXP1
DMI_TXN0
DMI_TXN1
SMRCOMPP
SMRCOMPN
H_CPUSLP# H_R_CPUSLP#
CFG0
CFG9
DMI_RXP3
DMI_RXP2
DMI_RXN2
DMI_RXN3
DMI_TXP2
DMI_TXP3
DMI_TXN2
DMI_TXN3
M_OCDOCMP0
M_OCDOCMP1
M_OCDOCMP0
M_OCDOCMP1
H_THERMTRIP#
H_DRDY#
H_A#25
H_A#24
H_A#23
H_REQ#3
H_DSTBP#0
H_REQ#2
H_A#12
H_A#5
H_A#4
H_BNR#
H_A#18
H_DSTBN#0
H_A#21
H_A#20
H_A#14
H_A#9
TP_H_EDRDY#
H_ADS#
H_A#29
H_REQ#0
H_A#31
H_A#30
H_BPRI#
H_RESET#
H_DBSY#
H_DSTBN#3
TP_H_PCREQ#
H_A#28
H_DSTBN#1
H_VREF
H_A#16
H_A#15
H_BR0#
H_A#17
H_A#13
H_LOCK#
H_A#8
H_ADSTB#0
H_DSTBP#1
H_REQ#4
H_A#26
H_A#19
H_A#6
H_TRDY#
H_A#11
H_A#7
H_DSTBN#2
H_REQ#1
H_A#22
H_A#10
H_DSTBP#3
H_DEFER#
H_DSTBP#2
H_A#27
H_A#3
H_XRCOMP
H_D#21
H_D#61
H_D#35
H_D#6
H_D#47
H_D#58
H_D#51
H_D#31
H_D#26
H_D#13
H_D#55
H_D#48
H_D#15
H_D#0
H_D#59
H_D#23
H_D#3
H_D#1
H_D#32
H_D#11
H_D#5
H_D#62
H_D#29
H_D#49
H_D#44
H_D#25
H_D#16
H_D#50
H_D#43
H_D#27
H_D#56
H_D#45
H_D#18
H_D#40
H_D#38
H_D#36
H_D#34
H_D#24
H_D#42
H_D#39
H_D#22
H_D#37
H_D#9
H_D#8
H_D#46
H_D#33
H_D#60
H_D#52
H_D#28
H_D#19
H_D#7
H_D#2
H_D#54
H_D#14
H_D#4
H_D#41
H_D#20
H_D#10
H_D#30
H_D#63
H_D#57
H_D#53
H_D#17
H_D#12
H_XSCOMP
CFG5
CFG7
CFG6
CFG0
CFG12
CFG13
CFG18
CFG19
CFG9
CFG16
H_HIT#
H_HITM#
H_A#[3..31]
<5>
H_REQ#[0..4]
<5>
H_ADSTB#0
<5>
H_ADSTB#1
<5>
CLK_MCH_BCLK#
<18>
CLK_MCH_BCLK
<18>
H_DSTBN#[0..3]
<5>
H_DSTBP#[0..3]
<5>
H_DINV#0
<5>
H_DINV#1
<5>
H_DINV#2
<5>
H_DINV#3
<5>
H_RESET#
<5>
H_ADS#
<5>
H_TRDY#
<5>
H_DPWR#
<5>
H_DRDY#
<5>
H_DEFER#
<5>
H_BR0#
<5>
H_BNR#
<5>
H_BPRI#
<5>
H_DBSY#
<5>
H_HITM#
<5>
H_HIT#
<5>
H_LOCK#
<5>
H_RS#[0..2]
<5>
H_CPUSLP#
<5,20>
H_D#[0..63] <5>
DMI_TXN0
<21>
DMI_TXN1
<21>
DMI_TXN2
<21>
DMI_TXN3
<21>
DMI_TXP0
<21>
DMI_TXP1
<21>
DMI_TXP2
<21>
DMI_TXP3
<21>
DMI_RXN0
<21>
DMI_RXN1
<21>
DMI_RXN2
<21>
DMI_RXN3
<21>
DMI_RXP0
<21>
DMI_RXP1
<21>
DMI_RXP2
<21>
DMI_RXP3
<21>
DDR_CLK0
<13>
DDR_CLK1
<13>
DDR_CLK3
<14>
DDR_CLK4
<14>
DDR_CLK0#
<13>
DDR_CLK1#
<13>
DDR_CLK3#
<14>
DDR_CLK4#
<14>
DDR_CKE0
<13>
DDR_CKE1
<13>
DDR_CKE2
<14>
DDR_CKE3
<14>
DDR_SCS#0
<13>
DDR_SCS#1
<13>
DDR_SCS#2
<14>
DDR_SCS#3
<14>
MCH_CLKSEL1 <18>
MCH_CLKSEL0 <18>
PM_BMBUSY# <21>
H_THERMTRIP# <5,20>
VGATE <18,21,45>
DREFCLK# <18>
DREFCLK <18>
SSC_DREFCLK <18>
SSC_DREFCLK# <18>
PLTRST_MCH# <19>
+VCCP
+VCCP
+VCCP
+VCCP
+2.5VS
+2.5V
+VCCP
+SDREF_DIMM
+VCCP
+2.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
8 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Layout Guide
will show these
signals routed
differentially.
Layout Guide will show
these signals routed
differentially.
Note:
"Do not install R for Dothan-A,
Install R97 for Dothan-B"
Layout Note:
Rote as short
as possible
CFG[17:3] have internal pull-up
CFG[19:18] have internal pull-down
CFG[2:0]
Refer to sheet 6 for FSB
frequency select
CFG19
(VTT Select)
*
*
CFG18
(VCC Select)
Low = DMI x 2
CFG7
High = DMI x 4
CFG5
Low = DT/Transportable CPU
High = Mobile CPU
CFG6
High = DDR-I
Low = DDR-II
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
Low = 1.05V (Default)
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
High = 1.2V
Low = 1.05V (Default)
High = 1.5V
High = Enabled
Low = Disabled
Low = Reverse Lane
CFG9
High = Normal Operation
*
*
*
*
*
*
10/20 mils
3.5 k reserve for choose
3.5 k reserve for choose
Alviso CFG[17:3] has internal pull-up
R387 10K_0402_5%
@
1
2
R35
2.2K_0402_5% @ 1
2
R367 10K_0402_5%
1
2
HOST
Alviso
U5A
ALVISO_BGA1257
HD0#
E4
HD1#
E1
HD2#
F4
HD3#
H7
HD4#
E2
HD5#
F1
HD6#
E3
HD7#
D3
HD8#
K7
HD9#
F2
HD10#
J7
HD11# J8
HD12# H6
HD13# F3
HD14# K8
HD15# H5
HD16# H1
HD17# H2
HD18# K5
HD19# K6
HD20# J4
HD21# G3
HD22# H3
HD23# J1
HD24# L5
HD25# K4
HD26# J5
HD27# P7
HD28# L7
HD29# J3
HD30# P5
HD31# L3
HD32# U7
HD33# V6
HD34# R6
HD35# R5
HD36# P3
HD37# T8
HD38# R7
HD39#
R8
HD40#
U8
HD41#
R4
HD42#
T4
HD43#
T5
HD44#
R1
HD45#
T3
HD46#
V8
HD47#
U6
HD48#
W6
HD49#
U3
HD50#
V5
HD51#
W8
HD52#
W7
HD53#
U2
HD54#
U1
HD55#
Y5
HD56#
Y2
HD57#
V4
HD58#
Y7
HD59#
W1
HD60#
W3
HD61#
Y3
HD62#
Y6
HD63#
W2
HA3#
G9
HA4#
C9
HA5#
E9
HA6#
B7
HA7#
A10
HA8#
F9
HA9#
D8
HA10#
B10
HA11#
E10
HA12#
G10
HA13#
D9
HA14#
E11
HA15#
F10
HA16#
G11
HA17#
G13
HA18#
C10
HA19#
C11
HA20#
D11
HA21#
C12
HA22#
B13
HA23#
A12
HA24#
F12
HA25#
G12
HA26#
E12
HA27#
C13
HA28#
B11
HA29#
D13
HA30#
A13
HA31#
F13
HREQ#0
A7
HREQ#1
D7
HREQ#2
B8
HREQ#3
C7
HREQ#4
A8
HADSTB#0
B9
HADSTB#1
E13
HPCREQ#
A11
HCLKN
AB1
HCLKP
AB2
HVREF
J11
HXRCOMP
C1
HXSCOMP
C2
HYRCOMP
T1
HYSCOMP
L1
HYSWING
P1
HXSWING
D1
HDSTBN#0
G4
HDSTBN#1
K1
HDSTBN#2
R3
HDSTBN#3
V3
HDSTBP#0
G5
HDSTBP#1
K2
HDSTBP#2
R2
HDSTBP#3
W4
HDINV#0
H8
HDINV#1
K3
HDINV#2
T7
HDINV#3
U5
HCPURST#
H10
HADS#
F8
HTRDY#
B5
HDPWR#
G6
HDRDY#
F7
HDEFER#
E6
HEDRDY#
F6
HHITM#
D6
HHIT#
D4
HLOCK#
B3
HBREQ0#
E7
HBNR#
A5
HBPRI#
D5
HDBSY#
C6
HCPUSLP#
G8
HRS0#
A4
HRS1#
C5
HRS2#
B4
R38
2.2K_0402_5% @ 1
2
T1 PAD
R57
56_0402_5%
@
1 2
DMI
DDR
MUXING
CFG/RSVD
PM
CLK
NC
U5B
ALVISO_BGA1257
DMIRXN0
AA31
DMIRXN1
AB35
DMIRXP0
Y31
DMIRXP1
AA35
DMITXN0
AA33
DMITXN1
AB37
DMITXP0
Y33
DMITXP1
AA37
SM_CK0
AM33
SM_CK1
AL1
SM_CK2
AE11
SM_CK3
AJ34
SM_CK4
AF6
SM_CK5
AC10
SM_CK0#
AN33
SM_CK1#
AK1
SM_CK2#
AE10
SM_CK3#
AJ33
SM_CK4#
AF5
SM_CK5#
AD10
SM_CKE0
AP21
SM_CKE1
AM21
SM_CKE2
AH21
SM_CKE3
AK21
SM_CS0#
AN16
SM_CS1#
AM14
SM_CS2#
AH15
SM_CS3#
AG16
SM_OCDCOMP0
AF22
SM_OCDCOMP1
AF16
SM_ODT0
AP14
SM_ODT1
AL15
SM_ODT2
AM11
SM_ODT3
AN10
SMRCOMPN
AK10
SMRCOMPP
AK11
SMVREF0
AF37
SMVREF1
AD1
SMXSLEWIN
AE27
SMXSLEWOUT
AE28
SMYSLEWIN
AF9
SMYSLEWOUT
AF10
CFG0 G16
CFG1
H13
CFG2
G14
CFG3
F16
CFG4
F15
CFG5
G15
CFG6
E16
CFG7
D17
CFG8
J16
CFG9
D15
CFG10
E15
CFG11
D14
CFG12
E14
CFG13
H12
CFG14
C14
CFG15 H15
CFG16 J15
CFG17 H14
CFG18 G22
CFG19 G23
CFG20 D23
RSVD21 G25
RSVD22 G24
RSVD23 J17
RSVD24 A31
RSVD25 A30
RSVD26 D26
RSVD27 D25
BM_BUSY# J23
EXT_TS0# J21
EXT_TS1# H22
THRMTRIP# F5
PWROK
AD30
RSTIN#
AE29
DREF_CLKN
A24
DREF_CLKP
A23
DREF_SSCLKN
C37
DREF_SSCLKP
D37
NC1
AP37
NC2
AN37
NC3
AP36
NC4
AP2
NC5
AP1
NC6
AN1
NC7
B1
NC8
A2
NC9
B37
NC10
A36
NC11
A37
DMITXN2
AC33
DMITXN3
AD37
DMIRXN3
AD35
DMIRXN2
AC31
DMITXP2
AB33
DMITXP3
AC37
DMIRXP2
AB31
DMIRXP3
AC35
R397
221_0603_1%
1
2
R376
200_0402_1%
1
2
R484 80.6_0402_1%
1 2
R37 1K_0402_5%
@
1 2
R36 1K_0402_5%
@
1 2
R41
54.9_0402_1%
1
2
T26
PAD @
T27 PAD
@
R370 2.2K_0402_5%
1 2
R374 2.2K_0402_5%
@
1 2
C419
0.1U_0402_16V4Z
1
2
R365
10K_0402_5%
1
2
R477
40.2_0402_1%
@
1
2
R388
100_0402_1%
1
2
T25
PAD @
R489
80.6_0402_1%
1
2
R66
54.9_0402_1%
1
2
R394 2.2K_0402_5%
@
1 2
R384 10K_0402_5%
@
1
2
C385
0.1U_0402_16V4Z
1
2
R77
24.9_0402_1%
1
2
R476
40.2_0402_1%
@
1
2
R44
24.9_0402_1%
1
2
R369 2.2K_0402_5%
1 2
R375 2.2K_0402_5%
@
1 2
R368 2.2K_0402_5%
1 2
R73
100_0603_1%
1
2
R430 2.2K_0402_5%
@
1 2
R418
0_0402_5%
1 2
R492 100_0402_1%
1 2
R372
100_0402_1%
1
2
R366
10K_0402_5%
1
2
R67
221_0603_1%
1
2
C428
0.1U_0402_16V4Z
1
2
C379
0.1U_0402_16V7K 1
2
C362
0.1U_0402_16V4Z
1
2

9. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM6
DDR_A_DM4
DDR_A_DM3
DDR_A_DM1
DDR_A_DM7
DDR_A_DM5
DDR_A_DM2
DDR_A_BS#0
DDR_A_BS#1
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_CAS#
DDR_A_WE#
DDR_A_RAS#
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA5
DDR_A_MA4
DDR_A_MA7
DDR_A_MA6
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_D5
DDR_A_D0
DDR_A_D10
DDR_A_D3
DDR_A_D1
DDR_A_D4
DDR_A_D11
DDR_A_D2
DDR_A_D8
DDR_A_D9
DDR_A_D6
DDR_A_D7
DDR_A_D17
DDR_A_D22
DDR_A_D15
DDR_A_D16
DDR_A_D13
DDR_A_D20
DDR_A_D12
DDR_A_D23
DDR_A_D19
DDR_A_D18
DDR_A_D14
DDR_A_D21
DDR_A_D25
DDR_A_D29
DDR_A_D24
DDR_A_D35
DDR_A_D30
DDR_A_D32
DDR_A_D34
DDR_A_D27
DDR_A_D33
DDR_A_D28
DDR_A_D26
DDR_A_D37
DDR_A_D40
DDR_A_D46
DDR_A_D44
DDR_A_D39
DDR_A_D36
DDR_A_D47
DDR_A_D31
DDR_A_D42
DDR_A_D43
DDR_A_D38
DDR_A_D41
DDR_A_D45
DDR_A_D53
DDR_A_D48
DDR_A_D59
DDR_A_D56
DDR_A_D58
DDR_A_D51
DDR_A_D52
DDR_A_D57
DDR_A_D50
DDR_A_D49
DDR_A_D63
DDR_A_D55
DDR_A_D54
DDR_A_D61
DDR_A_D60
DDR_A_D62
DDR_B_BS#0
DDR_B_BS#1
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
DDR_B_MA0
DDR_B_MA1
DDR_B_MA7
DDR_B_MA2
DDR_B_MA3
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_MA4
DDR_B_MA6
DDR_B_MA13
DDR_B_MA11
DDR_B_MA10
DDR_B_BS#2
DDR_A_BS#0
<13>
DDR_A_BS#1
<13>
DDR_A_DM[0..7]
<13>
DDR_A_MA[0..13]
<13>
DDR_A_CAS#
<13>
DDR_A_RAS#
<13>
DDR_B_WE#
<14>
DDR_B_CAS#
<14>
DDR_B_RAS#
<14>
DDR_B_MA[0..13]
<14>
DDR_B_BS#0
<14>
DDR_B_BS#1
<14>
DDR_A_D[0..63] <13>
DDR_A_DQS[0..7]
<13>
DDR_A_WE#
<13>
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
9 52
Friday, March 11, 2005
2005/03/01 2006/03/01
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
T34 PAD
DDR
SYSTEM
MEMORY
B
U5D
ALVISO_BGA1257
SBDQ0
AE31
SBDQ1
AE32
SBDQ2
AG32
SBDQ3
AG36
SBDQ4
AE34
SBDQ5 AE33
SBDQ6 AF31
SBDQ7 AF30
SBDQ8 AH33
SBDQ9 AH32
SBDQ10 AK31
SBDQ11 AG30
SBDQ12 AG34
SBDQ13 AG33
SBDQ14 AH31
SBDQ15 AJ31
SBDQ16 AK30
SBDQ17 AJ30
SBDQ18 AH29
SBDQ19 AH28
SBDQ20 AK29
SBDQ21 AH30
SBDQ22 AH27
SBDQ23 AG28
SBDQ24 AF24
SBDQ25 AG23
SBDQ26 AJ22
SBDQ27 AK22
SBDQ28 AH24
SBDQ29 AH23
SBDQ30 AG22
SBDQ31 AJ21
SBDQ32 AG10
SBDQ33
AG9
SBDQ34
AG8
SBDQ35
AH8
SBDQ36
AH11
SBDQ37
AH10
SBDQ38
AJ9
SBDQ39
AK9
SBDQ40
AJ7
SBDQ41
AK6
SBDQ42
AJ4
SBDQ43
AH5
SBDQ44
AK8
SBDQ45
AJ8
SBDQ46
AJ5
SB_BS0#
AJ15
SB_BS1#
AG17
SB_BS2#
AG21
SBDQ47
AK4
SBDQ48
AG5
SBDQ49
AG4
SBDQ50
AD8
SBDQ51
AD9
SBDQ52
AH4
SBDQ53
AG6
SBDQ54
AE8
SBDQ55
AD7
SBDQ56
AC5
SBDQ57
AB8
SBDQ58
AB6
SBDQ59
AA8
SBDQ60
AC8
SBDQ61
AC7
SBDQ62
AA4
SBDQ63
AA5
SB_CAS#
AH14
SB_RAS#
AK14
SB_RCVENIN#
AF15
SB_RCVENOUT#
AF14
SB_WE#
AH16
SB_MA0
AH17
SB_MA1
AK17
SB_MA2
AH18
SB_MA3
AJ18
SB_MA4
AK18
SB_MA5
AJ19
SB_MA6
AK19
SB_MA7
AH19
SB_MA8
AJ20
SB_MA9
AH20
SB_MA10
AJ16
SB_MA11
AG18
SB_MA12
AG20
SB_MA13
AG15
SB_DQS0#
AF35
SB_DQS1#
AK33
SB_DQS2#
AK28
SB_DQS3#
AJ23
SB_DQS4#
AL10
SB_DQS5#
AH7
SB_DQS6#
AF7
SB_DQS7#
AB5
SB_DQS0
AF34
SB_DQS1
AK32
SB_DQS2
AJ28
SB_DQS3
AK23
SB_DQS4
AM10
SB_DQS5
AH6
SB_DQS6
AF8
SB_DQS7
AB4
SB_DM0
AF32
SB_DM1
AK34
SB_DM2
AK27
SB_DM3
AK24
SB_DM4
AJ10
SB_DM5
AK5
SB_DM6
AE7
SB_DM7
AB7
DDR
MEMORY
SYSTEM
A
U5C
ALVISO_BGA1257
SADQ0
AG35
SADQ1
AH35
SADQ2
AL35
SADQ3
AL37
SADQ4
AH36
SADQ5 AJ35
SADQ6 AK37
SADQ7 AL34
SADQ8 AM36
SADQ9 AN35
SADQ10 AP32
SADQ11 AM31
SADQ12 AM34
SADQ13 AM35
SADQ14 AL32
SADQ15 AM32
SADQ16 AN31
SADQ17 AP31
SADQ18 AN28
SADQ19 AP28
SADQ20 AL30
SADQ21 AM30
SADQ22 AM28
SADQ23 AL28
SADQ24 AP27
SADQ25 AM27
SADQ26 AM23
SADQ27 AM22
SADQ28 AL23
SADQ29 AM24
SADQ30 AN22
SADQ31 AP22
SADQ32 AM9
SADQ33
AL9
SADQ34
AL6
SADQ35
AP7
SADQ36
AP11
SADQ37
AP10
SADQ38
AL7
SADQ39
AM7
SADQ40
AN5
SADQ41
AN6
SADQ42
AN3
SADQ43
AP3
SADQ44
AP6
SADQ45
AM6
SADQ46
AL4
SADQ47
AM3
SADQ48
AK2
SADQ49
AK3
SADQ50
AG2
SADQ51
AG1
SADQ52
AL3
SADQ53
AM2
SADQ54
AH3
SADQ55
AG3
SADQ56
AF3
SADQ57
AE3
SADQ58
AD6
SADQ59
AC4
SADQ60
AF2
SADQ61
AF1
SADQ62
AD4
SADQ63
AD5
SA_BS0#
AK15
SA_BS1#
AK16
SA_BS2#
AL21
SA_DM0
AJ37
SA_DM1
AP35
SA_DM2
AL29
SA_DM3
AP24
SA_DM4
AP9
SA_DM5
AP4
SA_DM6
AJ2
SA_DM7
AD3
SA_DQS0
AK36
SA_DQS1
AP33
SA_DQS2
AN29
SA_DQS3
AP23
SA_DQS4
AM8
SA_DQS5
AM4
SA_DQS6
AJ1
SA_DQS7
AE5
SA_DQS0#
AK35
SA_DQS1#
AP34
SA_DQS2#
AN30
SA_DQS3#
AN23
SA_DQS4#
AN8
SA_DQS5#
AM5
SA_DQS6#
AH1
SA_DQS7#
AE4
SA_MA0
AL17
SA_MA1
AP17
SA_MA2
AP18
SA_MA3
AM17
SA_MA4
AN18
SA_MA5
AM18
SA_MA6
AL19
SA_MA7
AP20
SA_MA8
AM19
SA_MA9
AL20
SA_MA10
AM16
SA_MA11
AN20
SA_MA12
AM20
SA_MA13
AM15
SA_CAS#
AN15
SA_RAS#
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
SA_WE#
AP15
T38 PAD
T35 PAD
T36 PAD T33 PAD
T37 PAD

10. w
w
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R
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c
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN7
PEG_RXN6
PEG_RXN8
PEG_RXN9
PEG_RXN11
PEG_RXN10
PEG_RXN14
PEG_RXN15
PEG_RXN13
PEG_RXN12
PEG_RXP1
PEG_RXP3
PEG_RXP2
PEG_RXP6
PEG_RXP7
PEG_RXP5
PEG_RXP4
PEG_RXP11
PEG_RXP9
PEG_RXP8
PEG_RXP12
PEG_RXP13
PEG_RXP15
PEG_RXP14
PEG_RXP10
PEG_TXN0
PEG_TXN1
PEG_TXN3
PEG_TXN2
PEG_TXN6
PEG_TXN7
PEG_TXN5
PEG_TXN4
PEG_TXN11
PEG_TXN9
PEG_TXN8
PEG_TXN12
PEG_TXN13
PEG_TXN15
PEG_TXN14
PEG_TXN10
PEG_TXP0
PEG_TXP1
PEG_TXP3
PEG_TXP2
PEG_TXP6
PEG_TXP7
PEG_TXP5
PEG_TXP4
PEG_TXP11
PEG_TXP9
PEG_TXP8
PEG_TXP12
PEG_TXP13
PEG_TXP15
PEG_TXP14
PEG_TXP10
PEG_RXN[0..15]
PEG_TXN[0..15]
PEG_TXP[0..15]
PEG_RXP[0..15]
PEG_RXP0
PEGCOMP
LVDS_A0-
LVDS_A1-
LVDS_A2-
LVDS_A1+
LVDS_A2+
LVDS_A0+
LVDS_B1-
LVDS_B2-
LVDS_B0+
LVDS_B1+
LVDS_B2+
LVDS_B0-
LVDS_BC+
LVDS_BC-
LVDS_AC+
LVDS_AC-
CLK_DDC2
DAT_DDC2
LCD_CLK
LCD_DAT
LCD_CLK
LCD_DAT
BIA
BK_EN
LCTLA_CLK
LCTLB_DAT
LCTLA_CLK
LCTLB_DAT
EN_LCDVDD
CLK_DDC2
DAT_DDC2
BIA
<16,32>
Y/G
<17>
COMP/B
<17>
C/R
<17>
CLK_MCH_3GPLL#
<18>
CLK_MCH_3GPLL
<18>
CLK_DDC2
<17>
VSYNC
<17>
HSYNC
<17>
DAT_DDC2
<17>
CRT_BLU
<17>
CRT_GRN
<17>
CRT_RED
<17>
BK_EN
<16>
LVDS_AC-
<16>
LVDS_AC+
<16>
LVDS_BC-
<16>
LVDS_BC+
<16>
LVDS_A0-
<16>
LVDS_A1-
<16>
LVDS_A2-
<16>
LVDS_A0+
<16>
LVDS_A1+
<16>
LVDS_A2+
<16>
LVDS_B0-
<16>
LVDS_B1-
<16>
LVDS_B2-
<16>
LVDS_B0+
<16>
LVDS_B1+
<16>
LVDS_B2+
<16>
EN_LCDVDD
<16>
LCD_CLK
<16>
LCD_DAT
<16>
PEG_RXN[0..15] <16>
PEG_RXP[0..15] <16>
PEG_TXN[0..15] <16>
PEG_TXP[0..15] <16>
+1.5VS_PCIE
+2.5VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
10 52
Friday, March 11, 2005
2005/03/01 2006/03/01
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
R29 3K_0402_5%
@
1 2
R364 2.2K_0402_5%
1 2
R362 2.2K_0402_5%
1 2
R363 2.2K_0402_5%
1 2
R30
3K_0402_5%
@
1 2
R34
150_0402_1%
1@
1
2
R3781.5K_0402_1%
1
2
MISC
TV
VGA
LVDS
PCI
-
EXPRESS
GRAPHICS
U5G
ALVISO_BGA1257
SDVOCTRL_DATA
H24
SDVOCTRL_CLK
H25
GCLKN
AB29
GCLKP
AC29
TVDAC_A
A15
TVDAC_B
C16
TVDAC_C
A17
TV_REFSET
J18
TV_IRTNA
B15
TV_IRTNB
B16
TV_IRTNC
B17
GREEN#
B20
HSYNC
G21
DDCCLK
E24
DDCDATA
E23
BLUE
E21
BLUE#
D21
GREEN
C20
RED
A19
RED#
B19
VSYNC
H21
REFSET
J20
LDDC_CLK
F23
LBKLT_CTL
E25
LBKLT_EN
F25
LCTLA_CLK
C23
LCTLB_DATA
C22
LDDC_DATA
F22
LVDD_EN
F26
LIBG
C33
LVBG
C31
LVREFH
F28
LVREFL
F27
LACLKN
B30
LACLKP
B29
LBCLKN
C25
LBCLKP
C24
LADATAN0
B34
LADATAN1
B33
LADATAN2
B32
LADATAP0
A34
LADATAP1
A33
LADATAP2
B31
LBDATAN0
C29
LBDATAN1
D28
LBDATAN2
C27
LBDATAP2
C26
EXP_COMPI
D36
EXP_ICOMPO
D34
EXP_RXN0/SDVO_TVCLKIN#
E30
EXP_RXN1/SDVO_INT#
F34
EXP_RXN2/SDVO_FLDSTALL#
G30
EXP_RXN3
H34
EXP_RXN4
J30
EXP_RXN5
K34
EXP_RXN6
L30
EXP_RXN7
M34
EXP_RXN8
N30
EXP_RXN9
P34
EXP_RXN10
R30
EXP_RXN11 T34
EXP_RXN12 U30
EXP_RXN13 V34
EXP_RXN14 W30
EXP_RXN15 Y34
EXP_RXP0/SDVO_TVCLKIN D30
EXP_RXP1/SDVO_INT E34
EXP_RXP2/SDVO_FLDSTALL F30
EXP_RXP3 G34
EXP_RXP4 H30
EXP_RXP5 J34
EXP_RXP6 K30
EXP_RXP7 L34
EXP_RXP8 M30
EXP_RXP9 N34
EXP_RXP10 P30
EXP_RXP11 R34
EXP_RXP12 T30
EXP_RXP13 U34
EXP_RXP14 V30
EXP_RXP15 W34
EXP_TXN0/SDVOB_RED# E32
EXP_TXN1/SDVOB_GREEN# F36
EXP_TXN2/SDVOB_BLUE# G32
EXP_TXN3/SDVOB_CLKN H36
EXP_TXN4/SDVOC_RED# J32
EXP_TXN5/SDVOC_GREEN#
K36
EXP_TXN6/SDVOC_BLUE#
L32
EXP_TXN7/SDVOC_CLKN
M36
EXP_TXN8
N32
EXP_TXN9
P36
EXP_TXN10
R32
EXP_TXN11
T36
EXP_TXN12
U32
EXP_TXN13
V36
EXP_TXN14
W32
EXP_TXN15
Y36
EXP_TXP0/SDVOB_RED
D32
EXP_TXP1/SDVOB_GREEN
E36
EXP_TXP2/SDVOB_BLUE
F32
EXP_TXP3/SDVOB_CLKP
G36
EXP_TXP4/SDVOC_RED
H32
EXP_TXP5/SDVOC_GREEN
J36
EXP_TXP6/SDVOC_BLUE
K32
EXP_TXP7/SDVOC_CLKP
L36
EXP_TXP8
M32
EXP_TXP9
N36
EXP_TXP10
P32
EXP_TXP11
R36
EXP_TXP12
T32
EXP_TXP13
U36
EXP_TXP14
V32
EXP_TXP15
W36
LBDATAP0
C28
LBDATAP1
D27
R429
255_0402_1%
1 2
R33
150_0402_1%
1@
1
2
R396 100K_0402_1%
1 2
R385 2.2K_0402_5%
1 2
R428
4.99K_0603_1%
1
2
R360 2.2K_0402_5%
1 2
R392
0_0402_5%
1@
1 2
R361 2.2K_0402_5%
1 2
R32
150_0402_1%
1@
1
2
R404100K_0402_1%
1 2
R40
24.9_0603_1%
1 2

11. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V1.8_DDR_CAP3
V1.8_DDR_CAP4
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP6
3GRLL_R
V1.8_DDR_CAP3
+1.5VS_PM
VCC_SYNC
VCC_SYNC
+2.5VS_PM
V1.8_DDR_CAP5
V1.8_DDR_CAP2
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP1
V1.8_DDR_CAP5
+1.5VS_PM
+2.5VS_PM
+2.5VS_LVDSPM
+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS
+1.5VS_DDRDLL
+1.5VS
+1.5VS
+1.5VS_3GPLL
+2.5VS
+2.5VS_3GBG
+VCCP
+2.5V
+1.5VS_MPLL
+1.5VS
+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS
+1.5VS_HPLL
+1.5VS
+1.5VS_DPLLB
+1.5VS
+1.5VS_DPLLA
+1.5VS
+2.5VS
+2.5VS
+VCCP
+1.5VS_PCIE
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+3VS
+1.5VS
+2.5V
+VCCP
+VCCP
+VCCP +VCCP
+2.5VS +3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
11 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Note : All VCCSM pin
shorted internally.
W=20 mils
Note: Place near chip.
Close B26,B25,A25
Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.
C52
0.22U_0603_10V7K
1
2
C433
10U_1206_6.3V6M
1
2
C363
0.022U_0402_16V7K
1
2
C353
0.022U_0402_16V7K
1
2
C126
10U_1206_6.3V6M
1
2
C329
4.7U_0805_6.3V6K
1
2
C30
10U_1206_6.3V6M
1
2
C365
0.1U_0402_16V4Z
1
2
C339
0.022U_0402_16V7K
1
2
C388
0.1U_0402_16V4Z
1
2
+
C131
100U_D2_6.3VM
1
2
C418
0.1U_0402_16V4Z
1
2
POWER
U5F
ALVISO_BGA1257
VTT0
K13
VTT1
J13
VTT2
K12
VTT3
W11
VTT4
V11
VTT5
U11
VTT6
T11
VTT7
R11
VTT8
P11
VTT9
N11
VTT10
M11
VTT11
L11
VTT12
K11
VTT13
W10
VTT14
V10
VTT15
U10
VTT16
T10
VTT17
R10
VTT18
P10
VTT19
N10
VTT20
M10
VTT21
K10
VTT22
J10
VTT23
Y9
VTT24
W9
VTT25
U9
VTT26
R9
VTT27
P9
VTT28
N9
VTT29
M9
VTT30
L9
VTT31
J9
VTT32
N8
VTT33
M8
VTT34
N7
VTT35
M7
VTT36
N6
VTT37
M6
VTT38
A6
VTT39
N5
VTT40
M5
VTT41
N4
VTT42
M4
VTT43
N3
VTT44
M3
VTT45
N2
VTT46
M2
VTT47
B2
VTT48
V1
VTT49
N1
VTT50
M1
VTT51
G1
VCCSM0 AM37
VCCSM1 AH37
VCCSM2 AP29
VCCSM3 AD28
VCCSM4 AD27
VCCSM5 AC27
VCCSM6 AP26
VCCSM7 AN26
VCCSM8
AM26
VCCSM9
AL26
VCCSM10
AK26
VCCSM11
AJ26
VCCSM12
AH26
VCCSM13
AG26
VCCSM14
AF26
VCCSM15
AE26
VCCSM16
AP25
VCCSM17
AN25
VCCSM18
AM25
VCCSM19
AL25
VCCSM20
AK25
VCCSM21
AJ25
VCCSM22 AH25
VCCSM23 AG25
VCCSM24 AF25
VCCSM25 AE25
VCCSM26 AE24
VCCSM27 AE23
VCCSM28 AE22
VCCSM29 AE21
VCCSM30 AE20
VCCSM31 AE19
VCCSM32 AE18
VCCSM33 AE17
VCCSM34 AE16
VCCSM35 AE15
VCCSM36 AE14
VCCSM37 AP13
VCCSM38 AN13
VCCSM39 AM13
VCCSM40 AL13
VCCSM41 AK13
VCCSM42 AJ13
VCCSM43 AH13
VCCSM44 AG13
VCCSM45 AF13
VCCSM46 AE13
VCCSM47 AP12
VCCSM48 AN12
VCCSM49 AM12
VCCSM50
AL12
VCCSM51
AK12
VCCSM52
AJ12
VCCSM53
AH12
VCCSM54
AG12
VCCSM55
AF12
VCCSM56
AE12
VCCSM57
AD11
VCCSM58
AC11
VCCSM59
AB11
VCCSM60
AB10
VCCSM61
AB9
VCCSM62
AP8
VCCSM63
AM1
VCCSM64
AE1
C140
0.1U_0402_16V4Z
1
2
C412
0.1U_0402_16V4Z
1
2
C399
0.1U_0402_16V4Z
1
2
C438
0.1U_0402_16V4Z
1
2
C429
0.1U_0402_16V7K
1
2
R740 0_0603_5% 1@
1 2
C341
0.1U_0402_16V4Z
1
2
C475
0.1U_0402_16V7K
1
2
L26
0_0603_5%
1
2
C29
0.47U_0603_16V7K
1
2
L13
CHB1608U301_0603
1
2
L19
CHB1608U301_0603
1 2
C678
0.1U_0402_16V4Z
1
2
D22
1N4148_SOD80
@
1
2
POWER
U5E
ALVISO_BGA1257
VCC0
T29
VCC1
R29
VCC2
N29
VCC3
M29
VCC4
K29
VCC5
J29
VCC6
V28
VCC7
U28
VCC8
T28
VCC9
R28
VCC10
P28
VCC11
N28
VCC12
M28
VCC13
L28
VCC14
K28
VCC15
J28
VCC16
H28
VCC17
G28
VCC18
V27
VCC19
U27
VCC20
T27
VCC21
R27
VCC22
P27
VCC23
N27
VCC24
M27
VCC25
L27
VCC26
K27
VCC27
J27
VCC28
H27
VCC29
K26
VCC30
H26
VCC31
K25
VCC32
J25
VCC33
K24
VCC34
K23
VCC35
K22
VCC36
K21
VCC37
W20
VCC38
U20
VCC39
T20
VCC40
K20
VCC41
V19
VCC42
U19
VCC43
K19
VCC44
W18
VCC45
V18
VCC46
T18
VCC47
K18
VCC48
K17
VCCD_HMPLL1
AC1
VCCD_HMPLL2
AC2
VCCA_DPLLA
B23
VCCA_DPLLB
C35
VCCA_HPLL
AA1
VCCA_MPLL
AA2
VCCA_TVDACA0 F17
VCCA_TVDACA1 E17
VCCA_TVDACB0 D18
VCCA_TVDACB1 C18
VCCA_TVDACC0
F18
VCCA_TVDACC1
E18
VCCA_TVBG
H18
VSSA_TVBG
G18
VCCD_TVDAC
D19
VCCDQ_TVDAC
H17
VCCD_LVDS0
B26
VCCD_LVDS1
B25
VCCD_LVDS2
A25
VCCA_LVDS
A35
VCCHV0 B22
VCCHV1 B21
VCCHV2 A21
VCCTX_LVDS0 B28
VCCTX_LVDS1 A28
VCCTX_LVDS2 A27
VCCA_SM0 AF20
VCCA_SM1 AP19
VCCA_SM2 AF19
VCCA_SM3 AF18
VCC3G0 AE37
VCC3G1 W37
VCC3G2 U37
VCC3G3 R37
VCC3G4 N37
VCC3G5 L37
VCC3G6 J37
VCCA_3GPLL0 Y29
VCCA_3GPLL1 Y28
VCCA_3GPLL2 Y27
VCCA_3GBG
F37
VSSA_3GBG
G37
VCC_SYNC
H20
VCCA_CRTDAC0
F19
VCCA_CRTDAC1
E19
VSSA_CRTDAC
G19
+
C81
330U_D2E_2.5VM
1
2
+
C403
330U_D2E_2.5VM
1
2
C355
0.1U_0402_16V4Z
1
2
C420
0.1U_0402_16V4Z
1
2
C31
0.1U_0402_16V4Z
1
2
C468
0.1U_0402_16V7K
1
2
C340
0.1U_0402_16V4Z
1
2
C74
0.22U_0603_10V7K
1
2
C346
0.01U_0402_16V7K
1
2
L20
CHB1608U301_0603
1 2
C336
0.022U_0402_16V7K
1
2
R741
0_0603_5%
2@
1
2
C372
0.1U_0402_16V4Z
1
2
C685
0.1U_0402_16V4Z
1
2
R31
0_0402_5%
@
1
2
C354
0.1U_0402_16V4Z
1
2
D21
1N4148_SOD80
@
1
2
C334
10U_1206_6.3V6M
1
2
C683
0.1U_0402_16V4Z
1
2
C473
0.1U_0402_16V4Z
1
2
C408
0.1U_0402_16V4Z
1
2
C135
10U_1206_6.3V6M
1
2
C681
0.1U_0402_16V4Z
1
2
C342
0.1U_0402_16V4Z
1
2
R134
0.5_0805_1%
1 2
C366
0.022U_0402_16V7K
1
2
C352
0.1U_0402_16V4Z
1
2
+
C348
330U_D2E_2.5VM
1
2
C676
0.1U_0402_16V4Z
1
2
+
C330
330U_D2E_2.5VM
1
2
10U_1206_6.3V6M
1
2
C411
0.1U_0402_16V4Z
1
2
C682
0.1U_0402_16V4Z
1
2
C345
0.1U_0402_16V4Z
1
2
C684
0.1U_0402_16V4Z
1
2
C680
0.1U_0402_16V4Z
1
2
C404
0.1U_0402_16V4Z
1
2
C128
0.1U_0402_16V4Z
1
2
C674
0.1U_0402_16V4Z
1
2
C391
2.2U_0805_10V6K
1
2
C478
0.1U_0402_16V7K
1
2
R739 0_0603_5%
1@
1 2
C380
10U_1206_6.3V6M
1
2
C392
4.7U_0805_6.3V6K
1
2
L23
CHB1608U301_0603
1 2
R805
10K_0402_5%
@
1 2
C349
0.1U_0402_16V4Z
1
2
R737 0_0603_5%
2@ 1 2
C409
0.1U_0402_16V4Z
1
2
C443
0.1U_0402_16V7K
1
2
+
C130
330U_D2E_2.5VM
1
2
C675
0.1U_0402_16V4Z
1
2
L14
0_0603_5%
1
2
+
C452
220U_D2_4VM
1
2
C371
0.1U_0402_16V4Z
1
2
C413
0.1U_0402_16V4Z
1
2
C28
0.47U_0603_16V7K
1
2
R736 0_0603_5%
1@
1 2
C367
0.1U_0402_16V4Z
1
2
C347
0.1U_0402_16V4Z
1
2
R738 0_0603_5%
2@ 1 2
C465
0.1U_0402_16V7K
1
2
C393
10U_1206_6.3V6M
1
2
C127
10U_1206_6.3V6M
1
2
R806
10K_0402_5%
@
1 2
R28
0_0402_5%
1
2
C677
0.1U_0402_16V4Z
1
2
L11
CHB1608U301_0603
1 2
L9
0_0603_5%
1
2

12. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP +2.5V
+VCCP
+VCCP
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
12 52
Friday, March 11, 2005
2005/03/01 2006/03/01
C695
0.1U_0402_10V6K
1
2
C691
0.1U_0402_10V6K
1
2
C702
0.1U_0402_10V6K
1
2
C699
0.1U_0402_10V6K
1
2
C696
0.1U_0402_10V6K
1
2
C693
0.1U_0402_10V6K
1
2
C687
0.1U_0402_10V6K
1
2
C689
0.1U_0402_10V6K
1
2
C694
0.1U_0402_10V6K
1
2
C690
0.1U_0402_10V6K
1
2
C698
0.1U_0402_10V6K
1
2
C703
0.1U_0402_10V6K
1
2
VSS
U5I
ALVISO_BGA1257
VSS271
Y1
VSS270
D2
VSS269
G2
VSS268
J2
VSS260
L2
VSS259
P2
VSS258
T2
VSS257
V2
VSS256
AD2
VSS255
AE2
VSS254
AH2
VSS253
AL2
VSS252
AN2
VSS251
A3
VSS250
C3
VSS249
AA3
VSS248
AB3
VSS247
AC3
VSS246
AJ3
VSS245
C4
VSS244
H4
VSS243
L4
VSS242
P4
VSS241
U4
VSS240
Y4
VSS239
AF4
VSS238
AN4
VSS237
E5
VSS236
W5
VSS235
AL5
VSS234
AP5
VSS233
B6
VSS232
J6
VSS231
L6
VSS230
P6
VSS229
T6
VSS228
AA6
VSS227
AC6
VSS226
AE6
VSS225
AJ6
VSS224
G7
VSS223
V7
VSS222
AA7
VSS221
AG7
VSS220
AK7
VSS219
AN7
VSS218
C8
VSS217
E8
VSS216
L8
VSS215
P8
VSS214
Y8
VSS213
AL8
VSS212
A9
VSS211
H9
VSS210
K9
VSS209
T9
VSS208
V9
VSS207
AA9
VSS206
AC9
VSS205
AE9
VSS204
AH9
VSS203
AN9
VSS202
D10
VSS201
L10
VSS200
Y10
VSSALVDS B36
VSS199
AA10
VSS198
F11
VSS197
H11
VSS196
Y11
VSS195 AA11
VSS194 AF11
VSS193 AG11
VSS192 AJ11
VSS191 AL11
VSS190 AN11
VSS189 B12
VSS188 D12
VSS187 J12
VSS186 A14
VSS185 B14
VSS184 F14
VSS183 J14
VSS182 K14
VSS181 AG14
VSS180 AJ14
VSS179 AL14
VSS178 AN14
VSS177 C15
VSS176 K15
VSS175 A16
VSS174 D16
VSS173 H16
VSS172 K16
VSS171 AL16
VSS170
C17
VSS169
G17
VSS168
AF17
VSS167
AJ17
VSS166
AN17
VSS165
A18
VSS164
B18
VSS163
U18
VSS162
AL18
VSS161
C19
VSS160
H19
VSS159
J19
VSS158
T19
VSS157
W19
VSS156
AG19
VSS155
AN19
VSS154
A20
VSS153
D20
VSS152
E20
VSS151
F20
VSS150
G20
VSS149
V20
VSS148
AK20
VSS147
C21
VSS146
F21
VSS145
AF21
VSS144
AN21
VSS143
A22
VSS142
D22
VSS141
E22
VSS140
J22
VSS139
AH22
VSS138
AL22
VSS137
H23
VSS136
AF23
VSS135
B24
VSS134
D24
VSS133
F24
VSS132
J24
VSS131
AG24
VSS130
AJ24
C688
0.1U_0402_10V6K
1
2
VSS
U5J
ALVISO_BGA1257
VSS267
AL24
VSS266
AN24
VSS265
A26
VSS264
E26
VSS263
G26
VSS262
J26
VSS261
B27
VSS129
E27
VSS128
G27
VSS127
W27
VSS126
AA27
VSS125
AB27
VSS124
AF27
VSS123
AG27
VSS122
AJ27
VSS121
AL27
VSS120
AN27
VSS119
E28
VSS118
W28
VSS117
AA28
VSS116
AB28
VSS115
AC28
VSS114
A29
VSS113
D29
VSS112
E29
VSS111
F29
VSS110
G29
VSS109
H29
VSS108
L29
VSS107
P29
VSS106
U29
VSS105
V29
VSS104
W29
VSS103
AA29
VSS102
AD29
VSS101
AG29
VSS100
AJ29
VSS99
AM29
VSS98
C30
VSS97
Y30
VSS96
AA30
VSS95
AB30
VSS94
AC30
VSS93
AE30
VSS92
AP30
VSS91
D31
VSS90
E31
VSS89
F31
VSS88
G31
VSS87
H31
VSS86
J31
VSS85
K31
VSS84
L31
VSS83
M31
VSS82
N31
VSS81
P31
VSS80
R31
VSS79
T31
VSS78
U31
VSS77
V31
VSS76
W31
VSS75
AD31
VSS74
AG31
VSS73
AL31
VSS72
A32
VSS71
C32
VSS70
Y32
VSS69
AA32
VSS68
AB32
VSS67 AC32
VSS66 AD32
VSS65 AJ32
VSS64 AN32
VSS63 D33
VSS62 E33
VSS61 F33
VSS60 G33
VSS59 H33
VSS58 J33
VSS57 K33
VSS56 L33
VSS55 M33
VSS54 N33
VSS53 P33
VSS52 R33
VSS51 T33
VSS50 U33
VSS49 V33
VSS48 W33
VSS47 AD33
VSS46 AF33
VSS45 AL33
VSS44 C34
VSS43 AA34
VSS42 AB34
VSS41 AC34
VSS40
AD34
VSS39
AH34
VSS38
AN34
VSS37
B35
VSS36
D35
VSS35
E35
VSS34
F35
VSS33
G35
VSS32
H35
VSS31
J35
VSS30
K35
VSS29
L35
VSS28
M35
VSS27
N35
VSS26
P35
VSS25
R35
VSS24
T35
VSS23
U35
VSS22
V35
VSS21
W35
VSS20
Y35
VSS19
AE35
VSS18
C36
VSS17
AA36
VSS16
AB36
VSS15
AC36
VSS14
AD36
VSS13
AE36
VSS12
AF36
VSS11
AJ36
VSS10
AL36
VSS9
AN36
VSS8
E37
VSS7
H37
VSS6
K37
VSS5
M37
VSS4
P37
VSS3
T37
VSS2
V37
VSS1
Y37
VSS0
AG37
C697
0.1U_0402_10V6K
1
2
C692
0.1U_0402_10V6K
1
2
C686
0.1U_0402_10V6K
1
2
NCTF
U5H
ALVISO_BGA1257
VCCSM_NCTF31
AB12
VCCSM_NCTF30
AC12
VCCSM_NCTF29
AD12
VCCSM_NCTF28
AB13
VCCSM_NCTF27
AC13
VCCSM_NCTF26
AD13
VCCSM_NCTF25
AC14
VCCSM_NCTF24
AD14
VCCSM_NCTF23
AC15
VCCSM_NCTF22
AD15
VCCSM_NCTF21
AC16
VCCSM_NCTF20 AD16
VCCSM_NCTF19 AC17
VCCSM_NCTF18 AD17
VCCSM_NCTF17 AC18
VCCSM_NCTF16 AD18
VCCSM_NCTF15 AC19
VCCSM_NCTF14 AD19
VCCSM_NCTF13 AC20
VCCSM_NCTF12 AD20
VCCSM_NCTF11 AC21
VCCSM_NCTF10 AD21
VCCSM_NCTF9 AC22
VCCSM_NCTF8 AD22
VCCSM_NCTF7 AC23
VCCSM_NCTF6 AD23
VCCSM_NCTF5 AC24
VCCSM_NCTF4 AD24
VCCSM_NCTF3 AC25
VCCSM_NCTF2 AD25
VCCSM_NCTF1 AC26
VCC_NCTF78 L17
VCC_NCTF77 M17
VCC_NCTF76 N17
VCC_NCTF75 P17
VCC_NCTF74 T17
VCC_NCTF73 U17
VCC_NCTF72
V17
VCC_NCTF71
W17
VCC_NCTF70
L18
VCC_NCTF69
M18
VCC_NCTF68
N18
VCC_NCTF67
P18
VCC_NCTF66
R18
VCC_NCTF65
Y18
VCC_NCTF64
L19
VCC_NCTF63
M19
VCC_NCTF62
N19
VCC_NCTF61
P19
VCC_NCTF60
R19
VCC_NCTF59
Y19
VCC_NCTF58
L20
VCC_NCTF57
M20
VCC_NCTF56
N20
VCC_NCTF55
P20
VCC_NCTF54
R20
VCC_NCTF53
Y20
VCC_NCTF52
L21
VCC_NCTF51
M21
VCC_NCTF50
N21
VCC_NCTF49
P21
VCC_NCTF48
T21
VCC_NCTF47
U21
VCC_NCTF46
V21
VCC_NCTF45
W21
VCC_NCTF44
L22
VCC_NCTF43
M22
VCC_NCTF42
N22
VCC_NCTF41
P22
VCC_NCTF40
R22
VCC_NCTF39
T22
VCC_NCTF38
U22
VCC_NCTF37
V22
VCC_NCTF36
W22
VCC_NCTF35
L23
VCC_NCTF34
M23
VCC_NCTF33
N23
VCC_NCTF32
P23
VCC_NCTF31
R23
VCC_NCTF30
T23
VCC_NCTF29
U23
VCC_NCTF28
V23
VCC_NCTF27
W23
VCC_NCTF26
L24
VCC_NCTF25
M24
VCC_NCTF24
N24
VCC_NCTF23
P24
VCC_NCTF22
R24
VCC_NCTF21
T24
VCC_NCTF20
U24
VCC_NCTF19
V24
VCC_NCTF18
W24
VCC_NCTF17
L25
VCC_NCTF16 M25
VCC_NCTF15 N25
VCC_NCTF14 P25
VCC_NCTF13 R25
VCC_NCTF12 T25
VCC_NCTF11 U25
VCCSM_NCTF0 AD26
VTT_NCTF17
L12
VTT_NCTF16
M12
VTT_NCTF15
N12
VTT_NCTF14
P12
VTT_NCTF13
R12
VTT_NCTF12
T12
VTT_NCTF11
U12
VTT_NCTF10
V12
VTT_NCTF9
W12
VTT_NCTF8
L13
VTT_NCTF7
M13
VTT_NCTF6
N13
VTT_NCTF5
P13
VTT_NCTF4
R13
VTT_NCTF3
T13
VTT_NCTF2
U13
VTT_NCTF1
V13
VTT_NCTF0
W13
VSS_NCTF68
Y12
VSS_NCTF67
AA12
VSS_NCTF66
Y13
VSS_NCTF65
AA13
VSS_NCTF64
L14
VSS_NCTF63
M14
VSS_NCTF62
N14
VSS_NCTF61
P14
VSS_NCTF60
R14
VSS_NCTF59
T14
VSS_NCTF58
U14
VSS_NCTF57
V14
VSS_NCTF56
W14
VSS_NCTF55
Y14
VSS_NCTF54
AA14
VSS_NCTF53
AB14
VSS_NCTF52
L15
VSS_NCTF51
M15
VSS_NCTF50
N15
VSS_NCTF49
P15
VSS_NCTF48
R15
VSS_NCTF47
T15
VSS_NCTF46
U15
VSS_NCTF45
V15
VSS_NCTF44
W15
VSS_NCTF43
Y15
VSS_NCTF42
AA15
VSS_NCTF41
AB15
VSS_NCTF40
L16
VSS_NCTF39
M16
VSS_NCTF38
N16
VSS_NCTF37
P16
VSS_NCTF36
R16
VSS_NCTF35
T16
VSS_NCTF34
U16
VSS_NCTF33
V16
VSS_NCTF32
W16
VSS_NCTF31
Y16
VSS_NCTF30
AA16
VSS_NCTF29
AB16
VSS_NCTF28
R17
VSS_NCTF27
Y17
VSS_NCTF26
AA17
VSS_NCTF25
AB17
VSS_NCTF24
AA18
VSS_NCTF23
AB18
VSS_NCTF22
AA19
VSS_NCTF21
AB19
VSS_NCTF20
AA20
VSS_NCTF19
AB20
VSS_NCTF18
R21
VSS_NCTF17
Y21
VSS_NCTF16
AA21
VSS_NCTF15
AB21
VSS_NCTF14
Y22
VSS_NCTF13
AA22
VSS_NCTF12
AB22
VSS_NCTF11
Y23
VSS_NCTF10
AA23
VSS_NCTF9
AB23
VSS_NCTF8
Y24
VSS_NCTF7
AA24
VSS_NCTF6
AB24
VSS_NCTF5
Y25
VSS_NCTF4
AA25
VSS_NCTF3
AB25
VSS_NCTF2
Y26
VSS_NCTF1
AA26
VSS_NCTF0
AB26
VCC_NCTF10
V25
VCC_NCTF9
W25
VCC_NCTF8
L26
VCC_NCTF7
M26
VCC_NCTF6
N26
VCC_NCTF5
P26
VCC_NCTF4
R26
VCC_NCTF3
T26
VCC_NCTF2
U26
VCC_NCTF1
V26
VCC_NCTF0
W26

13. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
DDR_A_BS#1
DDR_A_MA9
DDR_A_MA12
DDR_A_MA11
DDR_A_MA6
DDR_A_MA3
DDR_A_MA0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA2
DDR_A_MA5
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS#0
DDR_A_WE#
DDR_A_MA8
DDR_A_MA7
DDR_A_MA4
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_MA[0..13]
DDR_A_DQS[0..7]
DDR_A_D24
DDR_A_D19
DDR_A_D1
DDR_A_D2
DDR_A_D5
DDR_A_D3
DDR_A_DM0
DDR_A_DQS0
DDR_A_D0
DDR_A_D13
DDR_A_D7
DDR_A_D8
DDR_A_D6
DDR_A_D9
DDR_A_DM1
DDR_A_D12
DDR_A_DQS1
DDR_A_D11
DDR_A_D14
DDR_A_D20
DDR_A_D21
DDR_A_D17
DDR_A_D15
DDR_A_D10
DDR_A_D16
DDR_A_D28
DDR_A_D23
DDR_A_D22
DDR_A_DM2
DDR_A_D18
DDR_A_DQS2
DDR_CKE1
DDR_SCS#1
DDR_SCS#0
DDR_CKE0
CK_SCLK
DDR_CKE1 DDR_CKE0
DDR_SCS#0 DDR_SCS#1
DDR_A_MA5
DDR_A_MA3
DDR_A_MA7
DDR_A_MA1
DDR_A_MA12
DDR_A_MA9
DDR_A_MA10
DDR_DQS0
DDR_DQS2
DDR_DQS1
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_A_WE#
DDR_A_BS#0
DDR_D6
DDR_D4
DDR_D2
DDR_D0
DDR_D10
DDR_D8
DDR_D12
DDR_D14
DDR_D22
DDR_D18
DDR_D20
DDR_D24
DDR_D26
DDR_D16
DDR_D28
DDR_D30
DDR_D39
DDR_D35
DDR_D41
DDR_D33
DDR_D36
DDR_D45
DDR_A_MA0
DDR_A_MA2
DDR_A_MA6
DDR_A_MA4
DDR_A_MA8
DDR_A_MA11
DDR_DM6
DDR_DM3
DDR_DM0
DDR_DM1
DDR_DM7
DDR_DM2
DDR_DM4
DDR_DM5
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS#1
DDR_D11
DDR_D9
DDR_D23
DDR_D21
DDR_D27
DDR_D29
DDR_D25
DDR_D34
DDR_D32
DDR_D37
DDR_D47
DDR_D43
DDR_D40
DDR_D51
DDR_D44
DDR_D49
DDR_D48
DDR_D62
DDR_D61
DDR_D57
DDR_D42
DDR_D46
DDR_DQS6
DDR_D19
DDR_D56
DDR_D50
DDR_D17
DDR_D38
DDR_D31
DDR_D55
CK_SDATA
DDR_D5
DDR_D54
DDR_D7
DDR_D15
DDR_D1
DDR_D60
DDR_DQS7
DDR_D53
DDR_D3
DDR_D13
DDR_D52
DDR_A_DQS3
DDR_A_D29
DDR_A_DM3
DDR_A_D25
DDR_A_D31
DDR_A_D26
DDR_A_D30
DDR_A_D27
DDR_A_D36
DDR_A_D34
DDR_A_DQS4
DDR_A_D38
DDR_A_D35
DDR_A_D32
DDR_A_D33
DDR_A_D37
DDR_A_D39
DDR_A_DM4
DDR_A_MA13
DDR_D63
DDR_D59
DDR_A_MA13
DDR_D4
DDR_D1
DDR_D5
DDR_D2
DDR_A_D60
DDR_A_DQS7
DDR_A_D59
DDR_A_D62
DDR_A_D56
DDR_A_D61
DDR_A_D51
DDR_A_D50
DDR_A_D57
DDR_A_DQS6
DDR_A_D55
DDR_A_DQS5
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D48
DDR_A_D42
DDR_A_D47
DDR_A_D53
DDR_A_D49
DDR_A_D46
DDR_A_D52
DDR_A_D41
DDR_A_D40
DDR_A_D54
DDR_A_DM5
DDR_A_DM7
DDR_A_DM6
DDR_A_D63
DDR_A_D58
DDR_DM0
DDR_D3
DDR_DQS0
DDR_D0
DDR_D7
DDR_D6
DDR_D13
DDR_D11
DDR_D10
DDR_D8
DDR_D9
DDR_DM1
DDR_D12
DDR_DQS1
DDR_D14
DDR_D15
DDR_D20
DDR_D21
DDR_D16
DDR_D17
DDR_DQS2
DDR_D18
DDR_DM2
DDR_D22
DDR_D23
DDR_D19
DDR_D28
DDR_D24
DDR_D29
DDR_DQS3
DDR_D25
DDR_DM3
DDR_D31
DDR_D26
DDR_D30
DDR_D27
DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38
DDR_D39
DDR_DQS4
DDR_DM4
DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5
DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6
DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7
DDR_A_D4
DDR_D[0..63]
DDR_DM[0..7]
DDR_DQS[0..7]
DDR_D58
DDR_A_D[0..63]
<9>
DDR_A_DM[0..7]
<9>
DDR_A_DQS[0..7]
<9>
DDR_D[0..63] <14>
DDR_DM[0..7] <14>
DDR_DQS[0..7] <14>
DDR_A_MA[0..13]
<9>
DDR_CLK0
<8>
DDR_CLK0#
<8>
DDR_CKE1
<8>
DDR_SCS#0
<8>
DDR_A_BS#0
<9>
DDR_A_WE#
<9>
CK_SDATA
<14,18>
CK_SCLK
<14,18>
DDR_CLK1 <8>
DDR_CLK1# <8>
DDR_SCS#1 <8>
DDR_A_CAS# <9>
DDR_A_RAS# <9>
DDR_A_BS#1 <9>
DDR_CKE0 <8>
+1.25VS
+2.5V
+3VS
+SDREF
+SDREF_DIMM
+2.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
B
13 52
Friday, March 11, 2005
2005/03/01 2006/03/01
R679 10_0402_5%
1 2
R668 10_0402_5%
1 2
R252 10_0402_5%
1 2
R263 10_0402_5%
1 2
R234 10_0402_5%
1 2
R247 10_0402_5%
1 2
R240 10_0402_5%
1 2
R678 56_0402_5%
1 2
R647 10_0402_5%
1 2
R655 10_0402_5%
1 2
R270 10_0402_5%
1 2
R664 10_0402_5%
1 2
R666 10_0402_5%
1 2
R264 10_0402_5%
1 2
R269 10_0402_5%
1 2
R649 10_0402_5%
1 2
R249 10_0402_5%
1 2
R670 10_0402_5%
1 2
R659 10_0402_5%
1 2
R665 10_0402_5%
1 2
R268 10_0402_5%
1 2
R661 10_0402_5%
1 2
JDIMM2
TYCO_1612560-1
VREF
1
VSS
3
DQ0
5
DQ1
7
VDD
9
DQS0
11
DQ2
13
VSS
15
DQ3
17
DQ8
19
VDD
21
DQ9
23
DQS1
25
VSS
27
DQ10
29
DQ11
31
VDD
33
CK0
35
CK0#
37
VSS
39
DQ16
41
DQ17
43
VDD
45
DQS2
47
DQ18
49
VSS
51
DQ19
53
DQ24
55
VDD
57
DQ25
59
DQS3
61
VSS
63
DQ26
65
DQ27
67
VDD
69
CB0
71
CB1
73
VSS
75
DQS8
77
CB2
79
VDD
81
CB3
83
DU
85
VSS
87
CK2
89
CK2#
91
VDD
93
CKE1
95
DU
97
A12
99
A9
101
VSS
103
A7
105
A5
107
A3
109
A1
111
VDD
113
A10/AP
115
BA0
117
WE#
119
S0#
121
DU/A13
123
VSS
125
DQ32
127
DQ33
129
VDD
131
DQS4
133
DQ34
135
VSS
137
DQ35
139
DQ40
141
VDD
143
VREF 2
VSS 4
DQ4
6
DQ5
8
VDD
10
DM0
12
DQ6
14
VSS
16
DQ7
18
DQ12
20
VDD
22
DQ13
24
DM1
26
VSS
28
DQ14
30
DQ15
32
VDD 34
VDD 36
VSS 38
VSS 40
DQ20 42
DQ21 44
VDD 46
DM2 48
DQ22 50
VSS 52
DQ23 54
DQ28 56
VDD 58
DQ29 60
DM3 62
VSS 64
DQ30 66
DQ31 68
VDD 70
CB4 72
CB5 74
VSS 76
DM8 78
CB6 80
VDD 82
CB7 84
DU/RESET#
86
VSS
88
VSS
90
VDD
92
VDD
94
CKE0
96
DU
98
A11
100
A8
102
VSS
104
A6
106
A4
108
A2
110
A0
112
VDD
114
BA1
116
RAS#
118
CAS#
120
S1#
122
DU
124
VSS
126
DQ36
128
DQ37
130
VDD
132
DM4
134
DQ38
136
VSS
138
DQ39
140
DQ44
142
VDD
144
DQ41
145
DQS5
147
VSS
149
DQ42
151
DQ43
153
VDD
155
VDD
157
VSS
159
VSS
161
DQ48
163
DQ49
165
VDD
167
DQS6
169
DQ50
171
VSS
173
DQ51
175
DQ56
177
VDD
179
DQ57
181
DQS7
183
VSS
185
DQ58
187
DQ59
189
VDD
191
SDA
193
SCL
195
VDD_SPD
197
VDD_ID
199
DQ45
146
DM5
148
VSS
150
DQ46
152
DQ47
154
VDD
156
CK1#
158
CK1
160
VSS
162
DQ52
164
DQ53
166
VDD
168
DM6
170
DQ54
172
VSS
174
DQ55
176
DQ60
178
VDD
180
DQ61
182
DM7
184
VSS
186
DQ62
188
DQ63
190
VDD
192
SA0
194
SA1
196
SA2 198
DU 200
R277 56_0402_5%
1 2
C237
0.1U_0402_16V4Z
1
2
R265 10_0402_5%
1 2
R256 10_0402_5%
1 2
R288 56_0402_5%
1 2
R691 10_0402_5%
1 2
R674 56_0402_5%
1 2
R235 10_0402_5%
1 2
R251 10_0402_5%
1 2
R652 10_0402_5%
1 2
R683 10_0402_5%
1 2
R693 10_0402_5%
1 2
R676 56_0402_5%
1 2
R287 56_0402_5%
1 2
R236 10_0402_5%
1 2
R266 10_0402_5%
1 2
R677 56_0402_5%
1 2
R250 10_0402_5%
1 2
R684 10_0402_5%
1 2
R646 10_0402_5%
1 2
R245 10_0402_5%
1 2
R271 10_0402_5%
1 2
R257 10_0402_5%
1 2
R282 56_0402_5%
1 2
R648 10_0402_5%
1 2
R283 56_0402_5%
1 2
R237 10_0402_5%
1 2
R660 10_0402_5%
1 2
R242 10_0402_5%
1 2
R286 56_0402_5%
1 2
R260 10_0402_5%
1 2
R656 10_0402_5%
1 2
R657 10_0402_5%
1 2
R241 10_0402_5%
1 2
R685 10_0402_5%
1 2
R294 56_0402_5%
1 2
R688 10_0402_5%
1 2
R280 56_0402_5%
1 2
R681 10_0402_5%
1 2
R253 10_0402_5%
1 2
R650 10_0402_5%
1 2
R672 56_0402_5%
1 2
R244 10_0402_5%
1 2
R238 10_0402_5%
1 2
R673 56_0402_5%
1 2
R279 56_0402_5%
1 2
R682 10_0402_5%
1 2
R690 10_0402_5%
1 2
R267 10_0402_5%
1 2
R243 10_0402_5%
1 2
R274 10_0402_5%
1 2
R692 10_0402_5%
1 2
R254 10_0402_5%
1 2
R651 10_0402_5%
1 2
R675 56_0402_5%
1 2
R680 10_0402_5%
1 2
R275 56_0402_5%
1 2
R248 10_0402_5%
1 2
R246 10_0402_5%
1 2
R255 10_0402_5%
1 2
R273 10_0402_5%
1 2
R663 10_0402_5%
1 2
R276 56_0402_5%
1 2
R653 10_0402_5%
1 2
R278 56_0402_5%
1 2
R233 10_0402_5%
1 2
R296 56_0402_5%
1 2
R295 56_0402_5%
1 2
R239 10_0402_5%
1 2
R281 56_0402_5%
1 2
R261 10_0402_5%
1 2
R272 10_0402_5%
1 2
R654 10_0402_5%
1 2
R658 10_0402_5%
1 2
R662 10_0402_5%
1 2
R687 10_0402_5%
1 2
R686 10_0402_5%
1 2
R689 10_0402_5%
1 2
R669 10_0402_5%
1 2
R262 10_0402_5%
1 2
R227
0_0402_5%
1
2
R293 56_0402_5%
1 2
R667 10_0402_5%
1 2

14. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CK_SCLK
DDR_SCS#2
DDR_CKE3
DDR_SCS#3
DDR_CKE2
DDR_B_MA5
DDR_B_MA3
DDR_B_MA7
DDR_B_MA0
DDR_B_MA2
DDR_B_MA1
DDR_B_MA12
DDR_B_MA9
DDR_B_MA6
DDR_B_MA4
DDR_B_MA10
DDR_B_MA8
DDR_B_MA11
CK_SDATA
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_B_BS#0
DDR_B_BS#1
DDR_B_MA[0..13]
DDR_B_BS#1
DDR_B_MA9
DDR_B_MA12
DDR_B_MA11
DDR_B_MA0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA2
DDR_B_MA5
DDR_B_CAS#
DDR_B_RAS#
DDR_B_BS#0
DDR_B_WE#
DDR_B_MA7
DDR_B_MA4
DDR_B_MA8
DDR_B_MA3
DDR_B_MA6
DDR_SCS#2
DDR_SCS#3
DDR_CKE2
DDR_CKE3
DDR_B_MA13
DDR_B_MA13
DDR_D[0..63]
DDR_DM[0..7]
DDR_DQS[0..7]
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_D6
DDR_D4
DDR_D2
DDR_D0
DDR_D10
DDR_D8
DDR_D12
DDR_D14
DDR_D22
DDR_D18
DDR_D20
DDR_D24
DDR_D26
DDR_D16
DDR_D28
DDR_D30
DDR_D39
DDR_D35
DDR_D41
DDR_D33
DDR_D42
DDR_D46
DDR_D36
DDR_D45
DDR_D54
DDR_D53
DDR_D57
DDR_D58
DDR_D50
DDR_D60
DDR_D52
DDR_D59
DDR_DM3
DDR_DM0
DDR_DM1
DDR_DM6
DDR_DM7
DDR_DM2
DDR_DM4
DDR_DM5
DDR_D11
DDR_D5
DDR_D7
DDR_D1
DDR_D3
DDR_D9
DDR_D23
DDR_D19
DDR_D15
DDR_D13
DDR_D21
DDR_D27
DDR_D29
DDR_D17
DDR_D31
DDR_D25
DDR_D34
DDR_D32
DDR_D37
DDR_D47
DDR_D38
DDR_D43
DDR_D40
DDR_D44
DDR_D51
DDR_D55
DDR_D63
DDR_D49
DDR_D48
DDR_D62
DDR_D61
DDR_D56
DDR_D4
DDR_D1
DDR_D5
DDR_D2
DDR_DM0
DDR_D3
DDR_DQS0
DDR_D0
DDR_D7
DDR_D6
DDR_D13
DDR_D11
DDR_D10
DDR_D8
DDR_D9
DDR_DM1
DDR_D12
DDR_DQS1
DDR_D14
DDR_D15
DDR_D20
DDR_D21
DDR_D16
DDR_D17
DDR_DQS2
DDR_D18
DDR_DM2
DDR_D22
DDR_D23
DDR_D19
DDR_D28
DDR_D24
DDR_D29
DDR_DQS3
DDR_D25
DDR_DM3
DDR_D31
DDR_D26
DDR_D30
DDR_D27
DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38
DDR_D39
DDR_DQS4
DDR_DM4
DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5
DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6
DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7
DDR_D[0..63] <13>
DDR_DM[0..7] <13>
DDR_DQS[0..7] <13>
DDR_B_MA[0..13]
<9>
DDR_CLK3
<8>
DDR_CLK3#
<8>
DDR_CKE3
<8>
DDR_SCS#2
<8>
DDR_B_BS#0
<9>
DDR_B_WE#
<9>
CK_SDATA
<13,18>
CK_SCLK
<13,18>
DDR_CLK4# <8>
DDR_CLK4 <8>
DDR_SCS#3 <8>
DDR_CKE2 <8>
DDR_B_BS#1 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
+1.25VS
+2.5V
+3VS
+2.5V
+SDREF_DIMM
+1.25VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
B
14 52
Friday, March 11, 2005
2005/03/01 2006/03/01
R591 56_0402_5%
1 2
R573 56_0402_5%
1 2
R206 56_0402_5%
1 2
R216 56_0402_5%
1 2
R582 56_0402_5%
1 2
R211 56_0402_5%
1 2
R571 56_0402_5%
1 2
R170 56_0402_5%
1 2
R186 56_0402_5%
1 2
R611 56_0402_5%
1 2
R205 56_0402_5%
1 2
R208 56_0402_5%
1 2
R580 56_0402_5%
1 2
R577 56_0402_5%
1 2
R184 56_0402_5%
1 2
R572 56_0402_5%
1 2
R593 56_0402_5%
1 2
R180 56_0402_5%
1 2
R606 56_0402_5%
1 2
R178 56_0402_5%
1 2
R213 56_0402_5%
1 2
R615 56_0402_5%
1 2
R576 56_0402_5%
1 2
R570 56_0402_5%
1 2
R587 56_0402_5%
1 2
R599 56_0402_5%
1 2
R201 56_0402_5%
1 2
R167 56_0402_5%
1 2
R565 56_0402_5%
1 2
R189 56_0402_5%
1 2
R602 56_0402_5%
1 2
R601 56_0402_5%
1 2
R609 56_0402_5%
1 2
R600 56_0402_5%
1 2
R586 56_0402_5%
1 2
R575 56_0402_5%
1 2
R612 56_0402_5%
1 2
R181 56_0402_5%
1 2
R212 56_0402_5%
1 2
R173 56_0402_5%
1 2
C188
0.1U_0402_16V4Z
1
2
R566 56_0402_5%
1 2
R168 56_0402_5%
1 2
R198 56_0402_5%
1 2
R182 56_0402_5%
1 2
R597 56_0402_5%
1 2
R603 56_0402_5%
1 2
R568 56_0402_5%
1 2
R574 56_0402_5%
1 2
R193 56_0402_5%
1 2
R195 56_0402_5%
1 2
R177 56_0402_5%
1 2
R605 56_0402_5%
1 2
R608 56_0402_5%
1 2
R191 56_0402_5%
1 2
R190 56_0402_5%
1 2
R175 56_0402_5%
1 2
R187 56_0402_5%
1 2
R578 56_0402_5%
1 2
R200 56_0402_5%
1 2
R610 56_0402_5%
1 2
R203 56_0402_5%
1 2
R595 56_0402_5%
1 2
R583 56_0402_5%
1 2
R592 56_0402_5%
1 2
R581 56_0402_5%
1 2
R204 56_0402_5%
1 2
R563 56_0402_5%
1 2
R171 56_0402_5%
1 2
R176 56_0402_5%
1 2
R562 56_0402_5%
1 2
R166 56_0402_5%
1 2
R209 56_0402_5%
1 2
R585 56_0402_5%
1 2
R614 56_0402_5%
1 2
R185 56_0402_5%
1 2
R199 56_0402_5%
1 2
R594 56_0402_5%
1 2
R179 56_0402_5%
1 2
JDIMM1
KLINK_5763-2-111
VREF
1
VSS
3
DQ0
5
DQ1
7
VDD
9
DQS0
11
DQ2
13
VSS
15
DQ3
17
DQ8
19
VDD
21
DQ9
23
DQS1
25
VSS
27
DQ10
29
DQ11
31
VDD
33
CK0
35
CK0#
37
VSS
39
DQ16
41
DQ17
43
VDD
45
DQS2
47
DQ18
49
VSS
51
DQ19
53
DQ24
55
VDD
57
DQ25
59
DQS3
61
VSS
63
DQ26
65
DQ27
67
VDD
69
CB0
71
CB1
73
VSS
75
DQS8
77
CB2
79
VDD
81
CB3
83
DU
85
VSS
87
CK2
89
CK2#
91
VDD
93
CKE1
95
DU/A13
97
A12
99
A9
101
VSS
103
A7
105
A5
107
A3
109
A1
111
VDD
113
A10/AP
115
BA0
117
WE#
119
S0#
121
DU
123
VSS
125
DQ32
127
DQ33
129
VDD
131
DQS4
133
DQ34
135
VSS
137
DQ35
139
DQ40
141
VDD
143
VREF 2
VSS 4
DQ4 6
DQ5 8
VDD 10
DM0 12
DQ6 14
VSS 16
DQ7 18
DQ12
20
VDD
22
DQ13
24
DM1
26
VSS
28
DQ14
30
DQ15
32
VDD
34
VDD
36
VSS
38
VSS
40
DQ20
42
DQ21 44
VDD 46
DM2 48
DQ22 50
VSS 52
DQ23 54
DQ28 56
VDD 58
DQ29 60
DM3 62
VSS 64
DQ30 66
DQ31 68
VDD 70
CB4 72
CB5 74
VSS 76
DM8 78
CB6 80
VDD 82
CB7 84
DU/RESET# 86
VSS 88
VSS 90
VDD 92
VDD 94
CKE0 96
DU/BA2 98
A11
100
A8
102
VSS
104
A6
106
A4
108
A2
110
A0
112
VDD
114
BA1
116
RAS#
118
CAS#
120
S1#
122
DU
124
VSS
126
DQ36
128
DQ37
130
VDD
132
DM4
134
DQ38
136
VSS
138
DQ39
140
DQ44
142
VDD
144
DQ41
145
DQS5
147
VSS
149
DQ42
151
DQ43
153
VDD
155
VDD
157
VSS
159
VSS
161
DQ48
163
DQ49
165
VDD
167
DQS6
169
DQ50
171
VSS
173
DQ51
175
DQ56
177
VDD
179
DQ57
181
DQS7
183
VSS
185
DQ58
187
DQ59
189
VDD
191
SDA
193
SCL
195
VDD_SPD
197
VDD_ID
199
DQ45
146
DM5
148
VSS
150
DQ46
152
DQ47
154
VDD
156
CK1#
158
CK1
160
VSS
162
DQ52
164
DQ53
166
VDD
168
DM6
170
DQ54
172
VSS
174
DQ55
176
DQ60
178
VDD
180
DQ61
182
DM7
184
VSS
186
DQ62
188
DQ63
190
VDD
192
SA0
194
SA1
196
SA2
198
DU
200
R613 56_0402_5%
1 2
R192 56_0402_5%
1 2
R207 56_0402_5%
1 2
R188 56_0402_5%
1 2
R567 56_0402_5%
1 2
R607 56_0402_5%
1 2
R196 56_0402_5%
1 2
R194 56_0402_5%
1 2
R172 56_0402_5%
1 2
R564 56_0402_5%
1 2
R165 56_0402_5%
1 2
R596 56_0402_5%
1 2
R197 56_0402_5%
1 2
R569 56_0402_5%
1 2
R604 56_0402_5%
1 2
R169 56_0402_5%
1 2
R210 56_0402_5%
1 2
R174 56_0402_5%
1 2
R183 56_0402_5%
1 2
R215 56_0402_5%
1 2
R598 56_0402_5%
1 2
R584 56_0402_5%
1 2
R214 56_0402_5%
1 2
R579 56_0402_5%
1 2
R202 56_0402_5%
1 2

15. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+2.5V
+2.5V +2.5V
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
15 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Layout note :
Distribute as close as possible
to DDR-SODIMM.
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
C218
0.1U_0402_16V4Z
1
2
C263
0.1U_0402_16V4Z
1
2
C583
0.1U_0402_16V4Z
1
2
C189
0.1U_0402_16V4Z
1
2
C587
0.1U_0402_16V4Z
1
2
C246
0.1U_0402_16V4Z
1
2
C586
0.1U_0402_16V4Z
1
2
C544
0.1U_0402_16V4Z
1
2
C652
0.1U_0402_16V4Z
1
2
C215
0.1U_0402_16V4Z
1
2
C529
0.1U_0402_16V4Z
1
2
C647
0.1U_0402_16V4Z
1
2
C244
0.1U_0402_16V4Z
1
2
C242
0.1U_0402_16V4Z
1
2
C254
0.1U_0402_16V4Z
1
2
C654
0.1U_0402_16V4Z
1
2
C217
0.1U_0402_16V4Z
1
2
C216
0.1U_0402_16V4Z
1
2
C243
0.1U_0402_16V4Z
1
2
C651
0.1U_0402_16V4Z
1
2
C202
0.1U_0402_16V4Z
1
2
+
C163
150U_D2_6.3VM
1
2
C200
0.1U_0402_16V4Z
1
2
C581
0.1U_0402_16V4Z
1
2
C247
0.1U_0402_16V4Z
1
2
C228
0.1U_0402_16V4Z
1
2
+
C238
150U_D2_6.3VM
1
2
C249
0.1U_0402_16V4Z
1
2
C250
0.1U_0402_16V4Z
1
2
C582
0.1U_0402_16V4Z
1
2
C536
0.1U_0402_16V4Z
1
2
C648
0.1U_0402_16V4Z
1
2
C252
0.1U_0402_16V4Z
1
2
C191
0.1U_0402_16V4Z
1
2
C585
0.1U_0402_16V4Z
1
2
C576
0.1U_0402_16V4Z
1
2
C255
0.1U_0402_16V4Z
1
2
C650
0.1U_0402_16V4Z
1
2
C251
0.1U_0402_16V4Z
1
2
C590
0.1U_0402_16V4Z
1
2
C575
0.1U_0402_16V4Z
1
2
C588
0.1U_0402_16V4Z
1
2
C248
0.1U_0402_16V4Z
1
2
C531
0.1U_0402_16V4Z
1
2
C649
0.1U_0402_16V4Z
1
2
C530
0.1U_0402_16V4Z
1
2
C227
0.1U_0402_16V4Z
1
2
C535
0.1U_0402_16V4Z
1
2
C580
0.1U_0402_16V4Z
1
2
C584
0.1U_0402_16V4Z
1
2
C193
0.1U_0402_16V4Z
1
2
C266
0.1U_0402_16V4Z
1
2
C267
0.1U_0402_16V4Z
1
2
C208
0.1U_0402_16V4Z
1
2
C655
0.1U_0402_16V4Z
1
2
C579
0.1U_0402_16V4Z
1
2
C214
0.1U_0402_16V4Z
1
2
C245
0.1U_0402_16V4Z
1
2
C256
0.1U_0402_16V4Z
1
2
C230
0.1U_0402_16V4Z
1
2
C589
0.1U_0402_16V4Z
1
2
C262
0.1U_0402_16V4Z
1
2
C201
0.1U_0402_16V4Z
1
2
C229
0.1U_0402_16V4Z
1
2
C653
0.1U_0402_16V4Z
1
2
C646
0.1U_0402_16V4Z
1
2
C190
0.1U_0402_16V4Z
1
2
C253
0.1U_0402_16V4Z
1
2
C578
0.1U_0402_16V4Z
1
2

16. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
B+P B+I
B+P
VGA_GRN
VGA_RED
VGA_BLU
VSYNC_VGA
CLK_PCIE_VGA#
HSYNCVGA
PEG_RXP0
PEG_RXN0
PEG_A_TXN_4
PEG_TXN4
PEG_A_TXP_3
PEG_A_TXP_4
PEG_A_TXN_3
PEG_TXN3
PEG_TXP4
PEG_TXN5
PEG_TXP5
PEG_TXP3
PEG_A_TXN_6
PEG_A_TXP_7
PEG_A_TXP_6
PEG_A_TXN_7
PEG_TXP7
PEG_TXN7
PEG_TXN6
PEG_TXP6
PEG_TXP14
PEG_A_TXP_11
PEG_A_TXN_11
PEG_TXN14
PEG_A_TXP_14
PEG_A_TXP_13
PEG_A_TXN_14
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXP12
PEG_TXN10
PEG_TXN12
PEG_A_TXP_0
PEG_A_TXN_0
PEG_A_TXN_2
PEG_A_TXP_2
PEG_TXN2
PEG_TXN0
PEG_TXP2
PEG_TXP0
PEG_TXP15
PEG_TXN15 PEG_A_TXN_15
PEG_A_TXP_15
PEG_TXN1
PEG_TXP1
PEG_A_TXN_1
PEG_A_TXP_1
PEG_A_TXP_5
PEG_A_TXN_5
PEG_A_TXN_8
PEG_TXN8
PEG_A_TXP_8
PEG_TXP8
PEG_A_TXN_9
PEG_TXP9 PEG_A_TXP_9
PEG_TXN9
PEG_A_TXP_10
PEG_A_TXN_10
PEG_A_TXP_12
PEG_A_TXN_12
PEG_RXN6
PEG_RXP6
PEG_RXN9
PEG_RXP9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP14
PEG_RXN14
PEG_RXP1
PEG_RXN1
PEG_RXN2
PEG_RXP2
PEG_RXP13
PEG_RXN13
PEG_RXN3
PEG_RXP3
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXN4
PEG_RXP4
PEG_RXN5
PEG_RXP5
PEG_RXN10
PEG_RXP10
PEG_RXP11
PEG_RXN14
PEG_RXN15
PEG_RXP15
PEG_RXP0
PEG_RXP13
PEG_RXP4
PEG_RXN[0..15]
PEG_RXN5
PEG_RXN0
PEG_RXP6
PEG_RXP5
PEG_RXP2
PEG_RXP3
PEG_RXN3
PEG_RXP1
PEG_RXN12
PEG_RXN9
PEG_RXN13
PEG_RXN4
PEG_RXP15
PEG_RXN6
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN11
PEG_RXN1
PEG_RXN7
PEG_RXN2
PEG_RXP14
PEG_RXP7
PEG_RXN10
PEG_RXP10
PEG_RXP12
PEG_RXP[0..15]
PEG_RXN15
PEG_TXN5
PEG_TXN13
PEG_TXN10
PEG_TXN4
PEG_TXN9
PEG_TXP0
PEG_TXP6
PEG_TXP11
PEG_TXP5
PEG_TXP[0..15]
PEG_TXN2
PEG_TXP8
PEG_TXN1
PEG_TXP3
PEG_TXN12
PEG_TXP4
PEG_TXN14
PEG_TXP13
PEG_TXP2
PEG_TXP1
PEG_TXN13
PEG_TXN8
PEG_TXN15
PEG_TXP14
PEG_TXP15
PEG_TXP9
PEG_TXN3
PEG_A_TXN_13
PEG_TXN0
PEG_TXN11
PEG_TXN[0..15]
PEG_TXP12
PEG_TXP10
PEG_TXN7
PEG_TXN6
PEG_TXP7
PEG_TXP13
INVPWR_B+++
DISPLAYOFF#
LCDP_CLK
LCDP_DAT
LCDP_CLK
LCDP_DAT
CLK_PCIE_VGA
SUSP
RUNPWROK
PLTRST_VGA#
THERMATRIP_VGA#
SMBDAT_VGA
SMBCLK_VGA
SMB_EC_CK2
SMB_EC_DA2
LVDS_B0+
LVDS_B2-
LVDS_B0-
LVDS_B2+
LVDS_BC+
LVDS_BC-
LVDS_A2+
LVDS_A2-
LVDS_A0-
LVDS_AC+
LVDS_AC-
LVDS_A1-
LVDS_A1+
LVDS_A0+
LVDS_B1-
LVDS_B1+
PWM
DISPLAYOFF#
PWM
BK_EN
<10>
BKOFF#
<32>
BIA
<10,32>
INVT_PWM
<32>
RUNPWROK
PLTRST_VGA# <19,21>
THERMATRIP_VGA# <32>
SUSP <37,43,44>
CLK_PCIE_VGA# <18>
CLK_PCIE_VGA <18>
DAC_BRIG <32>
BKOFF# <32>
INVT_PWM <32>
PEG_TXP[0..15] <10>
PEG_RXN[0..15] <10> PEG_TXN[0..15]
<10>
PEG_RXP[0..15] <10>
LCD_CLK
<10>
LCD_DAT
<10>
EN_LCDVDD
<10>
DAC_BRIG <32>
LVDS_A0+
<10>
LVDS_A0-
<10>
LVDS_A1+
<10>
LVDS_A1-
<10>
LVDS_A2-
<10>
LVDS_A2+
<10>
LVDS_AC-
<10>
LVDS_AC+
<10>
LVDS_B0-
<10>
LVDS_B0+
<10>
LVDS_B2-
<10>
LVDS_B2+
<10>
LVDS_B1-
<10>
LVDS_B1+
<10>
LVDS_BC-
<10>
LVDS_BC+
<10>
SUSP#
<24,32,33,37,42>
SMB_EC_CK2
<32,34>
SMB_EC_DA2
<32,34>
SMBDAT_VGA
<17>
C/R_VGA
<17>
COMP/B_VGA
<17>
Y/G_VGA
<17>
VSYNC_VGA
<17>
HSYNC_VGA
<17>
VGA_BLU
<17>
VGA_GRN
<17>
VGA_RED
<17>
SMBCLK_VGA
<17>
+LCDVDD
+12VALW +LCDVDD +3VS
INVPWR_B+
+5VS
+3VS
+12VALW
+LCDVDD
INVPWR_B+
+5VALW
+2.5VS
+3VS
+5VS
+3VS
+5VS
+3VS
+2.5V
+3VS
B+ B+I
B+I
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
16 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Inverter
LCD EEPROM
Modify for 1.8vs move to VGA BD
FBM-201209-121LMA40T
C309
0.047U_0402_16V4Z
1
2
C54 0.1U_0402_16V4Z
2@ 1 2
C88 0.1U_0402_16V4Z
2@ 1 2
C66 0.1U_0402_16V4Z
2@ 1 2
C83 0.1U_0402_16V4Z
2@ 1 2
C51 0.1U_0402_16V4Z
2@ 1 2
JVGA1
FOX_QTS0140A-3021
2@
1 1
3 3
5 5
7 7
9 9
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
57 57
59 59
61 61
63 63
65 65
67 67
69 69
71 71
73 73
75 75
77 77
79 79
81 81
83 83
85 85
87 87
89 89
91 91
93 93
95 95
97 97
99 99
101 101
103 103
105 105
107 107
109 109
111 111
113 113
115 115
117 117
119 119
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
121 121
122
122
123 123
124
124
125 125
127 127
129 129
131 131
133 133
135 135
137 137
139 139
126
126
128
128
130
130
132
132
134
134
136
136
138
138
140
140
C48 0.1U_0402_16V4Z
2@ 1 2
C39 0.1U_0402_16V4Z
2@ 1 2
C76 0.1U_0402_16V4Z
2@ 1 2
R355
100K_0402_5%
1@
G
D
S
Q25
2N7002_SOT23
1@
2
1 3
C61 0.1U_0402_16V4Z
2@ 1 2
C310
0.047U_0402_16V4Z
1
2
G
D
S
Q22
2N7002_SOT23
1@
2
1
3
C82 0.1U_0402_16V4Z
2@ 1 2
C56 0.1U_0402_16V4Z
2@ 1 2
C311
0.047U_0402_16V4Z
1
2
C307
0.1U_0603_50V4Z
2@
1
2
C314
0.1U_0603_50V4Z
2@
1
2
C318
0.1U_0402_16V4Z
1@
1
2
C27
0.1U_0603_50V4Z C23
0.1U_0603_50V4Z
1@
C323
0.1U_0402_16V4Z
1@
R722
KC FBM-L11-201209-221LMAT_0805
1@
1 2
R4
0_0402_5%
1@
1 2
JLVDS1
ACES_88328-4000
1@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND 41
GND
42
C49 0.1U_0402_16V4Z
2@ 1 2
G
D
S
Q20
BSS138_SOT23
1@
2
1
3
C313
0.1U_0603_50V4Z
2@
1
2
C80 0.1U_0402_16V4Z
2@ 1 2
C67 0.1U_0402_16V4Z
2@ 1 2
U1
NC7ST08P5X_SC70-5
1@
A
1
B
2
O 4
P
5
G
3
C71 0.1U_0402_16V4Z
2@ 1 2
R329
FBM-L11-160808-800LMT_0603
2@
1 2
C79 0.1U_0402_16V4Z
2@ 1 2
R344
470_0402_5%
1@
G
D
S
Q23
2N7002_SOT23
1@
2
1
3
R3
0_0402_5%
1 2
C57 0.1U_0402_16V4Z
2@ 1 2
C717
10U_1206_25V6M
1
2
C93 0.1U_0402_16V4Z
2@ 1 2
JVGAP1
ACES_85205-1000
2@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
C44 0.1U_0402_16V4Z
2@ 1 2
C55 0.1U_0402_16V4Z
2@ 1 2
Q1
FDS4435_SO8
1@
3 6
5
7
8
2
4
1
R356
100K_0402_5%
1@
R328
FBM-L11-160808-800LMT_0603
2@
1 2
R336
2.2K_0402_5%
1@
1
2
C94 0.1U_0402_16V4Z
2@ 1 2
C716
0.1U_0603_50V4Z
C97 0.1U_0402_16V4Z
2@ 1 2
R335
2.2K_0402_5%
1@
1
2
C87 0.1U_0402_16V4Z
2@ 1 2
C73 0.1U_0402_16V4Z
2@ 1 2
R7
0_0402_5%
@
1 2
C308
0.1U_0603_50V4Z
2@
1
2
C704
0.1U_0402_16V4Z
2@
1
2
Q24
DTC124EK_SC59
1@
2
1
3
C70 0.1U_0402_16V4Z
2@ 1 2
R357 75K_0402_5%
1@
C320
0.1U_0402_16V4Z
1@
1
2
C72 0.1U_0402_16V4Z
2@ 1 2
C43 0.1U_0402_16V4Z
2@ 1 2
R27
100K_0402_5%
1@
G
D
S
Q21
BSS138_SOT23
1@
2
1
3
U2
NC7SZ14M5X_SOT23-5
@
A
2
G
3
Y 4
P
5
C64 0.1U_0402_16V4Z
2@ 1 2
R354
150K_0402_5%
1@
G
D
S
Q26
SI2302DS_SOT23
1@
2
1
3
L33
FBM-L11-201209-121LMA05T_0805
1 2
C59 0.1U_0402_16V4Z
2@ 1 2
C65 0.1U_0402_16V4Z
2@ 1 2
C705
0.1U_0402_16V4Z
2@
1
2
C321
0.1U_0402_16V4Z
1@
C50 0.1U_0402_16V4Z
2@ 1 2
C77 0.1U_0402_16V4Z
2@ 1 2

17. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SVIDEO_Y
SVIDEO_CVBS
C/R_C
SVIDEO_C
MSEN#
CRTR
CRTG
CRTB
COMP/B_C
Y/G_C
CRT_HSYNC
CRT_VSYNC
CRT_G
CRT_B
CRT_R
C/R
<10>
C/R_VGA
<16>
COMP/B
<10>
COMP/B_VGA
<16>
Y/G
<10>
Y/G_VGA
<16>
VGA_RED
<16>
VGA_GRN
<16>
CRT_RED
<10>
CRT_GRN
<10>
CRT_BLU
<10>
HSYNC_VGA
<16>
HSYNC
<10>
VSYNC_VGA
<16>
VSYNC
<10>
MSEN#
<32>
SMBDAT_VGA <16>
DAT_DDC2 <10>
SMBCLK_VGA <16>
CLK_DDC2 <10>
VGA_BLU
<16>
+3VS
+5VS
+2.5VS
+5VS
+3VS
+5VS
+2.5VS
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
17 52
Friday, March 11, 2005
2005/03/01 2006/03/01
DDC_MONID0
CRT Connector
C3
100P_0402_50V8J
1
2
L5
FBM-11-160808-121-T_0603
1 2
G
D
S
Q19
2N7002_SOT23
2
1 3
R9
75_0603_1%
1
2
C17
82P_0603_50V8J
1
2
L1
FBM-11-160808-121-T_0603
1 2
JTV1
SUYIN_33007SR-07T1-C
1
2
3
4
5
6
7
C8
3.3P_0603_50V8J
1
2
R340 0_0402_5%
2@
1 2
R8
75_0603_1%
1
2
D8
DAN217_SC59
@
2
3
1
R343 0_0402_5%
1@
1 2
R341 0_0402_5%
1@
1 2
R321
2K_0402_5%
1
2
R330
0_0402_5%
1
2
C22
82P_0402_50V8J
1
2
C15
82P_0603_50V8J
1
2
R22 0_0402_5%
2@
1 2
R332
0_0402_5%
1@
1 2
JCRT1
FOX_DZ11A91-L7
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
R23 0_0402_5%
1@
1 2
D12
DAN217_SC59
@
2
3
1
L8
FLM1608081R8K_0603
1 2
L4
FBM-11-160808-121-T_0603
1 2
R26 0_0402_5%
2@
1 2
D11
DAN217_SC59
@
2
3
1
C5
27P_0402_50V8J
1
2
R331
2.7K_0402_5%
1
2
D9
DAN217_SC59
@
2
3
1
U24
SN74AHCT1G125GW_SOT353-5
A
2
Y
4
OE#
1
G
3
P
5
R325
2K_0402_5%
1
2
C303
100P_0402_50V8J
1
2
R15 0_0402_5%
1@
1 2
R326
0_0402_5% 2@
1 2
R333
0_0402_5%
1@
1 2
R334
2.7K_0402_5%
1
2
C4
100P_0402_50V8J
1
2
C21
82P_0402_50V8J
1
2
C9
3.3P_0603_50V8J
1
2
R339
1K_0402_5%
1 2
R18
150_0402_1%
1
2
C304
0.1U_0402_16V4Z
1
2
R342 0_0402_5%
2@
1 2
C14
3.3P_0603_50V8J
@
1
2
D10
DAN217_SC59
@
2
3
1
R322
0_0402_5% 2@
1 2
D7
DAN217_SC59
@
2
3
1
R11 0_0402_5%
1@
1 2
R16 0_0402_5%
2@
1 2
L3
FBM-11-160808-121-T_0603
1 2
L7
FLM1608081R8K_0603
1 2
R12 0_0402_5%
2@
1 2
C302
100P_0402_50V8J
1
2
C12
3.3P_0603_50V8J
@
1
2
R19
150_0402_1%
1
2
C306
0.1U_0402_16V4Z
1
2
L6
FLM1608081R8K_0603
1 2
L2
FBM-11-160808-121-T_0603
1 2
C10
3.3P_0603_50V8J
1
2
U25
SN74AHCT1G125GW_SOT353-5
A
2
Y
4
OE#
1
G
3
P
5
R24 0_0402_5%
2@
1 2
R10
75_0603_1%
1
2
R21 0_0402_5%
1@
1 2
R14 0_0402_5%
2@
1 2
C16
82P_0603_50V8J
1
2
C305
0.1U_0402_16V4Z
1
2
D20
RB751V_SOD323
2
1
R13 0_0402_5%
1@
1 2
C6
27P_0402_50V8J
1
2
R25 0_0402_5%
1@
1 2
R17
150_0402_1%
1
2
C13
3.3P_0603_50V8J
@1
2
C20
82P_0402_50V8J
1
2
G
D
S
Q18
2N7002_SOT23
2
1 3

18. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_SMBCLK
CLK_14M_ICH
CK_SDATA
CLK_14M_SIO
ICH_SMBDATA
CLK_MCH_BCLK
CLK_ITP#
CLK_CPU_BCLK#
CLK_CPU_BCLK
CLK_MCH_BCLK#
CLK_PCIE_ICH#
CLK_PCIE_ICH
PCICLK2
H_STP_CPU#
CK_XTAL_OUT
H_STP_PCI#
PCICLK4
CK_SDATA
CK_SCLK
CLKIREF
CLKREF
PCICLK3
CLKSEL1
CLK_ITP
CLK_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CK_CPU1
CK_CPU1#
CK_CPU2#
CK_CPU2
CK_CPU0
CK_CPU0#
PCICLK5
PCICLKF1
CK_XTAL_IN
CLK_33M_ICH
CLK_33M_MPCI
CLK_33M_LAN
CLK_33M_CBS
CLK_33M_LPCSIO
SRC4#
SRC4
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLKSEL2
CK_VDD_REF
CK_VDD_48
CK_VDD_48
CK_VDD_A
CK_VDD_A CK_VDD_REF
CLKSEL2
CLK_48M_ICH
SRC5#
SCR5
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CK_SCLK
PCICLKF0
CLK_33M_LPCEC
CLK_ITP
SRC1
SRC1# CLK_PCIE_ICH#
CLK_PCIE_ICH
SRC0
SRC0# SSC_DREFCLK#
DREFCLK#
DREFCLK
SSC_DREFCLK
SSC_DREFCLK#
DREFCLK#
DREFCLK
SSC_DREFCLK
CLKSEL1
CLK_14M_CODEC
CLKSEL0
CLKSEL0
ICH_SMBDATA
<21>
ICH_SMBCLK
<21>
CK_SDATA <13,14>
CK_SCLK <13,14>
MCH_CLKSEL0 <8>
MCH_CLKSEL1 <8>
CPU_BSEL0
<6>
CPU_BSEL1
<6>
CLK_48M_ICH
<21>
CLK_14M_CODEC
<29>
CLK_33M_1394
<27>
CLK_33M_CBS
<26>
CLK_33M_LPCSIO
<31>
CLK_33M_MPCI
<28>
CLK_33M_LAN
<24>
CLK_33M_ICH
<19>
CLK_33M_LPCEC
<32>
CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>
CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>
CLK_ITP <5>
CLK_ITP# <5>
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>
CLK_PCIE_ICH <21>
CLK_PCIE_ICH# <21>
SSC_DREFCLK <8>
SSC_DREFCLK# <8>
DREFCLK <8>
DREFCLK# <8>
CLK_14M_ICH <21>
CLK_14M_SIO <31>
H_STP_PCI# <21>
H_STP_CPU# <21,45>
VGATE <8,21,45>
+CK_VDD_MAIN
+VCCP
+3VS
+3VS
+3VS
+CK_VDD_MAIN2
+3VS
+3VS
+3VS
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
18 52
Friday, March 11, 2005
2005/03/01 2006/03/01
3
1
G
Place near each pin
W>40 mil
S
Place near CK410M
2N7002
2
D
Place crystal within
500 mils of CK410
FSC FSB FSA CPU
MHz
SRC
MHz
PCI
MHz
266
133
166
333
400
RESERVED
100 33.3
0
1
Table : ICS 954201 / Cypress CY28411
CLKSEL0 CLKSEL1 CLKSEL2
0 0 1 for Dothan-A 533Mhz
1 0 1 for Dothan-A 400Mhz
33.3
33.3
33.3
33.3
33.3
33.3
100
100
100
100
100
100
100
200
0
0
0
0
0
0
0
0
0
0
0
0
1
1 1
1
1
1
1
1
1
1
*
R509 10K_0402_5%
1 2
C476
33P_0402_50V8J
1
2
R521 33_0402_5%
1 2
R121
10K_0402_5%
1
2
R552 49.9_0402_1%
1 2
R522 49.9_0402_1%
1
2
R513
10K_0402_5%
1
2
R497 33_0402_5%
1
2
R126
1_0603_5%
1 2
R142 33_0402_5%
1@
1 2
R514 33_0402_5%
1 2
R531
10K_0402_5%
@
1
2
R524
10K_0402_5%
@
1
2
R539 33_0402_5%
1 2
R538 33_0402_5%
1@
1 2
R503 12.1_0402_1%
1 2
R486
10K_0402_5%
@
1
2
R542 49.9_0402_1%
1 2
R491 33_0402_5%
1
2
R533
1K_0402_5%
1 2
R555 49.9_0402_1%
1 2
R525 49.9_0402_1%
1@
1 2
R744
10K_0402_5%
1 2
R131 475_0603_1%
1 2
R128
2.2_0603_5%
1 2
R519 49.9_0402_1%
1@
1 2
R548 33_0402_5%
1 2
R119
10K_0402_5%
1
2
R554 33_0402_5%
1 2
R545 49.9_0402_1%
1
2
C487
33P_0402_50V8J
1
2
U31
ICS954206AG
VDD_SRC0
21
VDD_SRC1
28
VDD_SRC2
34
VDD_PCI0
1
VDD_PCI1
7
VDD_48
11
VDD_CPU
42
VDD_REF
48
FSA/USB_48
12
VSS_PCI0
2
FSB/TEST_MODE
16
XTAL_OUT
49
XTAL_IN
50
VSS_SRC
29
VSS_48
13
VSS_CPU
45
PCI2
56
FSC/TEST_SEL
53
SDATA
47
SCLOCK
46
PCIF0/ITP_EN
8
PCIF1
9
IREF
39
SRC5
31
CPU_STOP# 54
CPU1 41
CPU1# 40
CPU_2_ITP/SRC_7
36
SRC5#
30
PCI3
3
PCI4
4
PCI5
5
CPU0# 43
CPU0 44
SRC6
33
SRC6#
32
PCI_STOP# 55
VSS_A 38
VDD_A 37
REF
52
VSS_PCI1
6
VSS_REF
51
CPU_2_ITP/SRC7#
35
SRC4
26
SRC4#
27
SRC3
24
SRC3#
25
SRC2
22
SRC2#
23
SRC1
19
SRC1#
20
SRC0
17
SRC0#
18
DOT96
14
DOT96#
15
VTT_PWRGD#/PD
10
R535 49.9_0402_1%
1
2
X3 14.318MHZ_20P_1BX14318CC1A
1
2
C456
0.1U_0402_16V4Z
1
2
C139
4.7U_0805_6.3V6K
1
2
R508 33_0402_5%
1
2
R145
2.2_0603_5%
1 2
C123
0.047U_0402_16V7K
1
2
R547 49.9_0402_1%
1 2
L24
CHB1608U301_0603
1 2
R526 33_0402_5%
1@
1 2
R558 33_0402_5%
1 2
R550 49.9_0402_1%
1 2
R499 12.1_0402_1%
1 2
C133
0.047U_0402_16V7K
1
2
G
D
S
Q45 2N7002_SOT23
2
1
3
R528 49.9_0402_1%
1
2
C635
0.047U_0402_16V4Z
1
2
R146 49.9_0402_1%
1@
1 2
L25
CHB1608U301_0603
1 2
R501 12.1_0402_1%
1
2
R527 33_0402_5%
1 2
C505
0.047U_0402_16V7K
1
2
R488
1K_0402_5%
1 2
R553 33_0402_5%
1 2
C137
0.047U_0402_16V7K
1
2
R537 49.9_0402_1%
1@
1 2
R742
10K_0402_5%
1
2
C134
4.7U_0805_6.3V6K
1
2
R557 49.9_0402_1%
1 2
G
D
S
Q5
2N7002_SOT23
2
1 3
G
D
S
Q4
2N7002_SOT23
2
1 3
C508
0.047U_0402_16V7K
1
2
R543 33_0402_5%
1 2
R493
33_0402_1%
1
2
C444
10U_0805_10V4Z
1
2
R512
10K_0402_5%
@
1
2
C457
10U_0805_10V4Z
1
2
R506 33_0402_5%
1
2
R502 12.1_0402_1%
1
2
R482
10K_0402_5%
@
1
2
R520 33_0402_5%
1@
1 2
C523
0.047U_0402_16V7K
1
2
R534 33_0402_5%
1 2
R511 33_0402_5%
1
2
R540 49.9_0402_1%
1
2
C479
0.047U_0402_16V7K
1
2
C511
0.047U_0402_16V7K
1
2
R498 33_0402_5%
1
2
R544 33_0402_5%
1 2
R515 49.9_0402_1%
1
2
R549 33_0402_5%
1 2
C466
0.047U_0402_16V7K
1
2

19. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_33M_ICH
PCI_SERR#
PCI_DEVSEL#
PCI_PCIRST#
PCI_C_BE0#
CLK_ICH_TERM
PCI_REQ4#
PCI_PERR#
PCI_GNT1#
PCI_PIRQG#
PCI_PIRQB#
PCI_REQ5#
PCI_STOP#
PCI_C_BE1#
PCI_C_BE3#
PCI_PIRQF#
PCI_PIRQC#
PCI_REQ2#
PCI_PIRQE#
PCI_REQ6#
PCI_FRAME#
PCI_REQ3#
PCI_PLOCK#
PCI_IRDY#
PCI_C_BE2#
PCI_REQ1#
PCI_REQ0#
PCI_PIRQD#
PCI_PIRQA#
PCI_PAR
PCI_GNT3#
PCI_TRDY#
PCI_PIRQH#
PLTRST#
PLTRST#
CLK_33M_ICH
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD7
PCI_AD6
PCI_AD8
PCI_AD9
PCI_AD11
PCI_AD10
PCI_AD14
PCI_AD15
PCI_AD13
PCI_AD12
PCI_AD16
PCI_AD17
PCI_AD19
PCI_AD18
PCI_AD22
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD25
PCI_AD24
PCI_AD28
PCI_AD29
PCI_AD31
PCI_AD30
PCI_AD26
PCI_AD27
PCI_PIRQG#
PCI_PIRQF#
PCI_PIRQE#
PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#
PCI_REQ2#
PCI_REQ5#
PCI_REQ6#
PCI_PCIRST#
PCIRSTB3#
PCI_GNT4#
PCI_PIRQB#
PCI_PIRQD#
PCI_PLOCK#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_FRAME#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQH#
PCI_GNT0#
PCI_GNT2#
ICH_PME#
ICH_PME#
PCIRSTB1#
PCIRSTB2#
PCI_AD[0..31]
<24,26,27,28>
PCI_FRAME#
<24,26,27,28>
PCI_PIRQA#
<26>
PCI_PIRQB#
<26>
PCI_REQ0# <24>
PCI_REQ1# <26>
PCI_REQ2# <27>
PCI_REQ3# <28>
ICH_PME# <24,26,27,28,31,32>
PCI_PIRQE# <27>
PCI_PIRQF# <24>
PCI_PIRQG# <28>
PCI_PIRQH# <28>
PCI_SERR# <24,26,28>
PCI_GNT0# <24>
PCI_GNT1# <26>
PCI_GNT2# <27>
PCI_GNT3# <28>
PLTRST_VGA# <16,21>
PLTRST_SIO# <31>
PLTRST_MCH# <8>
PLTRST# <21>
CLK_33M_ICH <18>
PCIRST# <24,26,27,28,32>
PCI_C_BE0# <24,26,27,28>
PCI_C_BE1# <24,26,27,28>
PCI_C_BE2# <24,26,27,28>
PCI_C_BE3# <24,26,27,28>
PCI_IRDY# <24,26,27,28>
PCI_PAR <24,26,27,28>
PCI_DEVSEL# <24,26,27,28>
PCI_PERR# <24,26,27,28>
PCI_STOP# <24,26,27,28>
PCI_TRDY# <24,26,27,28>
+3VS
+3V
+3VS
+3VS
+3VS
+3VS
+3V
+3V
+3V
CHGRTC
+RTCVCC
+3VALW
+3V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
19 52
Friday, March 11, 2005
2005/03/01 2006/03/01
R86
8.2K_0402_5% 1 2
R443
33_0402_5%
1 2
R84
8.2K_0402_5% 1 2
R447
8.2K_0402_5% 1 2
R757
10K_0402_5%
@
1
2
U29B
74VHC08MTC_TSSOP14
@
A
4
B
5
O
6
P
14
G
7
C350
0.1U_0402_16V4Z
1
2
R478
8.2K_0402_5% 1 2
U29A
74VHC08MTC_TSSOP14
@
A
1
B
2
O
3
P
14
G
7
R774
0_0402_5%
1 2
R389
33_0402_5%
1 2
RP4
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R758
0_0402_5%
1 2
R775
0_0402_5%
1 2
R448
8.2K_0402_5% 1 2
U29C
74VHC08MTC_TSSOP14
@
A
10
B
9
O
8
P
14
G
7
D16
BAS40-04_SOT23
1
2
3
G
D
S
Q46
2N7002_SOT23
@
2
1
3
R72
8.2K_0402_5% 1 2
R445
33_0402_5%
1 2
RP5
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R724 10K_0402_1%
1 2
R70
8.2K_0402_5% 1 2
R480
8.2K_0402_5% 1 2
R472
10_0402_5%
@
1
2
Interrupt I/F
PCI
RESERVED
U7B
ICH6_BGA609
AD[0]
E2
AD[1]
E5
AD[2]
C2
AD[3]
F5
AD[4]
F3
AD[5]
E9
AD[6]
F2
AD[7]
D6
AD[8]
E6
AD[9]
D3
AD[10]
A2
AD[11]
D2
AD[12]
D5
AD[13]
H3
AD[14]
B4
AD[15]
J5
AD[16]
K2
AD[17]
K5
AD[18]
D4
AD[19]
L6
AD[20]
G3
AD[21]
H4
AD[22]
H2
AD[23]
H5
AD[24]
B3
AD[25]
M6
AD[26]
B2
AD[27]
K6
AD[28]
K3
AD[29]
A5
AD[30]
L1
AD[31]
K4
FRAME#
J3
REQ[0]# L5
GNT[0]# C1
REQ[1]# B5
GNT[1]#
B6
REQ[2]#
M5
GNT[2]#
F1
REQ[3]#
B8
GNT[3]#
C8
REQ[4]#/GPI[40]
F7
GNT[4]#/GPO[48]
E7
REQ[5]#/GPI[1]
E8
GNT[5]#/GPO[17]
F6
REQ[6]#/GPI[0]
B7
TRDY# J2
STOP# J1
PLTRST# R5
PCICLK G6
PME# P6
PIRQ[E]#/GPI[2] D9
PIRQ[F]#/GPI[3] C7
PIRQ[G]#GPI[4] C6
PIRQ[H]#/GPI[5] M3
GNT[6]#/GPO[16]
D8
C/BE[0]#
J6
C/BE[1]#
H6
C/BE[2]# G4
C/BE[3]# G2
IRDY# A3
PAR E1
PCIRST# R2
DEVSEL# C3
PERR# E3
PLOCK# C5
SERR# G5
PIRQ[C]#
M1
SATA[1]TXP/RSVD[4]
AG4
PIRQ[A]#
N2
SATA[3]RXN/RSVD[5]
AC9
SATA[1]RXP/RSVD[2]
AD5
SATA[1]TXN/RSVD[3]
AF4
PIRQ[B]#
L2
PIRQ[D]#
L3
SATA[1]RXN/RSVD[1]
AC5
SATA[3]RXP/RSVD[6]
AD9
SATA[3]TXN/RSVD[7]
AF8
SATA[3]TXP/RSVD[8]
AG8
TP[3]/RSVD[9]
U3
R475
8.2K_0402_5% 1 2
RP3
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C410
8.2P_0402_50V8J~D
@
1
2
R88
8.2K_0402_5% 1 2
R446
33_0402_5%
1 2
BATT1
ML1220T13RE
1
2
U29D
74VHC08MTC_TSSOP14
@
A
13
B
12
O
11
P
14
G
7
R756
0_0402_5%
1 2
R473
8.2K_0402_5% 1 2

20. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_LFRAME#
ICH_RTCRST#
LPC_LDRQ0#
LPC_LDRQ1#
ICH_AC_SYNC_R
IDE_HDIOR#
IDE_DCS1#
IAC_SDATAI2
IAC_SDATAI1
IDE_HDIORDY
ICH_AC_SDOUT_R
IDE_HDDACK#
ICH_AC_RST_R#
IDE_HDIOW#
ICH_RTCX1
IDE_HDREQ
IDE_DDREQ
LPC_LAD2
LPC_LAD1
LPC_LAD0
LPC_LAD3
IDE_DA1
IDE_DCS3#
IDE_DA2
IDE_DA0
ICH_RTCX2
H_A20M#
H_INIT#
H_IGNNE#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_CPUSLP#
H_DPSLP#
GATEA20
A20M#
IGNNE#
ICH4_INIT#
STPCLK#
SMI#
NMI
INTR
DPSLP#
CPUSLP#
H_PWRGOOD
INTRUDER#
IDE_HIRQ
KBRST#
H_DPRSLP#
DPRSLP#
FERR#
ICH_AC_BITCLK_TERM
INTRUDER#
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDOUT_R
H_FERR#
H_DPRSLP#
IDE_HDD8
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD15
IDE_HDD14
IDE_HDD10
IDE_HDD9
IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0
H_THERMTRIP#
IDE_HDIORDY IDE_HIRQ
H_THERMTRIP#
THRMTRIP_ICH#
INTRUDER#
IAC_BITCLK
<29,35>
IAC_RST#
<29>
IAC_RST#_MDC
<35>
IDE_HIORDY
<23>
IDE_HIRQ
<23>
IDE_HDACK#
<23>
IAC_SDATAI1
<29>
IAC_SDATAI2
<35>
GATEA20 <32>
KBRST# <32>
H_THERMTRIP#
<5,8>
LPC_LAD[0..3] <31,32>
LPC_LFRAME# <31,32>
IDE_HDD[0..15] <23>
IAC_SDATO
<29>
IAC_SDATO_MDC
<35>
IAC_SYNC_MDC
<35>
IDE_HDIOW#
<23>
IDE_HDIOR#
<23>
H_A20M# <5>
H_CPUSLP# <5,8>
H_DPRSLP# <5>
H_DPSLP# <5>
H_FERR# <5>
H_PWRGOOD <5>
H_IGNNE# <5>
H_INIT# <5>
H_INTR <5>
H_NMI <5>
H_SMI# <5>
H_STPCLK# <5>
IDE_HDREQ <23>
MAINPWRON <39,41,44>
LPC_LDRQ0#
LPC_LDRQ1# <31>
IDE_HDA0 <23>
IDE_HDA1 <23>
IDE_HDA2 <23>
IDE_HDCS1# <23>
IDE_HDCS3# <23>
IAC_SYNC
<29>
+RTCVCC
+RTCVCC
+VCCP
+3VS +3VS
+VCCP
+VCCP
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
20 52
Friday, March 11, 2005
2005/03/01 2006/03/01
Package
9.6X4.06 mm
Note : R169 Do not populate for
Dothan-A, Populte for Dothan-B.
Note : R168 populate 56 ohm for
Dothan-A, Populte zero ohm for
Dothan-B.
Note : R423 must be stuff for
Dothan-A, no-stuff for Dothan-B.
R143
56_0402_5%
1
2
R496
0_0402_5%
1 2
C526
0.68U_0603_10V6K
@
1 2
X1
32.768KHZ_12.5P_MC-306
1
2
C461
33P_0402_50V8J
1
2
R95
33_0402_5%
1 2
R144 56_0402_5%
1
2
R546
56_0402_5%
1
2
R148 0_0402_5%
1
2
CMOS_CLR1
SHORT PADS~D
@
1
1 2 2
RTC
LAN
SATA
AC-97/AZALIA
LPC
CPU
PIDE
U7A
ICH6_BGA609
RTCX1
Y1
RTCX2
Y2
RTCRST#
AA2
INTRUDER#
AA3
INTVRMEN
AA5
EE_CS
D12
EE_SHCLK
B12
EE_DOUT
D11
EE_DIN
F13
LAN_CLK
F12
LAN_RSTSYNC
B11
LANRXD[0]
E12
LANRXD[1]
E11
LANRXD[2]
C13
LANTXD[0]
C12
LANTXD[1]
C11
LANTXD[2]
E13
ACZ_BIT_CLK
C10
ACZ_SYNC
B9
ACZ_RST#
A10
ACZ_SDIN[0]
F11
ACZ_SDIN[1]
F10
ACZ_SDIN[2]
B10
ACZ_SDO
C9
SATALED#
AC19
SATA[0]RXN
AE3
SATA[0]RXP
AD3
SATA[0]TXN
AG2
SATA[0]TXP
AF2
SATA[2]RXN
AD7
SATA[2]RXP
AC7
SATA[2]TXN
AF6
SATA[2]TXP
AG6
SATA_CLKN
AC2
SATA_CLKP
AC1
SATARBIAS#
AG11
SATARBIAS
AF11
IORDY
AF16
IDEIRQ
AB16
DDACK#
AB15
DIOW#
AC14
DIOR#
AE16
LAD[0]/FWH[0]
P2
LAD[1]/FWH[1]
N3
LAD[2]/FWH[2]
N5
LAD[3]/FWH[3]
N4
LDRQ[0]#
N6
LDRQ[1]#/GPI[41]
P4
LFRAME#/FWH[4]
P3
A20GATE AF22
A20M# AF23
CPUSLP# AE27
DPRSLP#/TP[4] AE24
DPSLP#/TP[2] AD27
FERR# AF24
CPUPWRGD/GPO[49] AG25
IGNNE# AG26
INIT3_3V# AE22
INIT# AF27
INTR AG24
RCIN# AD23
NMI AF25
SMI# AG27
STPCLK# AE26
THRMTRIP# AE23
DA[0]
AC16
DA[1]
AB17
DA[2]
AC17
DCS1#
AD16
DCS3#
AE17
DD[0]
AD14
DD[1]
AF15
DD[2]
AF14
DD[3]
AD12
DD[4]
AE14
DD[5]
AC11
DD[6]
AD11
DD[7]
AB11
DD[8]
AE13
DD[9]
AF13
DD[10]
AB12
DD[11]
AB13
DD[12]
AC13
DD[13]
AE15
DD[14]
AG15
DD[15]
AD13
DDREQ
AB14
R551 0_0402_5%
1
2
R147 0_0402_5%
1
2
R162 0_0402_5%
1
2
R160 0_0402_5%
1
2
R504
10K_0402_5%
1
2
R483
10_0402_5%
@
1
2
R494
75_0402_5%
1 2
R762
47K_0402_5%
1 2
R467
180K_0402_5%
1 2
R151 0_0402_5%
1
2
R105
33_0402_5%
1 2
R91
33_0402_5%
1 2
R96
33_0402_5%
1 2
R101
24.9_0603_1%
1 2
R161 0_0402_5%
1
2
R114
4.7K_0402_5%
1
2
C68
10P_0603_50V8J
1
2
R474 0_0402_5%
@
1 2
R104
33_0402_5%
1 2
C
B
E
Q39
2SC2411K_SC59
1
2
3
R561
47K_0402_5%
@
1 2
C62
10P_0603_50V8J
1
2
R135 0_0402_5%
1
2
R92
33_0402_5%
1 2
R139 0_0402_5%
1
2
R541
56_0402_5%
1 2
C458
10P_0402_50V8J
@
1
2
R471
0_0402_5%
1
2
C400
0.1U_0402_16V4Z
1 2
R68
10M_0402_5%
1
2
R469
1M_0402_5%
1
2
R159 0_0402_5%
1
2

21. w
w
w
.
R
a
h
a
s
i
a
L
a
p
t
o
p
.
c
o
m
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM_DPRSLPVR
ICH_SUSCLK
VGATE
ICH_RI#
H_STP_PCI#
PM_DPRSLPVR
USBP0-
USBP0+
USBP1+
USBP2+
USBP3+
USBP1-
USBP2-
USBP5+
USBP4+
USBP3-
USBP4-
USBP5-
USBRBIAS
OVCUR#1
OVCUR#0
OVCUR#2
OVCUR#4
OVCUR#3
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
DMI_RXN0
DMI_RXN1
DMI_RXP1
DMI_RXP0
ICH_BATLOW#
SLP_S5#
SLP_S3#
PLTRST#
PWRBTN_OUT#
ICH_SMBDATA
ICH_SMBCLK
ICH_SMLINK1
ICH_SMLINK0
H_STP_CPU#
RSMRST#
SYS_RESET#
PM_BMBUSY#
CLKRUN#
CLK_14M_ICH
CLK_48M_ICH
CK_14M_ICH_TERM
CK_48M_ICH_TERM
CLK_14M_ICH
CLK_48M_ICH
MCH_SYNC#
SPKR
LINKALERT#
ICH_SMBDATA
ICH_SMLINK1
ICH_SMLINK0
ICH_SMBCLK
EC_SMI#
DMI_IRCOMP
CLK_PCIE_ICH#
CLK_PCIE_ICH
SIO_THRM#
ICH_PCIE_WAKE#
USBP7+
USBP6+
USBP6-
USBP7-
OVCUR#7
ICH_PWRGD
LINKALERT#
SYS_RESET#
ACINA
ICH_BATLOW#
ICH_PCIE_WAKE#
SIO_THRM#
MCH_SYNC#
SIRQ
OVCUR#5
OVCUR#6
CLKRUN#
DMI_TXN2
DMI_TXN3
DMI_TXP2
DMI_TXP3
DMI_RXN3
DMI_RXN2
DMI_RXP3
DMI_RXP2
SLP_S4#
EC_SCI#
ACINA
SIRQ
OVCUR#1
OVCUR#0
OVCUR#2
OVCUR#3
OVCUR#7
OVCUR#6
OVCUR#5
OVCUR#4
ICH_SMBDATA
<18>
ICH_SMBCLK
<18>
SPKR
<30>
PM_BMBUSY#
<8>
EC_SMI#
<32>
ACIN
<32,40,41>
EC_SCI#
<32>
EC_FLASH#
<33>
H_STP_PCI#
<18>
H_STP_CPU#
<18,45>
PLTRST_VGA#
<16,19>
IDE_HRESET#
<23>
IDE_DRESET#
<23>
CLKRUN#
<24,26,28,31,32>
VGATE
<8,18,45>
ICH_PWRGD
<32>
ICH_BATLOW#
<32>
PWRBTN_OUT#
<32>
PLTRST#
<19>
RSMRST#
<32>
PM_DPRSLPVR
<45>
SLP_S3#
<32>
SLP_S4#
<32>
SLP_S5#
<32>
EC_THRM# <32>
CLK_14M_ICH
<18>
CLK_48M_ICH
<18>
OVCUR#4 <36>
OVCUR#0 <36>
OVCUR#1 <36>
OVCUR#3 <36>
CLK_PCIE_ICH# <18>
CLK_PCIE_ICH <18>
DMI_RXN0 <8>
DMI_RXP0 <8>
DMI_RXN1 <8>
DMI_RXP1 <8>
DMI_RXN2 <8>
DMI_RXP2 <8>
DMI_RXN3 <8>
DMI_RXP3 <8>
DMI_TXN0 <8>
DMI_TXP0 <8>
DMI_TXN1 <8>
DMI_TXP1 <8>
DMI_TXN2 <8>
DMI_TXP2 <8>
DMI_TXN3 <8>
DMI_TXP3 <8>
USBP0- <36>
USBP0+ <36>
USBP1- <36>
USBP1+ <36>
USBP2- <35>
USBP2+ <35>
USBP3- <36>
USBP3+ <36>
USBP4- <36>
USBP4+ <36>
USBP5-
USBP5+
USBP6-
USBP6+
USBP7-
USBP7+
SIRQ
<26,31,32>
LID_SWOUT#
<32>
+3VS
+3VSUS
+3VSUS
+3VSUS
+1.5VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3V
+3VS
+3VSUS
+3VS
+3VS
+3V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2362 1
<Title>
Custom
21 52
Friday, March 11, 2005
2005/03/01 2006/03/01
(PCI Express Wake Event)
May need pulldown for DPRSLPVR in case
the ICH6m does not set this value in time
for boot.
closed to 500 mils
R141
22.6_0603_1%
1 2
R130
10K_0402_5%
1 2
PCI-EXPRESS
DIRECT
MEDIA
INTERFACE
USB
CLOCK
GPIO
POWER
MGT
U7C
ICH6_BGA609
RI#
T2
SATA[0]GP/GPI[26]
AF17
SATA[1]GP/GPI[29]
AE18
SATA[2]GP/GPI[30]
AF18
SATA[3]GP/GPI[31]
AG18
SMBCLK
Y4
SMBDATA
W5
LINKALERT#
Y5
SMLINK[0]
W4
SMLINK[1]
U6
MCH_SYNC#
AG21
SPKR
F8
SUS_STAT#/LPCPD#
W3
SYS_RESET#
U2
BM_BUSY#/GPI[6]
AD19
GPI[7]
AE19
GPI[8]
R1
STP_PCI#/GPO[18]
AC21
GPO[19]
AB21
STP_CPU#/GPO[20]
AD22
GPO[21]
AD20
GPO[23]
AD21
GPIO[24]
V3
GPIO[25]
P5
GPIO[27]
R3
GPIO[28]
T3
CLKRUN#/GPIO[32]
AF19
GPIO[33]
AF20
GPIO[34]
AC18
WAKE#
U5
SERIRQ
AB20
THRM#
AC20
CLK14
E10
CLK48
A27
SUSCLK
V6
SLP_S3#
T4
SLP_S4#
T5
SLP_S5#
T6
PWROK
AA1
DPRSLPVR/TP[1]
AE20
LAN_RST#
V5
BATLOW#/TP[0]
V2
PWRBTN#
U1
VRMPWRGD
AF21
RSMRST#
Y3
PERn[1]
H25
PERp[1]
H24
PETn[1]
G27
PETp[1]
G26
PERn[2]
K25
PERp[2]
K24
PETn[2]
J27
PETp[2]
J26
SMBALERT#/GPI[11]
W6
GPI[12]
M2
GPI[13]
R6
PERn[3]
M25
PERp[3]
M24
PETn[3] L27
PETp[3] L26
PERn[4] P24
PERp[4] P23
PETn[4] N27
PETp[4] N26
DMI[0]RXN T25
DMI[0]RXP T24
DMI[0]TXN R27
DMI[0]TXP R26
DMI[1]RXN V25
DMI[1]RXP V24
DMI[1]TXN U27
DMI[1]TXP U26
DMI[2]RXN Y25
DMI[2]RXP Y24
DMI[2]TXN W27
DMI[2]TXP W26
DMI[3]RXN AB24
DMI[3]RXP AB23
DMI[3]TXN AA27
DMI[3]TXP AA26
DMI_CLKN
AD25
DMI_CLKP
AC25
DMI_ZCOMP
F24
DMI_IRCOMP
F23
OC[4]#/GPI[9]
C23
OC[5]#/GPI[10]
D23
OC[6]#/GPI[14]
C25
OC[7]#/GPI[15]
C24
OC[0]#
C27
OC[1]#
B27
OC[2]#
B26
OC[3]#
C26
USBP[0]N
C21
USBP[0]P
D21
USBP[1]N
A20
USBP[1]P
B20
USBP[2]N
D19
USBP[3]N
A18
USBP[3]P
B18
USBP[4]N
E17
USBP[4]P
D17
USBP[5]P
A16
USBP[5]N
B16
USBP[6]N
C15
USBP[6]P
D15
USBP[7]N
A14
USBP[7]P
B14
USBP[2]P
C19
USBRBIAS#
A22
USBRBIAS
B22
R459
10K_0402_5%
1
2
C520
4.7P_0402_50V8C
@
1
2
R536 0_0402_5%
@
1 2
R487
10_0402_5%
@
1
2
R120 33_0402_5%
@1 2
R451
680_0402_5%
1 2
R117
10K_0402_5%
1
2
R556
10_0402_5%
@
1
2
R69
10K_0402_5%
1 2
R761 10K_0402_5%
1 2
R725 39K_0402_5%
1 2
R71
10K_0402_5%
1
2
R787 10K_0402_5%
1 2
R782 10K_0402_5%
1 2
T40
PAD
@
R460
2.2K_0402_5%
1
2
R518
10K_0402_5%
1 2
R746 0_0402_5%
1 2
T21
PAD
@
R529
8.2K_0402_5%
1 2
R461
2.2K_0402_5%
1
2
R75
10K_0402_5%
1
2
R455
10K_0402_5%
1 2
R788 10K_0402_5%
1 2
R523
100K_0402_5%
@
1
2
R125
10K_0402_5%
1
2
T32
PAD
@
R449
10K_0402_5%
1
2
R784 10K_0402_5%
1 2
R781 10K_0402_5%
1 2
R456
10K_0402_5%
1 2
R729 0_0402_5%
@
1 2
T30 PAD
@
R516
1K_0402_5%
@
1
2
R510 10K_0402_5%
1 2
R786 10K_0402_5%
1 2
R457
10K_0402_5%
1 2
T22
PAD
@
R783 10K_0402_5%
1 2
C455
4.7P_0402_50V8C
@
1
2
T23
PAD
@
R517 24.9_0603_1%
1 2
D15
RB751V_SOD323
2 1
R507 10K_0402_5%
@
1 2
G
D
S
Q47
2N7002_SOT23
2
1 3
R450
10K_0402_5%
1
2
R785 10K_0402_5%
1 2