1. Swapnadip Ghosh
Address: 445, Waupelani Dr. Apt #H21, State College, PA-16801
http://sites.google.com/site/swapnadipghoshmicorwave/
Email: sxg345@psu.edu, Tel: 505-459-8462
Research Interests:
 Novel nanoelectronic devices, beyond-CMOS devices, sub-60 mV/dec transistors.
 Complex oxides, ferroelectrics on Si and III-V substrates.
 Group-IV and III-V electronic materials, heteroepitaxy.
 Fast transistors and photovoltaic devices using nanostructured materials.
 Energy efficient RFIC design using a network of negative capacitance low-power transistors.
Education:
 Ph.D. (2010-2014), University of New Mexico: in Electrical Engineering, (GPA: 3.82/4.0)
Dissertation: “Large-area, wafer-scale epitaxial growth of germanium on silicon and integration
of high-performance transistors,” Advisor: Prof. Sang M. Han
 Bachelor of Technology (1998-2002), University of Kalyani, India: with honors in
Electronics & Telecommunication Engineering, (Percentage: 80.4/100)
Awards and Grants:
 2015: STC.UNM Innovation Award
 2014: AVS 2014 National Graduate Research Award
 2014: UNM Sigma Xi Excellence in Graduate Research Award
 2014: Travel Award from MRS for Presenting at Electronic Materials Conference
 2013: Best Graduate Student Speaker Award by NM AVS
 2013: AVS Dorothy M. and Earl S. Hoffman Travel Grant
 2013, 2012: UNM SCAP Travel Grant Award for Presenting Research at ECS and AVS Meetings
 2012, 2011: RTP Grant Awards for Presenting Research at MRS and AVS meetings
 1998, 1996: National Scholarship Merit Awards from Government of India
Research Experience:
 Postdoctoral Research Associate, Pennsylvania State University (2/2015-Present)
PIs: Suman Datta, Sumeet K. Gupta
 Investigated the thickness dependent negative capacitance phenomenon in complex oxides
such as Pb(Zr0.2Ti0.8)O3, (Hf0.5Zr0.5)O2, which led to the experimental demonstration of steep-
switching (<60mV/decade) in negative capacitance transistors using this ferroelectric gate
oxides.
 Monolithic integration of complex oxides with Si using thin HfO2 and SiO2 buffer layers.
 Characterization of negative capacitance transistors fabricated using CMOS compatible,
sputtered, polycrystalline ferroelectric oxides.
 Studied the SPICE-based modeling framework to design Inverters and SRAM utilizing negative
capacitance transistors for ultra low-power computing architecture.
 Graduate Research Assistant, University of New Mexico (1/2010-1/2015)
PIs: Sang M Han, Sang Eon Han, Talid Sinno (U. Penn)
1) High Carrier Mobility Transistors Fabricated on Ultra-Low-Dislocation-Density
Germanium Heteroepitaxially Grown on Silicon:
 Developed and implemented a novel epi-growth technique for achieving ultra-low-dislocation
density epitaxial germanium-on-silicon (GoS) using molecular beam epitaxy (MBE) on the
wafer-scale, reaching a threading dislocation density below 105 cm-2 .
 Engineered a unique growth process using an artificially introduced air-gapped, nano-
templates to relieve thermal stress in GoS.

2.  Modeling residual stress in Ge epilayer using COMSOL Multiphysics.
 Characterization of epilayer using z-contrast TEM, SEM, XPS, nano-probe EDX.
 Design, fabrication and characterization of high-performance p- and n-Metal-Oxide-
Semiconductor-FETs(MOSFETs) and p-MESFETs on Ge-on-Si films.
 Demonstrated outstanding effective mobility characteristics, and have shown 82% and 30%,
respectively, hole and electron mobility improvements compare to Si universal mobility.
 Modeling of Ge-on-Si transistors using a TCAD tool, named Crosslight.
 Demonstrated optical quality of Ge film through photoluminescence, which can lead to
fabrication of Ge-based light sources for Si-based photonics applications.
2) Large-Scale Patterning of Germanium Quantum Dots by Stress Transfer:
 Demonstrated growth of highly-ordered 2D arrays of semiconductor quantum dots, such as
Ge on a SiGe substrate. This lends itself to a variety of technologically important applications,
ranging from photodetectors, memory, and quantum computing.
 Implemented a thermal annealing system to perform experiments to demonstrate the
compositional redistribution of Si and Ge in the near-surface region of Si1-xGex substrates by
applying a spatially structured compressive stress to the substrate and thermally annealing the
substrate under stress. This compositional redistribution of atoms in turn can be used to grow
Ge QDs.
 Studied the compositional redistribution on the SiGe surface using STEM and nano-probe EDX.
 Demonstrated a unique, first of its kind, composition distribution of Si and Ge atoms where
compressed region shows near-complete Ge depletion and Si enrichment by in atomic
concentration.
3) Symmetry-breaking Light-trapping Nanostructures on Silicon:
 Demonstrated a novel periodic light-trapping nanostructure on silicon to implement an
efficient light-trapping mechanism.
 Fabrication of broken-symmetry, photonic lattice with nanostructured 2D-patterns on c-Silicon.
 Developed and implemented a photolithographic process and make use of wet etching
(anisotropic and isotropic) methods, to create symmetry-breaking, nanoscale features on c-Si.
 Demonstrated a scheme using broken-symmetry, pattern on back-electrode (such as Ag) to trap
light efficiently.
 Summer Research Intern, Actoprobe LLC, Albuquerque, NM (6/2014-8/2014)
 Responsible for developing etching process for fabricating nanostructures in III-V, which is
integrated on Si though wafer-bonding process.
Industrial Experience:
1) Lead Design Engineer (RF), in collaboration with Texas Instruments and SASKEN
Communication Ltd., Bangalore, India (11/2008-12/2009)
 Worked on the development cycle of the multiple IP combo GPS receiver.
 Providing leadership to a small team associated to this project.
2) Lead Design Engineer (RF), in collaboration with NOKIA and SASKEN Communication Ltd.,
Tampere, Finland (6/2007-10/2008)
 Fabricated antennas for GSM main (high and low band), diversity (high and low band) and
special band at 2.62 GHz (70MHz BW) in a limited space for high data rate modem system.
3) Design Engineer, General Electric Company, Bangalore, India (2/2006-11/2006)
 Simulated and characterized a 3T RF coil with complex high power quadrature hybrid
transmitter receiver (QHTR) circuit at 128.86MHz for 3T 3-channel head coil for MR systems.
 Implemented Six-sigma analysis to optimize the design parameters and specifications.

3. 4) Research scientist, Society for Applied Microwave Electronics Engineering & Research
(SAMEER), IIT Mumbai, India (12/2002-1/2006)
 Developed RF front end receiver components for a integrated digital microwave receiver.
 Implemented following algorithms using digital signal processing: a) Input-tracking to control
PLL synthesizer, b) control the digital receiver chip (AD6620) interfaced with ADC (AD6640), c)
demodulation of incoming AM & FM signal and I & Q signal processing.
 Designed a wide band antenna (4 GHz center freq with 200MHz band-width) for the transceiver
system.
 Designed and simulated using HFSS an airborne planar antenna with VSWR 2.5 (average) in
frequency Range of 100-400MHz.
Research Techniques/Skills:
 Intimate knowledge of ultra-high vacuum systems and components including gauges, pumps,
and instrumentation obtained through assembly, and maintenance of a MBE system.
 Material characterization tools: transmission electron microscopy (TEM), scanning electron
microscopy (SEM), atomic force microscopy (AFM), x-ray diffraction (XRD), photoluminescence
(PL), energy dispersive spectroscopy (EDX), and x-ray photoelectron spectroscopy (XPS), and
UV-VIS reflectance Spectroscopy.
 Cleanroom processing: Class 1000 clean room experience (>3,000 hrs), interferometric
Lithography, photolithography, plasma-RIE, PECVD, diffusion, optical microscope, e-beam
fabrication, rapid thermal annealing (RTA), sputtering.
 Device characterization tools: Hall, Current-voltage (I-V), capacitance-voltage (C-V).
Equipments: Network, noise figure, and spectrum analyzer, cathode ray oscilloscope.
 Software: COMSOL multiphysics, Crosslight-TCAD, Gatan digital micrograph, HP-ADS for RF
Circuit, CST Microwave Studio, Matlab, SolidWorks, CADENCE
Peer-reviewed Publications:
1) S. Ghosh, A. Aziz, R. Lee, T. Ngai, S. K. Gupta and S. Datta “Steep Slope Negative-Capacitance
FETs Using Polycrystalline PZT and HZO Ferroelectric Gate Stack,” Intl. Electron Devices Meeting
(IEDM), Submitted, (2015).
2) S. Ghosh, T. Sinno and S. M. Han, “Device Implications of Achieving Sub-105-cm-2 Dislocation
Density by Oxygen Precipitates in Epitaxial Ge on Si,” Appl. Phys. Lett., in preparation (2015).
3) S. Ghosh, D. Kaiser, J. E. Bonilla, T. R. Sinno and S. M. Han“Creating a Responsive SiGe Substrate
to Form 2D Array of Ge Quantum Dots Using Stress-induced Near-surface Compositional
Redistribution,” Appl. Phys. Lett., Accepted (2015).
4) S. Ghosh, S. J. Han, B. Hoard, E. Culler, J. E. Bonilla, E. J. Martin, J. Grey, S. M. Han and S. E. Han,
“Symmetry-Breaking Nanostructures for Enhanced Light-Trapping in Thin Film Solar Cells”
42nd IEEE Photovoltaic Specialists Conference (PVSC), Accepted, (2015).
5) S. Ghosh, and S. M. Han, “High-carrier Mobility Ge-channel p- and n-Field Effect Transistors
Fabricated From Large-area, Wafer-scale, Epitaxially Grown Ge on Si Substrate,” IEEE Electron
Device Letters, 35(9), September, (2014).
6) S. Ghosh, D. Leonhardt, and S. M. Han, “Effect of Threading Dislocation Density and Dielectric
Layer on Temperature Dependent Switching Characteristics of High-Hole Mobility Ge-channel
Field Effect Transistor Fabricated From Epitaxially Grown p-Ge on Si Substrate,” Journal of
Applied Physics, 115 (9), 094507, (2014).
7) S. Ghosh, D. Leonhardt, and S. M. Han, "Investigations on Thermal Stress Relief Mechanism
Using Air-Gapped SiO2 Nanotemplates during Epitaxial Growth of Ge on Si and Corresponding
Hole Mobility Improvement," ECS Trans., vol. 45, pp. 111-114, (2012).
8) S. Ghosh, D. Leonhardt, and S. M. Han, "Experimental and theoretical investigation of thermal
stress relief during epitaxial growth of Ge on Si using air-gapped SiO2 nanotemplates," Appl.
Phys. Lett., vol. 99, p. 181911, (2011).

4. 9) D. Leonhardt, S. Ghosh, and S. M. Han, "Defects in Ge epitaxy in trench patterned SiO2 on Si and
Ge substrates," J. Cryst. Growth, vol. 335, pp. 62–65, (2011).
10) D. Leonhardt, S. Ghosh, and S. M. Han, "Origin and removal of stacking faults in Ge islands
nucleated on Si within nanoscale openings in SiO2," J. Appl. Phys., vol. 110, p. 073516, (2011).
11) K.P.Ray, S.Ghosh and K.Nirmala, “Compact broadband gap-coupled microstrip antennas,” IEEE
Antennas and Propagation Society International Symposium, (2006).
12) K.P.Ray, S.Ghosh and K.Nirmala, “Multi-layer multi-resonator circular microstrip antennas for
broad band and dual band operations,” MOTL journal, Vol 47, issue 5, (2005).
Patents and Invention Disclosures:
1) US Patent 20150130017 A1, “Semiconductor device and method of making the device,”, S.
Ghosh, D.Leonhardt, S.M.Han, (2015).
2) US patent application, PCT/US2014/061178, “Use Methods to Introduce Sub-Micrometer,
Symmetry-Breaking Surface Corrugation to Silicon Substrates to Increase Light Trapping”, S.
Ghosh, S. E. Han, S. M. Han, (2013).
Invited Talks:
1) S. Ghosh, “From Large-area, Wafer-scale Ge-Based Epitaxy to Creating a Responsive SiGe
Substrate to Form a 2D Array of Ge Quantum Dots as a Basis for Future Transistor
Architecture,” Electrical & Computer Engineering Departmental Seminar, University of New
Mexico, January 30, 2015.
2) S. Ghosh “Characterizations of Large-area, Wafer-scale Ge-Based Epitaxy, Devices, and 2D Array
of Quantum Dots of Ge on Si/SiGe Platform,” Chemical & Biomedical Engineering Departmental
Seminar, University of New Mexico, October 15, 2014.
3) S. Ghosh, “From Large-area, Wafer-scale Ge-Based Epitaxy to Creating a Responsive SiGe
Substrate to Form a 2D Array of Ge Quantum Dots as a Basis for Future Transistor
Architecture,” AVS 61th Annual International Symposium and Exhibition, Baltimore, November
11, 2014. (AVS Award Talk)
Presentations:
1) S. Ghosh, T. R. Sinno and S. M. Han, “Characterizations of Large-area, Wafer-scale Ge-Based
Epitaxy, Devices, and 2D Array of Quantum Dots of Ge on Si/SiGe Platform,” 26th Annual Rio
Grande Symposium on Advanced Materials, October 6, 2014.
2) S. Ghosh, D. Kaiser, T. R. Sinno and S. M. Han, “Creating a Responsive SiGe Substrate to Form
2D Array of Ge Quantum Dots Using Stress-induced Near-surface Compositional
Redistribution,” AVS 61th Annual International Symposium and Exhibition, Baltimore, 2014.
3) S. Ghosh, and S. M. Han, “Structural, Electrical, and Optical Characterization of Impurity-
Dependent, Ultra-Low-Dislocation-Density Ge Epitaxially Grown on Si and Characterization of
MOSFETs Fabricated on Ge-on-Si,” AVS 61th Annual International Symposium and Exhibition,
Baltimore, 2014.
4) S. E. Han, S. Ghosh, T. Cai, B. R. Hoard, S. M. Han, “Symmetry-Breaking in Light Trapping
Nanostructures on Silicon for Solar Photovoltaics,” AVS 61th Annual International Symposium
and Exhibition, Baltimore, 2014.
5) S. E. Han, S. Ghosh, T. Cai, B. R. Hoard, S. M. Han, “Symmetry-Breaking in Light-Trapping
Nanostructures on Silicon for Solar Photovoltaics,” 14th AiChe General Annual Meeting, Atlanta,
GA, 2014.
6) S. Ghosh, and S. M. Han, “Impurity-Dependent Dislocation Reduction in Heteroepitaxially
Grown Wafer-Scale Ge on Si and Device Characterization of MOSFETs Fabricated on
Engineered Ge-on-Si Substrates,” Electronic Materials Conference, UCSB, CA, 2014.

5. 7) S. Ghosh, and S. M. Han, “Impurity-Dependent Ultra-low Dislocation Density Ge Epitaxially
Grown on Si and Its Device Characterization by Fabricating MOSFET,” 36th Surface Analysis
Meeting, Albuquerque, NM, 2014.
8) S. Ghosh, and S. M. Han, “High-Carrier-Mobility p- and n-Type Field Effect Transistors
Fabricated on Large-Area Wafer-Scale Ge Film Epitaxially Grown on Si,” MRS-2014 Annual
International Symposium and Exhibition, San Francisco, CA, , 2014.
9) S. Ghosh, and S. M. Han, “Experimental and Theoretical Investigation of Stress-induced Near-
surface Compositional Redistribution on Si0.8Ge0.2 Substrates for 2D Array Growth of Ge
Quantum Dots,” MRS-2014 Annual International Symposium and Exhibition, San Francisco, CA,
2014.
10) B. Hoard, S. Ghosh, S. M. Han, and S. E. Han, “Symmetry-Breaking in Light-Trapping
Nanostructures on Silicon,” MRS-2014 Annual International Symposium and Exhibition, 2014,
San Francisco, CA, 2014.
11) S. Ghosh, and S. M. Han, “High-carrier-mobility p- and n-Field Effect Transistors Fabricated on
Wafer Scale Planar Ge Film Epitaxially Grown on Si,” AVS 60th Annual International
Symposium and Exhibition, Oct 28, 2013, Long Beach, CA, 2014.
12) S. Ghosh, J. Bonilla, D. Kaiser, T. R. Sinno and S. M. Han “Experimental and Theoretical
Investigations of Stress-induced Near-surface Compositional Redistribution on Si0.8Ge0.2
Substrates for 2D Array Growth of Ge Quantum Dots,” AVS 60th Annual International
Symposium and Exhibition, Oct 29, 2013, Long Beach, CA, 2014.
13) S. Ghosh, J. Bonilla, D. Kaiser, T. R. Sinno and S. M. Han, “Experimental and Theoretical
Investigations of Stress-induced Near-surface Compositional Redistribution on Si0.8Ge0.2
Substrates for 2D Array Growth of Ge Quantum Dots,” 25th Annual Rio Grande Symposium on
Advanced Materials, October 7, 2013.
14) S. Ghosh and S. M. Han, “High-carrier-mobility p- and n-Field Effect Transistors Fabricated on
Wafer Scale Planar Ge Film Epitaxially Grown on Si,” NM AVS Symposium, Albuquerque, May
22, 2013 (Best Speaker Award).
15) S. Ghosh and S. M. Han, “Impact of Threading Dislocation Density and Dielectric Layer on
Device Characteristics of p-MESFETs Fabricated on Ge-on-Si Substrates,” MRS-2013 Annual
International Symposium and Exhibition, San Francisco, CA, 2013.
16) S. Ghosh and S. M. Han, “Implantation-Free, High-Hole-Mobility p-MOSFETs Fabricated on Ge
Epitaxially Grown on Si,” MRS-2013 Annual International Symposium and Exhibition, San
Francisco, CA, 2013.
17) S. Ghosh, D. Leonhardt, and S. M. Han, “Impact of Threading Dislocation Density and Dielectric
Layer on I-V Characteristics of Schottky Diodes Fabricated from Ti and Epitaxially Grown p-
Type Ge on Si,” AVS 59th Annual International Symposium and Exhibition, Tampa, FL,
November 1, 2012.
18) S. Ghosh, D. Leonhardt, and S. M. Han, “Investigations on thermal stress relief mechanism
using air-gapped SiO2 nanotemplates during epitaxial growth of Ge on Si and corresponding
hole mobility improvements,” 221st ECS meeting, Seattle, WA, 2012.
19) S. Ghosh, D. Leonhardt, and S. M. Han, “Impact of Threading Dislocation Density and Dielectric
Layer on I-V Characteristics of Schottky Diodes Fabricated from Ti and Epitaxially Grown p-
Type Ge on Si,” NM AVS Symposium, Albuquerque, May 23, 2012.
20) S. Ghosh, D. Leonhardt, and S. M. Han, “Experimental and Theoretical Investigations Using SiO2
Nanotemplates to Relieve Stress Caused by Thermal Expansion Coefficient Mismatch in
Epitaxial Germanium Grown on Silicon,” AVS 58th Annual International Symposium and
Exhibition, Nashville, TN, October 30, 2011.
21) S. Ghosh, D. Leonhardt, and S. M. Han, “Experimental and Theoretical Investigations Using SiO2
Nanotemplates to Relieve Stress Caused by Thermal Expansion Coefficient Mismatch in
Epitaxial Germanium Grown on Silicon,” NM AVS Symposium, Albuquerque, May 24, 2011.

6. 22) S. Ghosh, D. Leonhardt, and S. M. Han, “Use of SiO2 Nanotemplates for Relieving Thermally
Induced Stress During Epitaxial Growth of Ge on Si for III-V Photovoltaic Applications,”
Materials Research Society Spring Meeting, San Francisco, CA, April, 2011.
23) S. Ghosh, and S. M. Han, “Using SiO2 Nanotemplates to Relieve Stress Caused by Thermal
Expansion Coefficient Mismatch in Epitaxial Germanium Grown on Silicon,” IONS-2010
Conference, University of Arizona, AZ, 2010.
Memberships:
Optical Society of America, American Vacuum Society, Electrochemical Society, Material Research
Society
Professional services and peer-reviewing:
 Served as a session chair in College of Engineering Research Symposium (CERS), Penn State
University, April 2nd, 2015.
 Participated in the Elevator Speech (30 sec) competition as a showcase of postdoc research
pursued at Penn State University, State College, PA, July 27, 2015.
 Served as a treasurer for optical society of America, UNM student chapter, in the academic year of
2010-2011.
Peer-reviewing: 2015 College of Engineering Research Symposium (CERS), Penn State University
Leadership Experience (Research Mentorship):
I have mentored 4 graduate (chemical and nanoscience majors) and 4 undergraduate students
(electrical, chemical, material science, chemistry majors) at University of New Mexico. Their
projects focused on nanostructure fabrication, epitaxial growth, structural and electrical
characterization of thin films and device modeling and simulation.
Graduate: S. Atiganyanun (UNM, 1/2014-1/2015), M. Zhou (UNM, 5/2014-1/2015), C. Harrison
(UNM, 8/2013-1/2014), S. J. Han (UNM, 8/2014-1/2015)
Undergraduate: M. Hirsch (REU Student, John Brown University, 6/2014-8/2014), J Bonilla (Uni.
of New Mexico, 8/2012-11/2014, currently at Intel corp.), E. Culler (REU Student, Wilkes University,
6/2013-8/2013, currently pursuing Ph.D. at Univ. Colorado, Boulder), M. Flammia (REU Student,
Arizona State University, 6/2014-8/2014)
References:
 Prof. Suman Datta, Professor and Notre Dame Chair in Engineering Innovation, Department of
Electrical Engineering, University of Notre Dame, Notre Dame, IN, sdatta@engr.psu.edu
 Prof. Sang M. Han, Professor in Chemical & Biological Engineering and Electrical & Computer
Engineering, University of New Mexico, meister@unm.edu
 Prof. Talid R. Sinno Professor, Chemical and Biomolecular Engineering and Mechanical
Engineering and Applied Mechanics, University of Pennsylvania, talid@seas.upenn.edu
 Prof. Sanjay Krishna, Professor and Regents Lecturer, Director, Center for High Technology
Materials, Electrical and Computer Engineering, University of New Mexico,
skrishna@chtm.unm.edu