This document is a resume for Kyounkwon Park. It summarizes his education, including a Ph.D. in Electrical Engineering from UCLA in 2014, as well as his technical skills and work experience. Park currently works as a Senior Engineer at Samsung Display Co. designing nanocrystal-based display panels. He has also conducted research at UCLA on topics including quantum dot synthesis and characterization, optical voltage sensing using semiconductor nanoparticles, and nanoscale integrated circuits.

1. KYOUNGWON PARK
Hyundai APT 38-801, Ogum-dong, Songpa-gu
Seoul, 138-740, South Korea
82-10-3051-3655, pkw0818@gmail.com
EDUCATION
University of California, Los Angeles, CA, Postdoc., Chemistry, 2014
University of California, Los Angeles, CA, Ph.D., Electrical Engineering, 2014, GPA: 3.7/4.0
University of California, Los Angeles, CA, M.S, Electrical Engineering, 2009, GPA: 3.8/4.0
Korea University, Seoul, Korea, B.S, Electrical Engineering, 2007, Major GPA: 3.9/4.0
Graduate Courseworks: Optics, Solid State Physics, Quantum Mechanics, Semiconductor Device
Design, Analog and Digital Integrated Circuit, MEMS, Signal and Systems
TECHNICAL SKILLS
Software Python, MATLAB, Labview, MySQL, TCAD, SPICE, Lighttools
Calculation FDM, Image processing, Monte-Carlo sim., Schr¨odinger solver
Optics Display panel design, Optical setup, Spectroscopy
Display Fab. Process Nanocrystal patterning, Photolithography, Electron Microscopy (TEM,
SEM)
Chemistry Quantum dot (QD) synthesis & Characterization, QD surface functionalization
WORK EXPERIENCE
Senior Engineer, Panel Design Engineer, Samsung Display Co., Yongin-Si, Gyeonggi-do, South
Korea 2015 - Present
Nanocrystal-based Panel (NCP) design. Mathematical modeling of NCP with Quantum me-
chanical and Monte-Carlo calculation. Developed endurable nanocrystal resin
Research Associate, Optical Voltage Sensor, Electrical Engineering and Chemistry Department,
University of California, Los Angeles, CA 2009 - 2014
Quantum-Confined Stark Effect Measurement First demonstrated quntum-confined
Stark effect (QCSE) at room temperature for single particle level. Optimized a semiconductor
structure such that it exhibits 4X larger QCSE than previously demonstrated nanoparticles.
First unveiled wavelength blue-shift in QCSE and field-dependent Auger recombination rate.
Finite Difference Calculation Calculated semiconductor nanoparticle’s voltage sensitivity
by 3D self-consistent Schr¨odinger-Possion equation, assumed in realistic environmental condi-
tion. Dielectric inhomogeneity is considered. To do this, custom FDM solver is developed on
Python.
Voltage Visulization Visualized voltage dynamics of a cellular network by semiconductor
optical voltage sensor. Provided high spatio (sub µm) - temporal (sub ms) resolution and larger
than 10 % sensitivity for 100 mV change. Voltages are revealed in change of either intensity,
spectrum, lifetime and (or) ratiometic measurement of spectrally separated intensity.
Research Assistant, Nanoscale ASIC, Electrical Engineering Department, University of California,

2. KYOUNGWON PARK Page 2
Los Angeles, CA 2007-2009
Developed a fabric style ASIC structure and logic scheme to replace CMOS technology, con-
sisting of horizontal and vertical nanowires (NWs). Nanoscale ASIC proves 2X density benefits
compared to the 16nm CMOS logic.
Teaching Faculty, Electrical Engineering and Chemistry Department, University of California, Los
Angeles, CA 2009-2013
Quantum Chemistry (2011S, 2012W, 2013S), Principles of Semiconductor Device Design (2009W,
2009S, 2010W), Physics for Electrical Engineers (2010S)
Research Intern, Brain-Computer Interface, Samsung Advanced Institute of Technology,
Giheung, Korea Sum-
mer 2009
Proposed light-induced neuron stimulating and sensing techniques for Brain-Computer In-
terface (BCI). Stimulation is based on either photovoltaic effect or accumulation of dipoles.
Sensing is based on QCSE. Proposed idea was realized experimentally during Ph.D research
afterwards.
Research Intern, Si-Ge core/shell NW TR, Samsung Advanced Institute of Technology,
Giheung, Korea, Summer 2008
Developed two fabrication methods of Si/Ge Core-Shell Nanowire transistors (TR) for future
PMOS application. Extracted output, transfer characteristics and capacitances.
Student Intern, Circuit Design, Analog Device Inc., Seongnam, Korea Summer 2006
Developed a DC-DC buck converter. 3.6 mV ripple, 1.2V Vout, 200 mA of load current, 47◦
phase margin, 93 % power efficienty
Sergent, 67th Infantry Division of Republic of Korean Army, Computation Unit, Korea 2002-2004
PUBLICATIONS
K. Park et al., Regarding QD characterization, Nature Materials, 2015 (Submitted)
K. Park et al., Membrane insertion of- and membrane potential sensing by-semiconductor voltage
nanosensors: feasibility demonstration , Nature Communication, 2015 (Submitted)
K. Park, S. Weiss, Self-consistent Schrdinger-Poisson calculations, performance predictions, and
design rules for membrane-embedded semiconducting voltage-sensing nanoparticles, Small, 2015
(Submitted)
K. Park, Z. Deutsch, J. Li, D. Oron, S. Weiss, Single Molecule Quantum Confined Stark Effect
Measurement of Semiconductor Nanoparticles at Room Temperature, ACS Nano, 2012, 6
and 7 more conference proceedings.
PATENTS
Method of Forming Core/Shell Type Structure and Method of Manufacturing Transistor
- Application Number: 20100151659 (US), 1020080128183 (KR)
and 8 display panel patents.
AWARDS
Award from Qualcomm mobile game design competition 2006
Academic honor prizes at Korea University 2004 - 2006