Wafer probe technology & application overview ira feldman 101108

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Presentation by Ira Feldman (High Technology Business Development www.hightechbizdev.com) at the Silicon Valley Test Conference (November 8, 2010).

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Wafer probe technology & application overview ira feldman 101108

  1. 1. OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached -1500.0 -1000.0 -500.0 0.00 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 -200.0 0.00 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 Time (ps) V o l t a g e -m V- V [U3.1 (at pin)] Wafer Probe Technology &  Application Overview Date: Wednesday Mar. 3, 2010 Time: 14:16:09 Application Overview Ira Feldmana e d a 650‐472‐1192 iradave@gmail.com www.hightechbizdev.comwww.hightechbizdev.com 1Silicon Valley Test Conference 2010© 2010 Ira Feldman
  2. 2. AgendaAgenda • IntroductionIntroduction • Application Examples C h l i / b• Contact Technologies / Probe Types • Top Vendors • Hot Topics • SummarySummary • Resources Silicon Valley Test Conference 2010 2
  3. 3. Devices & Packages – Have Evolved! Silicon Valley Test Conference 2010 3 UV EPROM circa 1974 http://www.cpushack.com/EPROM.html
  4. 4. Peripheral Pads ‐ LogicPeripheral Pads  Logic SWTW 2009: MEMS Technology – Enabling Design Silicon Valley Test Conference 2010 4 http://www.chipworks.com/uploadedImages/Blog/blogimagessq3 10/AKM8975_6210_cal_branded.JPG Flexibility for Fine Pitch Probing Bahadir Tunaboylu, SV Probe
  5. 5. Fine Pitch LogicFine Pitch Logic Silicon Valley Test Conference 2010 5 Kulicke & Soffa: http://www.imaps.org/imaps2005/keynote.pdf SWTW 2009: MEMS Technology – Enabling Design Flexibility for Fine Pitch Probing Bahadir Tunaboylu, SV Probe
  6. 6. Area Array – Logic, µP, etc.Area Array  Logic, µP, etc. Silicon Valley Test Conference 2010 6 http://www.tradekorea.com/product-detail/P00032217/Solder_Bump.html
  7. 7. Marketing Version of a CPU…Marketing Version of a CPU… Intel Core i7-980X Extreme 6-Core Processor (32nm Q1 ’10) Silicon Valley Test Conference 2010 7 ( ) http://hothardware.com/News/Intel-Core-i7980X-Extreme-6Core- Processor-Review/
  8. 8. …What Probe Really Sees…What Probe Really Sees Silicon Valley Test Conference 2010 8 Intel Technology Journal (6/2008): 45 nm process ~50 µm tall Cu bumps
  9. 9. No One Solution Fits AllNo One Solution Fits All100 nt(K) DRAM & 050 robeCou & NOR FLASH Memory 510 ximatePr Microprocessor & Logic SOC & Logic LCD / NAND FLASH 1 Approx TSV g (Area Array) g LCD / Display Memory Silicon Valley Test Conference 2010 9 150 100 6080 2040 Approximate Pitch (µm)
  10. 10. Many Other ParametersMany Other Parameters • “Pad” type – bond pad, BGA, column, bumpyp p , , , p • Pad Configuration – peripheral, LOC, DLOC, array • Die Size • Pad Size ‐ passivation opening & keep away • Pad Metal – Al, Cu, Au, solder, etc. • Force Requirements • Scrub Depth • Frequency / Bandwidth• Frequency / Bandwidth • Pad Density (probes / mm2) • Active Area (size of probe array)Active Area (size of probe array) • Temperature Silicon Valley Test Conference 2010 10
  11. 11. Contact Technologies /  Probe Types • CantileverCantilever • Blade • VerticalVertical  • MEMS – VerticalVertical – Micro Cantilever – Torsional • Spring • Membrane Silicon Valley Test Conference 2010 11
  12. 12. CantileverCantilever Technoprobe K&S: http://www.imaps.org/imaps2005/keynote.pdf Technoprobe Silicon Valley Test Conference 2010 12
  13. 13. BladeBlade Silicon Valley Test Conference 2010 13SV Probe
  14. 14. Vertical ‐ Buckling BeamVertical  Buckling Beam M SWTW T t i l 2004 FormFactor: “MEMS for ProbeCard Applications” Chong Chan Pin – Semicon Singapore 2010 Mann: SWTW Tutorial 2004 Silicon Valley Test Conference 2010 14 SV Probe “Trio” JEM “VC”
  15. 15. Vertical ‐ Buckling BeamVertical  Buckling Beam MicroProbe: Apollo Vertical JEM: VC Silicon Valley Test Conference 2010 15 SV Probe: Trio
  16. 16. MEMS ‐ VerticalMEMS  Vertical Microfabrica MicroProbeMicrofabrica MicroProbe FormFactor (T1) Silicon Valley Test Conference 2010 16 MicroProbe (Vx-MP)
  17. 17. MEMS ‐ Micro CantileverMEMS  Micro Cantilever Microfabrica FormFactor (T3) MJC (U P b ) Silicon Valley Test Conference 2010 17 http://www.mjc.co.jp/eng/ir/pdf/MJC070226-s.pdf MJC (U Probe) JEM
  18. 18. MEMS ‐ TorsionalMEMS  Torsional Touchdown Technologies (ACCU-TORQ)Touchdown Technologies (ACCU TORQ) SWTW 2010: “Low-Force MEMS Probe Solution for Full Wafer Single Touch Test” Matt Losey Silicon Valley Test Conference 2010 18
  19. 19. Spring PinsSpring Pins http://www.nhkspg.co.jp/eng/mc/products/wlt.html Silicon Valley Test Conference 2010 19 http://www.ksdk.co.jp/eng/spring-probes.htmlJEM VS
  20. 20. MembraneMembrane Silicon Valley Test Conference 2010 20 Cascade Microtech Pyramid Probe
  21. 21. Top Vendors ‐ TechnologyTop Vendors  Technology Revenue per VLSI Research press release Silicon Valley Test Conference 2010 21 Revenue per VLSI Research press release https://vlsiwebserver.vlsiresearch.com/public/cms_pdf_upload/458310.pdf Based upon website and company responses to marketing inquires.
  22. 22. Top Vendors ‐ ApplicationsTop Vendors  Applications Based upon website and company responses to marketing inquires Silicon Valley Test Conference 2010 22 Based upon website and company responses to marketing inquires.
  23. 23. Hot Topics (1)Hot Topics (1) B / b ll d Most I i ti l • Bump / ball damage • Cu probing Inspirational • High currentMost Inspirational Silicon Valley Test Conference 2010 23
  24. 24. Hot Topics (2)Hot Topics (2) • High Frequency / high bandwidthHigh Frequency / high bandwidth – Advanced space transformers Modeling– Modeling – Direct Dock Silicon Valley Test Conference 2010 24
  25. 25. Hot Topics (3)Hot Topics (3) • Operational – lower cost quicker cycle timeOperational  lower cost, quicker cycle time Silicon Valley Test Conference 2010 25
  26. 26. SummarySummary • Device product requirements drive bothDevice product requirements drive both  packaging and test complexity – Essential to partner with suppliers from day one– Essential to partner with suppliers from day one C f l l ti f b d d• Careful selection of probe card vendors – Know strengths & weaknesses for your devices – Technology may limit performance & impact cost – No one solution fits all Silicon Valley Test Conference 2010 26
  27. 27. ResourcesResources • IEEE Semiconductor Wafer Test WorkshopIEEE Semiconductor Wafer Test Workshop www.swtest.org • International Test Conference www.itctestweek.org • My blogs www.hightechbizdev.com www.ateforum.com/tothepoint Silicon Valley Test Conference 2010 27
  28. 28. CreditsCredits Thank you to the vendors who provided photos!Thank you to the vendors who provided photos! • FormFactor h b• Technoprobe • MicroProbe • JEM • SV ProbeSV Probe • Cascade Microtech V i• Verigy Silicon Valley Test Conference 2010 28

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