1. Suneel Muppuri
KAVYA REDDAY P.G
NALLURIHALLI, WHITEFIELD
BANGALORE – 560066
Phone: +91-9994945749
Email: suneel.muppuri@gmail.com
Career Objective
To secure a challenging position in a progressive organization, where I can utilize my knowledge and skills for
the benefit of the organization and myself.
Work experience
Trainee Engineer at “ Si2chip Technologies Pvt.Ltd “ (Aug 2016 – present)
Project Details:
SRAM bit cell
 Design and characterisation of 6T bit cell
 Optimized transistor sizing
 Analysed Iread, SNM, write time..etc.
 The circuit is designed in 40nm CMOS technology
 The tool used to design is TANNER
Characterisation of Flip-Flop
 Enabling set, Reset functionality.
 Setup & hold time calculation with waveforms.
 Designing of shift register and calculation of different timing arcs (slack ,Setup and
hold ,frequency ,delay paths)
Basic MOS simulations &Standard Cells

 Designing and Characterization of basic gates, Transmission gate, Tristate inverter, Ring Oscillator.
Academicqualifications
YEAR COURSE INSTITUTION PERCENTAGE/CGPA
2015-17 M.Tech (VLSI) Vellore Institute of Technology University,
Chennai
7.7
2013 B.Tech (EEE) Priyadarshini institute of technology, Nellore 72.57
2009 Intermediate Sri pratibha Junior College, Ongole 80.7

2. Technical skills
Scripting Language
Operating Systems
EDA Tools
Hardware languages
Area of interest
PERL
DOS, Windows XP/7/8, Linux
CADENCE® (Virtuoso, NC Launch, RC, Encounter)
XILINX® ISE, Model Sim, Tanner
Verilog, Basics of System Verilog
Verification, Physical design, Digital design.
M.Tech Projects:
Efficiency Frequency to digital conversion based simple PLL
 Phase-Locked loops (PLL) serving as a frequency synthesizer locks the output frequency and
generates the square pulse output which is sampled and processed digitally.
 Design of single stage OP-AMP for to eliminates the current mis-matches in the Charge Pump .
 The circuit is designed in 0.18μm CMOS technology
 The tool used to design is CADENCE® Virtuoso
Co – curricular activities
 Presented a poster on fuzzy logic on induction motor in kl university, Vijayawada.
 Attended industrial visit conduct by VIT University BSNL in Chennai.
 Awarded participation certificate for main project in B.tech on vizag steel plant
Extracurricular activities
 Participated in inter college cricket tournaments organized by priyadashini and VIT UNIVERSITY.
Personal details
Father’s Name
Gender
Nationality
Date of Birth
Languages Spoken
Address for Communication
M sreenivasulu
Male
Indian
16th JUNE 1991
English and Telugu
Kavya redday P.G hostel , Nallurihalli ,whitefield,
Bangalore-560066
Declaration
I here by declare that the information given above is true to the best of my knowledge.
(SUNEEL MUPPURI)