Notes of 8051 Micro Controller for BCA, MCA, MSC (CS), MSC (IT) & AMIE IEI- by Arun Umrao

1
8051 MCU
AN INTRODUCTION
Arun Umrao
https://sites.google.com/view/arunumrao
DRAFT COPY - GPL LICENSING

2
Contents
1 Introduction 5
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.2 DPTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.3 Special Function Register (SFR) . . . . . . . . . . . . . 9
1.1.4 Input/Output Ports . . . . . . . . . . . . . . . . . . . 11
1.1.5 bit addressing . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.6 Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.7 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.1 Register Bank . . . . . . . . . . . . . . . . . . . . . . . 29
1.2.2 Bit Addressable RAM . . . . . . . . . . . . . . . . . . 31
1.2.3 Scratch Pad . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . 35
1.2.5 Program Counter . . . . . . . . . . . . . . . . . . . . . 35
1.3 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.3.1 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2 Instructions 39
2.1 Instruction Sets . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1.1 ACALL . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1.2 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.1.3 ADDC . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.1.4 AJMP . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.1.5 ANL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.1.6 CJNE . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1.7 CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.1.8 CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.9 DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1.10 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1.11 DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1.12 DJNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.13 INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.1.14 JB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.1.15 JBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3
2.1.16 JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.1.17 JMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.1.18 JNB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.1.19 JNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.1.20 JNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1.21 JZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1.22 LCALL . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.1.23 LJMP . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.1.24 MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.1.25 MOVC . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.1.26 MOVX . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.1.27 MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.1.28 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.1.29 ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.30 ORL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.31 POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.32 PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.1.33 RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.1.34 RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.1.35 RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.1.36 RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.1.37 RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.1.38 RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.1.39 SETB . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.1.40 SJMP . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.1.41 SUBB . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.1.42 SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.1.43 XCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.1.44 XCHD . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.1.45 XRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3 µC Structure 85
3.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.1.1 TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.1.2 TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.2.1 External Interrupt . . . . . . . . . . . . . . . . . . . . 96
3.2.2 Interrupt Priority Register . . . . . . . . . . . . . . . . 97

4 Introduction
3.2.3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . 98
3.3 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.3.1 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.3.2 SBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.3.3 SCON . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.3.4 PCON . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.4 Assembly Directives . . . . . . . . . . . . . . . . . . . . . . . . 108
3.4.1 Symbol Definition . . . . . . . . . . . . . . . . . . . . . 108
3.4.2 Data Definition . . . . . . . . . . . . . . . . . . . . . . 108
3.5 Assembly in C . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.5.1 Byte Register . . . . . . . . . . . . . . . . . . . . . . . 117
3.5.2 Bit Register . . . . . . . . . . . . . . . . . . . . . . . . 117
3.6 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.6.1 Hex File . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.7 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4 Numerical Problems 123

1.1. INTRODUCTION 5
1Introduction
1.1 Introduction
During the compilation and execution of codes, we use MCU 8051 IDE for the
purpose. Codes given below are never ported into real devices. As we know
that in 8051 MCU, data can be provided in decimal form or in hex form. If
a number is not suffixed with ‘H’ then it is taken as decimal value. In MCU
processor, it is first converts into the hex value and then it is executed. For
example, port P0 in MCU uses memory address 80H. If an instruction has
to access this port, it must identify it by its memory address, that is 0×80
(80H). If instruction is followed by 80 only, then it shall be treated as decimal
80 or 0×50 (50H) and instruction will access memory location other than
port P0.
✞
1 MOV P0 ,#0 FFH ; Set port P0 to input port
CPL 80 ;80th register of RAM
3 ;in hex it is 50H which is not
;address of port P0
5 END
✌
✆
Above example does not complement to the value of port P0 and it comple-
ments to 80th
register, i.e. 80 is in decimal value and it is not the address of
port P0. Again if above program is modified as given below
✞
1 MOV P0 ,#0 FFH ; Set port P0 to input port
CPL 80H ;80H is 128 in decimal. i.e.
3 ;128th register of RAM. It is
;address of port P0
5 END
✌
✆
then it complements to the value at port P0. As 80H represents to 128th
register of RAM that is address of port P0. So be careful while you are using
address as count form (decimal) or in hex form. User’s input data should

6 Introduction
be started with a numeric digit and prefixed with # symbol. Numeric input
data should be started with a numeric digit. See example below:
✞
1 MOV P0 ,#0 FFH ; Valid
MOV P0 ,# FFH ; Invalid
3 MOV P0 ,#80H ; Valid
END
✌
✆
Second line in above codes has invalid input. The input is consider as group
of characters rather than numerical input value. If an input is not prefixed
with # symbol then it is considered as RAM memory address or port address.
20 21
19 22
18 23
17 24
16 25
15 26
14 27
13 28
12 29
11 30
10 31
9 32
8 33
7 34
6 35
5 36
4 37
3 38
2 39
1 40
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Vcc
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
GND P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
EA
ALE
PSEN
Figure 1.1: 8051 pin diagram.
EA is acronym of External Access Enable. This pin is active when it
is low and it is used to access external memory locations 0 to 4K. This pin
must be connected to VCC if MCU wants to access internal ROM and should
connect to GND to access external ROM. 8051 micro controller has two 16
bit registers (PC & DPTR). PSEN is acronym of Program Store Enable
which controls the read signal for external program memory (active when
it is low). ALE is acronym of Address Latch Enable, to latch address
outputs at Ports P0 and P2. XTAL1 and XTAL2 pins are used for crystal
inputs for internal oscillator.

1.1. INTRODUCTION 7
1.1.1 Registers
Registers are used to store information temporarily. 8051 micro controller
unit (MCU) has 8 numbers of 8 bit registers. These eight registers are named
from R0 to R7 to process data. These are default registers. The registers are
used to access the stack pointer registers also. A register can be used as a
pointer to the data. For this purpose only register R0 and R1 are used. Other
registers can not be used to hold the address of operand located in RAM. To
hold the address of RAM location, the registers R0 and R1 must be prefixed
with symbol ‘@’. Special Function Register (SFR) can be accessed by their
names or by their address. Address of register A is 0E0H and of register B is
0F0H. The Carry flag is denoted by ‘C’ in 8051. 8051 MCU as one primary
accumulator and one secondary accumulator. They are represented by A and
B respectively. In 8051 MCU there are two other register banks named as
Bank 0 and Bank 1. Each bank has eight resisters named from R0 to R7.
Bank 0 or Bank 1 can be selected by using instructions like given below:
✞
SET B RS0
2 ; OR
SET B RS1
✌
✆
Application of register 1 and register 2 as RAM address is shown in the
following codes.
✞
1 MOV R1 ,#20H ;Value at register R1 is 0x20
MOV @R1 ,#30H;Use register 1 (R1) value as
3 ;RAM Address , i.e. 0x20
✌
✆
x0 x1 x2 x3 x4 x5 x6 x7
00 00 20 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
20 30 00 01 00 00 00 00 00
28 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
Table 1.1: Memory result.

8 Introduction
1.1.2 DPTR
Data Pointers i.e. DPTR is used either to store or to access 16bit data
from the internal RAM/ROM memory. While using the DPTR, source and
destination registers must have equal size. For example:
✞
1 ;Copy data in DPTR by direct addressing.
MOV DPTR ,#1012H
3 ;Copy low byte into R0 register
MOV R0,DPL
5 ;Copy high byte into R1 register
MOV R1,DPH
7 ;End the program execution
END
✌
✆
The data stored in DPTR is two bytes long. Its Low byte is stored in DPL
register and High byte is stored in DPH register. DPTR is a Special Function
Register (SFR). In instruction
✞
MOV DPTR ,#1012H
✌
✆
Low byte is 12H and high byte is 10H. Therefore DPL register has value 12H
and DPH register has 10H. DPTR acts an intermediate buffer where data
is stored temporarily before it moves from memory to register or register to
memory. See another example:
✞
1 ORG 0
MOV DPTR ,# MYDATA
3 MOV R1 ,#80H ;Start the point of data copying
B1:
5 CLR A ;Clear accumulator
MOVC A,@A+DPTR ;Get ROM data to Accumulator
7 MOV @R1 ,A ;Copy accumulator data to R1
MOV P0,A ;Copy accumulator data to P0
9 JZ EXIT
INC DPTR ;Increase data pointer
11 INC R1 ;Increase ROM location
SJMP B1
13 EXIT:
SJMP $ ;Stay here
15 ORG 30H ;New location of RAM
MYDATA: ;ROM data

1.1. INTRODUCTION 9
17 DB ’This is my word’ ,0
END
✌
✆
1.1.3 Special Function Register (SFR)
Special Function Register (SFR) are used by MCU internally to perform op-
erations. The SFR registers are P0, SP, DPL, DPH, PCON, TCON, TMOD,
TL0, TL1, P1, SCON, SBUG, P2, IE, P3, IP, PSW, ACC and B. In which
only ACC, B, PSW, IP, IE, SCON, TCON and input/output ports are bit
addressable. The bit indices, in hexa-decimal numbers, for the location of
each bit of SFR is given in the following table. These indices are used with
bit addressing instructions only.
D7 D6 D5 D4 D3 D2 D1 D0
P0 87 86 85 84 83 82 81 80
TCON 8F 8E 8D 8C 8B 8A 89 88
P1 97 96 95 94 93 92 91 90
SCON 9F 9E 9D 9C 9B 9A 99 98
P2 A7 A6 A5 A4 A3 A2 A1 A0
IE AF AE AD AC AB AA A9 A8
P3 B7 B6 B5 B4 B3 B2 B1 B0
IP BC BB BA B9 B8
PSW D7 D6 D5 D4 D3 D2 D1 D0
ACC E7 E6 E5 E4 E3 E2 E1 E0
B F7 F6 F5 F4 F3 F2 F1 F0
Table 1.2: Special function registers and indices of their corresponding bit in
hexa-decimal form.
Solved Problem 1.1 Load 24H in the accumulator of 8051MCU and access
its D3 bit as bit addressable mode.

10 Introduction
Solution Accumulator is a bit addressable register and its bit can be
accessed independently. According to this problem, we first load a value 24H
into the accumulator. Then we complement the fourth bit D3 bit of the
accumulator value by using CPL instruction. See the program given below:
✞
MOV A ,#24H ; A=24H = 0010 0100
2 CPL A.3 ; A=2CH = 0010 1100
END ; End the program
✌
✆
Solved Problem 1.2 Write a 8051MCU assembly program for continuous
toggling of D5 port pin of port P0 by accessing address location of port P0.
Solution The address location of port P0 ranges from RAM address 0×80
to 0×87 RAM location and they represent to the corresponding bit from D0
to D7 of the port P0. To toggle the D5 pin we have to complement the value
at 0×85 RAM Location.
✞
1 ORG 0000H
HERE:
3 CPL 85H ; Complement D_5 pin of port P0
CPL 85H ; Complement D_5 pin of port P0
5 JMP HERE; Continuous loop
✌
✆
Solved Problem 1.3 Write a 8051MCU assembly program for continuous
toggling of D6 bit of accumulator by accessing address location method.
Solution The address location of accumulator ranges from RAM address
0×E0 to RAM address 0×E7 and they represent to the corresponding bits,
from D0 to D7 of the accumulator. To toggle the D6 bit of accumulator we
have to complement the value at 0×E6 RAM Location.
✞
ORG 00H
2 HERE:
CPL 0E6H ; Complement D_6 of accumulator
4 CPL 0E6H ; Complement D_6 of accumulator
JMP HERE ; Continuous loop
6 END ; End the program
✌
✆

1.1. INTRODUCTION 11
1.1.4 Input/Output Ports
8051 has four 8-bit long I/O ports named from P0 to P3 and uses 8 pins.
When all or one of the 8 bit are in 0 state, then port or corresponding port
bit acts as output port. Similarly, when all or one of the 8 bit are in state 1,
then the port or port bit acts as input port. By default all ports are input
ports. Before we may start using port, it must be reconfigured. Each bit of
an Port is numbered from ‘Pn.0’ to ‘Pn.7’. Each bit pin of a port (say P0 for
example) can be accessed by its name or addresses, as pins have designated
addresses from 0×80 to 0×87. Port pin bit of port P1 can be accessed by
using either their name or addresses, as pins have designated addresses from
0×90 to 0×97. Similarly port pin bit of port P2 and P3 can be accessed by
using either their name or address as pins have designated addresses from
0×A0 to 0×A7 and from 0×B0 to 0×B7 respectively. Port P0 must be
connected with 10K ohm pull-up register as it is like open drain. Only port
P0 required pull up registers. Port P2 is used with port P0 as upper byte
and provides sixteen bit port address.
✞
MOV A ,#0FFH ;Set A=FF hex
2 MOV P0 ,A ;Reset all bit of port P0 to 1
;Hence it is made to input port.
4 END ;End of program
✌
✆
A port pins can be addressed either by its name or by its address. In the
following example, port pins are accessed by using their addresses.
✞
MOV P0 ,#0 FFH ; set port to FFH
2 CPL 80H ; Compliment the first LSB to 0
4 CPL 90H ; Compliment the first LSB to 0
6 CPL 0A0H ; Compliment the first LSB to 0
8 CPL 0B0H ; Compliment the first LSB to 0
END
✌
✆

12 Introduction
Port Hex Value D7 D6 D5 D4 D3 D2 D1 D0
P0 FE 1 1 1 1 1 1 1 0
P1 FE 1 1 1 1 1 1 1 0
P2 FE 1 1 1 1 1 1 1 0
P3 FE 1 1 1 1 1 1 1 0
87H
P0.7
86H
P0.6
85H
P0.5
84H
P0.4
83H
P0.3
82H
P0.2
81H
P0.1
80H
P0.0
97H
P1.7
96H
P1.6
95H
P1.5
94H
P1.4
93H
P1.3
92H
P1.2
91H
P1.1
90H
P1.0
0A7H
P2.7
0A6H
P2.6
0A5H
P2.5
0A4H
P2.4
0A3H
P2.3
0A2H
P2.2
0A1H
P2.1
0A0H
P2.0
0B7H
P3.7
0B6H
P3.6
0B5H
P3.5
0B4H
P3.4
0B3H
P3.3
0B2H
P3.2
0B1H
P3.1
0B0H
P3.0
Figure 1.2: Port pin addresses of ports P0, P1, P2 and P3.
Similarly, in the following example, port pins are accessed by using their port
name. For example, ‘P1.0’ for first pin of port P1 from LSB side, ‘P3.3’ for
D3 pin of port P3 from LSB side etc.
✞
1 MOV P0 ,#0 FFH ; set port to FFH
CPL P0.0 ; Compliment the first LSB to 0
9 END
✌
✆

P0 FE 1 1 1 1 1 1 1 0
P1 FE 1 1 1 1 1 1 1 0
P2 FE 1 1 1 1 1 1 1 0
P3 FE 1 1 1 1 1 1 1 0
1.1.5 bit addressing
We can access the entire 8-bits of a port or a specific bit of any port without
any alteration in other bits. To access a particular bit of a port, code syntax
is used like :
✞
1 SETB X.Y
✌
✆
Here ‘X’ is port name and ‘Y’ is specific bit number ranging from 0 to 7. For
example, first and second bit of port P1 are accessed by
✞
1 BACK:
CPL P1.0
3 CPL P1.1
SJMP BACk
5 END
✌
✆
Addresses of bit of ports P0 to P3 are given below:
1. Addresses of port bit of port P0 ranges from 80H to 87H
2. Addresses of port bit of port P1 ranges 90H to 97H
3. Addresses of port bit of port P2 ranges A0H to A7H
4. Addresses of port bit of port P3 ranges B0H to B7H
Registers A, B, Process State Word (PSW), IP, IE, ACC, SCON and TCON
are bit addressable.
D7 D6 D5 D4 D3 D2 D1 D0
CY AC RS1 RS0 OV P

14 Introduction
For example to check the Overflow bit, we use instruction as
✞
1 JB PSW.2 <target >
✌
✆
1.1.6 Status Flags
The ALU of 8051 includes five flip-flops which are set or reset after an oper-
ation according to data conditions of the result in the accumulator and other
registers. They are called Carry (CY), Auxiliary Carry (AC), RS1, RS0,
Over Flow (OV) and Parity (P) flags. All these flags are arranged as shown
below and they form a 8-bits long word (i.e. one byte long) that is called as
Process State Word (PSW).
D7 D6 D5 D4 D3 D2 D1 D0
CY AC RS1 RS0 OV P
Carry Flag The carry flag is commonly used to indicate whether an
addition causes a ‘carry’ into the next higher order digit. The carry flag is
also used as a ‘borrow’ flag in subtractions. To set the carry flag, syntax is
used as
✞
1 SETB C
; OR
3 SETB CY
✌
✆
Or via bit addressing of PSW as
✞
1 SETB PSW.7
✌
✆
Auxiliary Carry Flag The auxiliary carry flag indicates a carry out of
third bit of the accumulator. It is present to enable the Decimal Adjust
Accumulator (DAA) to perform its functions. The AC flag can be accessed
by bit addressing of PSW like
✞
1 SETB PSW.6
✌
✆
Register Bank 1 Select Control Bit (RS1) When RS1 is set to high then
register bank 1 is selected. In this bank there are eight registers those can

be accessed by using register’s name, R0 to R7. Both resister banks of the
8051 MCU can not be used simultaneously, hence before selecting of resister
bank 1, resister bank 0 must be deselected. The RS1 bit can be addressed
via bit addressing of PSW like
✞
1 SETB PSW.4
✌
✆
Register Bank 0 Select Control Bit (RS0) When RS0 is set to high then
register bank 0 is selected. In each bank there are eight registers can be
accessed by register name, R0 to R7. Both resister banks of the 8051 MCU
can not be used simultaneously, hence before selecting of resister bank 0,
resister bank 1 must be deselected. The RS0 bit can be addressed via bit
addressing of PSW like
✞
1 SETB PSW.3
✌
✆
Overflow Flag In additions, the Overflow (OV) bit is set if there is a
carry out-of D6 or out-of D7, but not both. The OV flag can be accessed by
bit addressing of PSW like
✞
1 SETB PSW.2
✌
✆
✞
1 MOV A ,#+96 ;96D = 0110 0000
MOV R0 ,#+70 ;70D = 0100 0110
3 ADD A,R0 ;166D= 1010 0110
END ; End of program
✌
✆
In above sum, sum of D6 bit of both numbers sends a carry to D7 bits. But
on the sum of D7 bit of the numbers there is no further carry. Hence overflow
flag is set to high.
Parity Flag Parity is determined by counting the number of one bit set
in the result in the accumulator. Instructions that affect the parity flag set
the flag to one for even parity and reset the flag to zero to indicate odd parity.
The parity flag can be accessed by bit addressing of PSW like
✞
SETB PSW.0
✌
✆
In the following table, some mathematical mnenomics are listed which uses
the PSW flags.

16 Introduction
Operator C AC OV P
ADD Y Y
ADDC Y Y
DA Y Y
DIV Y Y
MUL Y Y
RLC
RRC
SETB
SUBB
1.1.7 Addressing
In 8051 MCU data is copied or moved from register to accumulator or vice-
versa. Data transfer between registers is not acceptable and cause errors.
During data transfter, size of the source register and the destination register
should be same. Before going through the addressing, remember that the
values which are not ends with ‘H’ are taken as decimal number by truncating
trailing characters other than numeric digits. For example
✞
1 MOV A ,#10 ;Copy decimal 10 (hex A) to accumulator
MOV A,#1A ;"Invalid numeric base ‘A ’" if used
3 ; directly. If used via EQU directive
;Copy decimal 1 (hex 1) to accumulator
5 ;and truncate trailing character ’A’
MOV A,#A1 ;A1 is considered as label rather than value
7 ;There shall be error of "symbol not defined"
✌
✆
See the example below:
✞
1 AGE EQU 1A ;EQU directive for AGE
MOV P0 ,# AGE ;AGE is used by immediate addressing
3 MOV P1 ,#15 ;Copy decimal 15 (hex F) to port P1
MOV P2 ,#15H ;Copy hexa -decimal 15 to port P2

5 END
✌
✆
After execution of the above code, the port values will be as given below:
P0 01 0 0 0 0 0 0 0 1
P1 0F 0 0 0 0 1 1 1 1
P2 15 0 0 0 1 0 1 0 1
P3 00 0 0 0 0 0 0 0 0
With above examples it is clear that a data value is either copied from
the port or resister, or it moved to port or register.
Direct Addressing
In direct addressing mode data is transferred from register to accumulator or
vice-versa by identifying the source and destination as indicated in operands.
In direct addressing, source or destination is identified by its name.
✞
1 MOV A ,04H
✌
✆
Here 04H represents to the register R4. Pushing and popping the stack is
allowed only in direct addressing mode. PUSH A is not valid while PUSH
0E0H is valid. Here 0E0H is address of the accumulator. Looping is not
allowed in direct addressing mode. The RAM locations 30H to 7FH are only
accessible by direct addressing mode only. The direct addressing can access
to on-chip memory location.
Indirect Addressing Mode
Registers R0 and R1 are operated as pointer registers. Indirect addressing
is represented by an ‘@’ symbol before R0 and R1. In indirect addressing,
source or destination is identified by its address rather than its name. For
example
✞
1 MOV A,@R0
✌
✆

18 Introduction
Register Direct Addressing
In register direct addressing mode, data is addressed by register name. In
register direct addressing mode, a register is either target for data pasting or
source for data copying. For example
✞
1 MOV A,R4
✌
✆
Here, register R4 of a register bank is addressed directly and its contents are
copied into the accumulator.
Register Indirect Addressing
This mode is similar to the direct address. In this type of addressing, contents
of the memory location registers are copied into the internal registers, i.e.
accumulator or secondary accumulator. The registers in register indirect
addressing mode, register is identified by its address rather than register
name. In This addressing mode, source or destination is the sum of the
base address and the accumulator (acts as index). The base address may be
DPTR or PC. Example with DPTR base:
✞
1 MOV DPTR , #20H
MOV A, #15H
3 MOVC A, @A+DPTR ;A <- M[35H]
✌
✆
Example with PC base:
✞
1 ORG 0100H
100: MOV A, #05H
3 102: MOVC A, @A+PC ; A <- M[108]
103: NOP ; PC Location
✌
✆
Index Addressing
Index addressing mode is widely used in accessing data elements of the look-
up table entries located in the program ROM. The syntax use is
✞
MOVC A,@A+DPTR
✌
✆
In the following example, index addressing is used to return the index values
starting from numeric 1 to 9. Last digit 0 is used to halt the process.

✞
1 ORG 0
MOV DPTR ,#30H ;Fetch the data pointer from address
03H
3 ;It may be used as MOV DPTR ,# MYDATA
also
BACK:
5 CLR A ;Clear the accumulator
MOVC A,@A+DPTR;Get the data pointer value and copy
7 ;in accumulator
MOV P0 ,A ;Copy accumulator value to port P0
9 JZ EXIT ;Exit to loop when digit is 0
INC DPTR ;Increase data pointer value by 1
11 SJMP BACK ;Do it continue
EXIT:
13 SJMP $
ORG 30H ;Address of pointer pointed to data
15 MYDATA:
DB 1,2,3,4,5,6,7,8,9,0
17 END
✌
✆
Immediate Addressing
In immediate addressing mode, data is directly copied into a register or ac-
cumulator. Here source is data itself rather than register name or memory
address from where data is being copied. In immediate addressing data is
added to register or accumulator by using instruction MOV. The operand
data may be numeric constant, a symbolic variable and an arithmetic ex-
pression using constants, symbols and operators. Immediate operands are
preceded by symbol ‘#’. Assembler computes the value and substitutes the
immediate data into the instruction. Following is a way for immediate ad-
dressing of a hex value.
✞
1 MOV R0 ,#19H ; copy hex 19 in register R0 immediately.
✌
✆
The input operand data may be a decimal value for immediate addressing.
But it should be prefixed with symbol ‘#’ and does not suffixed with symbol
‘H’.
✞
1 MOV R0 ,#19 ; copy dec 19 in register R0 immediately.
✌
✆

20 Introduction
A signed number in decimal only can be immediately addressed if a sign (+
or –) is used between ‘#’ symbol and number.
✞
1 MOV R0 ,#+19 ; copy dec +19 in register R0 immediately.
MOV R1 ,# -19 ; copy dec -19 in register R1 immediately.
✌
✆
Remember that in immediate addressing, the value suffixed to symbol ‘#’
must be started with a number not with alphabet, as value with alphabet
is considered as symbol and there shall be compilation error. If input hex
values are like A1, AF or FF, then these values must be prefixed with number
0.
✞
MOV R0 ,# FFH ;Illegal operand and not acceptable
2 MOV R0 ,#0 FFH ;Legal operand and acceptable
✌
✆
For example
✞
MOV A ,#00H ;Store A with 0 value , all bit low
2 CLR C ;Reset carry flag to zero
SETB C ;Set carry flag to one
4 MOV P0,A ;Reset all bit of port P0 to 0
SETB P0.1 ;Set port bit P0.1 to 1
6 ;MOV A,# FFH ;Give error if not commented
MOV A,#0 FFH ;Accepted method , all bit of A are high
8 MOV P0,A ;Set all port bit of P0 to high
END ;End the program
✌
✆
An alpha-numeric symbol can also be used as input data. The symbol is put
in single quotes prefixed with # symbol.
✞
1 MOV A,#’Y’ ;Store A with symbol ’Y’
;’Y’ is equivalent to dec 89
3 MOV P0,A ;Set all port bit of P0 as
;binary value of dec 89
5 END
✌
✆
Address By Register (@)
Only R0 and R1 registers are used as a pointer to the data. Other registers
can not be used for this purpose. When R0 and R1 holds the address of
RAM they are preceded by ‘@’ symbol.

✞
1 ;Set the address of Stack Pointer
MOV SP ,#31H
3 ;Store hex 0AH in R7
MOV R7 ,#0AH
5 ;Store hex 0BH in R6
MOV R6 ,#0BH
7 ;Store hex 0CH in R5
MOV R5 ,#0CH
9 ;Store hex 0DH in R4
MOV R4 ,#0DH
11 ;Push value of R7 at address location 32H
PUSH 7
PUSH 6
PUSH 5
PUSH 4
19 ;Copy RAM address location into R0 & R1
MOV R0 ,#33H
21 MOV R1 ,#34H
;Copy data of RAM address pointed by R0
23 ;into accumulator A
MOV A,@R0
25 ;Copy data of RAM address pointed by R1
;into secondary accumulator B
27 MOV B,@R1
;Halt the execution of program
29 END
✌
✆
Long Addressing
Long addressing is done by using LCALL and LJMP instructions. These
instructions includes 16 bit destination address. The address range for these
instructions is 0000H to FFFFH. The memory range in 8051 MCU is from
00H to FFH, this is why, this type of addressing is called long addressing.

22 Introduction
1.2 RAM
8051 MCU has 128 bytes of RAM and 4K bytes ROM. ROM is used for
program code. 8051 MCU also supports 64K bytes read only external code
memory. It can be accessed through PSEN. 8051 MCU also supported to
64K external data memory that can be read and write by RD and WR.
Code memory is selectable by EA(internal or external). External memory
space is access by using MOVX instruction. These two type of memory
spaces are not shared between code and data. RAM memory is divided into
three parts.
1. First 32 bytes are used as register bank.
2. Next 16 bytes are used for bit addressable read/write memory.
3. Rest of 80 bytes are used for read and write storage. This section is
called scratch pad.
Bytes Location From Location To Label
32 Bytes 00H 1FH Register bank
16 Bytes 20H 2FH Bit addressable
80 Bytes 30H 7FH Scratch pad
Table 1.3: Memory distribution.
Memory location of RAM from 0×30 to 0×7F are used as scratch pad and
also as registers. Addresses from 0×08 to 0×1F addresses are used for stack.
ROM which stores data is not bit addressable while RAM location 0×20 to
0×2F are bit and byte addressable. The instructions which are allowed to
access the RAM address for byte or bit addressing are SETB, CLR, CPL,
JB, JNB, JBC. For bit or byte addressing of RAM registers, the register
can be accessed by its location or by its address. Bit or byte addressing
by location, the location of address is identify by its counting position. For
example, the RAM address 0×20 is 32th
register of the RAM when counting
started from 0. Note that, in the computer counting (indexing) started from
0 instead of 1. In RAM each location is identified by hexadecimal values,
hence if location is identified as a decimal number then it first should be

1.2. RAM 23
converted into equivalent hexadecimal value and then RAM address should
be identified by using this hexa-decimal value. See the example below in
which register location and bit of register is used for bit addressing. Bit
addressable registers are located in RAM memory from 0×20 to 0×2F. This
is why, the first default bit addressable resister is 0×20.
✞
1 MOV 33 ,#200 ; Dec 30 or hex 0x21 address of RAM memory
MOV 21H ,#200; 0x21 address of RAM memory
3 CPL 33 ; D33 bit from 0x20 address of RAM memory
; Memory bit are counted from 0 so that
5 ; D33 bit is D1 bit of 5th byte.
CPL 33.1 ; D1 bit of 0x21 address of RAM memory
7 ; on applying of . (dot) 33 becomes
; RAM register address in decimal
9 ; (equivalent 0x21 in hex)
CPL 35.0 ; D0 bit of 0x23 address of RAM memory
11 ; on applying of . (dot) 35 becomes
; RAM register address in decimal
13 ; (equivalent 0x23 in hex)
✌
✆
To kept out from this confusion, each decimal number should be converted
into equivalent hexadecimal numbers and then memory address should be
identify in the RAM register.
x0 x1 x2 x3 x4 x5 x6 x7
... 00 00 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 CA 00 01 02 00 00 00 00
28 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
In above example, we specify the bit of a register by using ‘.’ (dot). If
we do not use the ‘.’ (dot) as shown above then the address is consider as
bit number started from 0×20 to continue upto 0×2F in group of 8 bits. In

24 Introduction
the following example, fist we reset the value of RAM register identified by
its address 0×20.
✞
MOV 32 ,#00; 0x20 register of RAM memory
✌
✆
The above instruction is not compulsory as default bit addressable registers
are located in RAM from 0×20 to 0×2F. Original memory values at 0×20,
0×21 and 0×22 RAM registers are all zeros. Note that, here counting of bit
of binary numbers is in right-to-left direction and byte-by-byte wise.
✞
1 ;+---------------+----------------+----------------+
;| 0x20 | 0x21 | 0x22 |
3 ;+---------------+----------------+----------------+
;|0|0|0|0|0|0|0|0| 0|0|0|0|0|0|0|0| 0|0|0|0|0|0|0|0|
5 ;+---------------+----------------+----------------+
✌
✆
On complementing the D0 bit of 0×20 RAM register, the value of this register
is changed to 01H.
✞
1 CPL 0 ; D0 bit of 32(0x20) register of RAM memory
;+---------------+----------------+
3 ;| 0x20 | 0x21 |
;+---------------+----------------+
5 ;|0|0|0|0|0|0|0|1| 0|0|0|0|0|0|0|0|
;+---------------+----------------+
7 ;| 01D or 01H | 00D or 00H | SETB state
;+---------------+----------------+
✌
✆
✞
CPL 33.0 ; D0 bit of 0x21 register of RAM memory
2 ;+---------------+----------------+
;| 0x20 | 0x21 |
4 ;+---------------+----------------+
;|0|0|0|0|0|0|0|0| 0|0|0|0|0|0|0|1|
6 ;+---------------+----------------+
;| 00D or 00H | 01D or 01H | SETB state
8 ;+---------------+----------------+
✌
✆

1.2. RAM 25
x0 x1 x2 x3 x4 x5 x6 x7
... 00 00 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 01 00 01 00 00 00 00 00
28 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
Here, noted that, number succeeding to CPL instruction is the bit location
from the current address as CPL is bit addressable instruction. Therefore,
✞
CPL 16
✌
✆
meant that the complementing of 16th
bit (counted from 0) from the current
address. Now,
✞
1 CPL 1 ; D1 bit of 0x20 register of RAM memory
CPL 2 ; D2 bit of 0x20 register of RAM memory
✌
✆
complements the second and third bit from the current address. The memory
value of RAM register identified by RAM address 0×20 is
✞
;+---------------+----------------+
2 ;| 0x20 | 0x21 |
;+---------------+----------------+
4 ;|0|0|0|0|0|1|1|1| 0|0|0|0|0|0|0|0|
;+---------------+----------------+
;+---------------+----------------+
✌
✆
Similarly, other bit are complemented by using CPL instruction as shown
below:
✞
1 CPL 8 ; D0 bit of 33th (0 x21) register of RAM memory
;+---------------+----------------+
3 ;| 0x20 | 0x21 |
;+---------------+----------------+

26 Introduction
5 ;|0|0|0|0|0|1|1|1| 0|0|0|0|0|0|0|1|
;+---------------+----------------+
;+---------------+----------------+
9 CPL 16 ; D0 bit of 34th(0x22) register of RAM memory
;+---------------+----------------+----------------+
11 ;| 0x20 | 0x21 | 0x22 |
;+---------------+----------------+----------------+
13 ;|0|0|0|0|0|1|1|1| 0|0|0|0|0|0|0|1| 0|0|0|0|0|0|0|1|
;+---------------+----------------+----------------+
15 ;| 03D or 03H | 01D or 01H | 01D or 01H |
SETB state
;+---------------+----------------+----------------+
✌
✆
Full program codes are given below:
✞
MOV 33 ,#00;
2 CPL 0 ; D0 bit of first byte
CPL 1 ; D1 bit of first byte
4 CPL 2 ; D2 bit of first byte
CPL 8 ; D0 bit of second byte
6 CPL 16; D0 bit of third byte
✌
✆
The final values at RAM registers at memory addresses 0×20, 0×21 and
0×22 are shown in following memory map.
x0 x1 x2 x3 x4 x5 x6 x7
... 00 00 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 07 01 01 00 00 00 00 00
28 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
For bit or byte addressing of RAM register using addresses of registers is
possible by SETB instruction too. Byte or bit addressing of a RAM address

1.2. RAM 27
is allowed in group of two bytes. RAM addresses 0×20 and 0×21 (register
count numbers 32nd
and 33rd
) are taken as zero group, RAM addresses 0×22
and 0×23 (register count numbers 34th
and 35th
) are taken as first group and
so on. Counting of first register of a group started from 0 to 7 and second
register of the group started from 9 to F. Use of instruction
✞
SETB 14H ; 20 in decimal 2x8+4 = D4 bit
✌
✆
instructs that set the D4 bit of register at address 0 ×22 (register count
number 34th
) of first group. Similarly instruction
✞
1 SETB 1FH
✌
✆
instruct that set the D7 bit of register 0×23 (register count number 35th
)
of first group. Each character of operand of SETB instruction has unique
meaning. For example in instruction
✞
1 SETB 14H
✌
✆
14H has three characters, ‘1’, ‘4’ and ‘H’. Here, ‘1’ stands for first group of
RAM registers, i.e. RAM registers at the address of 0×22 and 0×23. ‘4’
represents to D4 bit of the register group. This bit is falls in the register
address 0×22. ‘H’ represents to hexa-decimal number. Now see the following
self explained example.
✞
1 ;+---------------+----------------+
;|0|0|0|0|0|0|0|0| 0|0|0|0|0|0|0|0| Original state
3 ;+---------------+----------------+
;
5 ;
SETB 14H ; Set the D4 bit of register 0x22 of group one
7 SETB 1FH ; Set the D7 bit of register 0x23 of group one
;+---------------+----------------+
9 ;| 0x22 | 0x23 |
;+---------------+----------------+
11 ;|0|0|0|1|0|0|0|0| 1|0|0|0|0|0|0|0|
;+---------------+----------------+
;+---------------+----------------+
15 SETB 24H ; Set the D4 bit of register 0x24 of group two
SETB 2BH ; Set the D3 bit of register 0x25 of group two

28 Introduction
17 ;+---------------+----------------+
;| 0x24 | 0x25 |
19 ;+---------------+----------------+
;|0|0|0|1|0|0|0|0| 0|0|0|0|1|0|0|0|
21 ;+---------------+----------------+
;| 16D or 10H | 08D or 08H | SETB state
23 ;+---------------+----------------+
SETB 31H ; Set the D1 bit of register 0x26 of group
three
25 SETB 38H ; Set the D0 bit of register 0x27 of group
three
;+---------------+----------------+
27 ;| 0x26 | 0x27 |
;+---------------+----------------+
29 ;|0|0|0|0|0|0|1|0| 0|0|0|0|0|0|0|1|
;+---------------+----------------+
;+---------------+----------------+
33 END
✌
✆
In above example, the bit is access by address. The memory of the MCU
after the execution of above program shall be looked like:
x0 x1 x2 x3 x4 x5 x6 x7
... 00 00 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 00 00 10 80 10 08 02 01
28 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
If operand of SETB is a decimal number then it represents to the bit
location from the D0 bit of 0×20 register. The counting starts from 0 to 7
for first register of the group and 8 to 15 for the second register of the group.
✞
1 SETB 14 ;8+6 => D6 bit of second byte

1.2. RAM 29
SETB 15 ;8+7 => D7 bit of second byte
3 SETB 16 ;8x2+0 => D0 bit of third byte
SETB 17 ;8x2+1 => D1 bit of third byte
5 ;+---------------+----------------+----------------+
;| 0x20 | 0x21 | 0x22 |
7 ;+---------------+----------------+----------------+
;|0|0|0|0|0|0|0|0| 1|1|0|0|0|0|0|0| 0|0|0|0|0|0|1|1|
9 ;+---------------+----------------+----------------+
;| 00D or 00H | 192D or C0H | 03D or 03H |
11 ;+---------------+----------------+----------------+
END
✌
✆
x0 x1 x2 x3 x4 x5 x6 x7
... 00 00 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 00 C0 03 00 00 00 00 00
28 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
To avoid this confusion of the bit position due to different starting
point of counting indices, first convert the location given in decimal
into hexa-decimal equivalent and then count the location of bit
starting from the index 0.
1.2.1 Register Bank
First 32 bytes are further divided in to four parts. Each part is of 8 bytes
long. Each byte of this part is called a register. A group of 8 bytes is called
register bank. The 8 bytes of a register bank are denoted by R0 to R7. Four
register banks are Bank 0, Bank 1, Bank 2 and Bank 3.

30 Introduction
Bank Range Registers
Bank 0 00H-07H R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 08H-0FH R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 10H-17H R0 R1 R2 R3 R4 R5 R6 R7
Bank 3 18H-1FH R0 R1 R2 R3 R4 R5 R6 R7
By default, register bank 0 is selected on power up. The following in-
structions
✞
MOV R0 ,#10 ; copy dec 10 to register
2 ; R0 of register bank 0
END
✌
✆
shall store the data into the register R0 of register bank 0. See RAM memory
x0 x1 x2 x3 x4 x5 x6 x7
00 0A 00 00 00 00 00 00 00
08 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
Table 1.9: RAM memory result.
PSW is used to select the desired register banks. The PSW register is
shown below.
D7 D6 D5 D4 D3 D2 D1 D0
CY AC RS1 RS0 OV P
D3 and D4 bit of PSW register are set as per table given below to select
the register banks.

1.2. RAM 31
Selected Bank RS1 RS0
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1
In the following example, RS0 bit is set high while RS1 bit is cleared.
Thus the register bank 1 is selected.
✞
1 SETB PSW.3 ; set D3 bit to 1
CLR PSW.4 ; set D4 bit to 0
3 MOV R0 ,#10 ; copy decimal 10 to register R0 of
; register bank 1, i.e. 08th RAM Byte
5 END
✌
✆
MOV R0,#10 stores the data in register R0 of register bank 1. See RAM
memory
RAM Address x0 x1 x2 x3 x4 x5 x6 x7
00H 00 00 00 00 00 00 00 00
08H 0A 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
Table 1.10: RAM memory result.
1.2.2 Bit Addressable RAM
The RAM location from 20H to 2FH are bit addressible. It means, all in-
structions whose operands are bit addresses can accessit. bit of bytes from
RAM address 20H to 2FH are identified by their position indices, counted
from 0 to 127. The instruction sets SETB, CLR, CPL, JB, JNB and JBC
are bit addressing instructions.

32 Introduction
RAM Address x0 x1 x2 x3 x4 x5 x6 x7
20H 00 00 00 00 00 00 00 00
28H 00 00 00 00 00 00 00 00
Table 1.11: Bit Addressable RAM.
Each RAM address is 8 bit long. Between RAM addresses 20H to 2FH
(total 16 bytes), bit are counted from 0 to 127, taking first bit (D0 bit) of
RAM address 0×20 as reference position, i.e. zero position. In other words,
D0 bit of 20H RAM address is counted as index 0. Similarly, D1 bit of RAM
address 21H is 9th
bit of bit-addressable RAM from RAM address 0×20.
RAM Address D7 D6 D5 D4 D3 D2 D1 D0
20H 007 006 005 004 003 002 001 000
21H 016 014 013 012 011 010 009 008
... 031 030 029 028 027 026 025 024
2FH 127 125 125 124 123 122 121 120
Table 1.12: Indices of each bit of bit addressable RAM memory addresses.
See the following example
✞
1 SETB 03 ; set D3 bit at 0x20 RAM location
SETB 03H ; set D3 bit at 0x20 RAM location
3 SETB 24 ; set D4 bit at 0x23 RAM location
SETB 18H ; set D4 bit at 0x23 RAM location
5 END
✌
✆
The bit of RAM Address 0×20 and 0×23 will be set as shown in the below
table.

1.2. RAM 33
RAM Address D7 D6 D5 D4 D3 D2 D1 D0 Value
20H 0 0 0 0 1 0 0 0 08H
21H 0 0 0 0 0 0 0 0 00H
22H 0 0 0 0 0 0 0 0 00H
23H 0 0 0 0 0 0 0 1 01H
24H 0 0 0 0 0 0 0 0 00H
The bit indicex from 128 to 255 in decimal count are assigned to SFRs.
Note that these bit indices are also used as hexadecimal values. For example
7th
bit index is equal to 0×07 and 128th
bit index is equal to 0×80 from the
RAM Address 0×20. When an operand is used with BIT ADDRESSABLE
INSTRUCTIONS then it always represents to the indices of bit rather than
RAM address.
When operand of the bit addressing instruction is [128, 255], it access to
bit of Special Function Registers (SFR), i.e. ROM memory.
D7 D6 D5 D4 D3 D2 D1 D0
P0 135 134 133 132 131 130 129 128
TCON 143 142 141 140 139 138 137 136
P1 151 150 149 148 147 146 145 144
SCON 159 158 157 156 155 154 153 152
P2 167 166 165 164 163 162 161 160
IE 175 174 173 172 171 170 169 168
P3 183 182 181 180 179 178 177 176
IP 188 187 186 185 184
PSW 215 214 213 212 211 210 209 208
ACC 231 230 229 228 227 256 225 224
B 247 246 245 244 243 242 241 240

34 Introduction
The corresponding indices in hexa-decimal form are shown in the below
table.
D7 D6 D5 D4 D3 D2 D1 D0
P0 87 86 85 84 83 82 81 80
TCON 8F 8E 8D 8C 8B 8A 89 88
P1 97 96 95 94 93 92 91 90
SCON 9F 9E 9D 9C 9B 9A 99 98
P2 A7 A6 A5 A4 A3 A2 A1 A0
IE AF AE AD AC AB AA A9 A8
P3 B7 B6 B5 B4 B3 B2 B1 B0
IP BC BB BA B9 B8
PSW D7 D6 D5 D4 D3 D2 D1 D0
ACC E7 E6 E5 E4 E3 E2 E1 E0
B F7 F6 F5 F4 F3 F2 F1 F0
Remember that, registers A, B, PSW, IP, IE, ACC, SCON, TCON, all
input/output ports are bit addressable as well as SFR. ROM which holds
program code for execution and PCON are not bit addressable.
1.2.3 Scratch Pad
RAM location from 30H to 7FH are used as scratch pad for data.
x0 x1 x2 x3 x4 x5 x6 x7
30 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00
7F 00 00 00 00 00 00 00 00
Table 1.13: Scratch Pad.

1.2. RAM 35
1.2.4 Stack Pointer
Stack is a section of RAM used to store information. This information may
be data or address. The register used to access the stack is called the stack
pointer (SP) register. It is 8 bit long register and can store values ranging
from 00H to FFH. On power on to 8051, SP contains the value 07H.
Bank Range Registers
Register Bank 0 00H-07H R0 R1 R2 R3 R4 R5 R6 R7
SP & Register Bank 1 08H-0FH R0 R1 R2 R3 R4 R5 R6 R7
Register Bank 2 10H-17H R0 R1 R2 R3 R4 R5 R6 R7
Register Bank 3 18H-1FH R0 R1 R2 R3 R4 R5 R6 R7
08H location of the RAM is first location which is used by the SP (from
Register Bank 1). PUSH instruction is used to add value in the stack and
POP is used to remove the value from the stack. SP is last location of stack,
this is why, SP is incremented by one on each PUSH and decremented by one
on each POP instruction. CPU uses stack to store the last address just after
the CALL instruction before handing over the control to the sub routine.
On RET instruction, control is transfer back to the caller. Caller resumes
the operation from the last address which was stored in stack by CALL. On
power up, register bank 1 and SP shares same memory location in the 8051
RAM. This is why, to use register bank 1, we first change the stack pointer
location to other RAM location by using MOV instruction as
✞
1 MOV SP ,<new RAM location >
✌
✆
Remember that, on each PUSH to stack, stack pointer register is incremented
by 1 and on each POP from the stack, stack pointer register is decremented by
1. There is no decrements protocol for stack pointer. Because, in decrements
protocol, SP may reach to the memory location of default register bank 0
and may violate the memory sharing protocol.
1.2.5 Program Counter
8051 has a program counter register. It is 8 bit long register. It is because,
8051 has 8 bit address line. It holds the address of opcode and operands

36 Introduction
which are to be executed (address of next opcode that would be fetched).
Program counter incremented by one when 8051 executed opcode at the
current address.
1.3 Subroutines
CALL instruction is used to call subroutine. Subroutines are used in seg-
mentation of large codes. Subroutines are group of instructions which are
frequently used in a program. It makes a program more structured and saves
the memory space. When subroutine is called, control is transferred to that
subroutine. After finishing of execution, RET return the control back to the
caller. See below codes
✞
1 ORG 0
;---------Start of Main -----------------
3 MAIN:
MOV A ,#11H
5 LCALL SUBROUT_1
LCALL SUBROUT_2
7 SJMP MAIN
;---------End of Main -------------------
9 ;
;---------Start of SUBROUT_1 ------------
11 SUBROUT_1:
MOV B ,#12H
13 RET ;Return to caller of SUBROUT_1
;---------End of SUBROUT_1 -------------
15 ;
;---------Start of SUBROUT_2 ------------
17 SUBROUT_2:
MOV R0 ,#13H
19 RET ;Return to caller of SUBROUT_2
;---------End of SUBROUT_2 -------------
21 END ;End of the program.
✌
✆

1.3. SUBROUTINES 37
1.3.1 Delay
8051 has two clocks. CPU takes certain number of clock cycle to execute an
instruction. It is called machine cycles. Length of machine cycle is depends
on the frequency of the crystal cycle. In 8051, one machine cycles lasts 12
oscillator period. If a CPU has a crystal frequency of 11.0592MHz then its
machine cycles frequency is computed as
MCF =
11.0592
12
= 921.6KHz
The machine cycle period is
T =
1
MCF
= 1.085µs
It means to read or write one byte, machine takes 1.085µs. Delay is a method
to lapse of time in MCU. Study following program:
✞
1 ;Start of DELAY subroutine
DELAY:
3 ;MOV is one byte instruction here. CPU takes
;one machine cycle to execute this instruction.
5 ;R3 register is stored value 200 immediately.
MOV R3 ,#200
7 ;Start HERE loop
HERE:
9 ;DJNZ is 2 byte instruction. Here DJNZ decrease
;R3 by one and checks whether it becomes zero
11 ;or not. If R3 is not zero , it again reach to
;HERE. By this way it performs 200 times loop
13 ;It means CPU takes 200x2 machine cycles to
;perform this line of instruction code.
15 DJNZ R3,HERE
;RET is two byte instruction. Here it takes two
17 ;machine cycles to execute it.
RET
19 ;By this way total machine cycles used to execute
;DELAY subroutines are 1+400+2 = 403 machine cycles.
✌
✆

2.1. INSTRUCTION SETS 39
2Instructions
2.1 Instruction Sets
Instruction sets guide to MCU for execution of operands following to the
instruction as per instruction’s guideline. Some of the instructions like JBC,
CPL, INC and DEC are read-modify-write type of instruction, because they
read value from the port-bit, register or memory location then modify it
by performing an operation on them and again store it again into the same
port-bit, register or memory location.
2.1.1 ACALL
It is two byte long instruction. ACALL unconditionally calls a subroutine
at the indicated code address. ACALL pushes the address of the instruc-
tion that follows ACALL onto the stack, least-significant-byte first, most-
significant-byte second. The Program Counter is then updated so that pro-
gram execution continues at the indicated address. Since only 11 bit of the
Program Counter are affected by ACALL, calls may only be made to sub
routines located within the same 2K block where the first byte that follows
ACALL is located. The syntax of the instruction is
✞
ACALL <accumulator >, <data or address >
✌
✆
✞
1 HERE: ; HERE subroutine
MOV A,#1AH ; Store value 1A Hex to
Accumulator
3 AGAIN1: ; AGAIN1 subroutine
DEC A ; Decrease accumulator by 1
5 JNZ AGAIN1 ; Jump to AGAIN1 subroutine
ACALL THERE ; Call the DELAY subroutine
7 SJMP HERE ; Do it again and again
THERE: ; THERE subroutine

40 Instructions
9 MOV A,#1AH ; Store value 1A Hex to
Accumulator
AGAIN1: ; AGAIN subroutine
11 DEC A ; Decrease accumulator by 1
JNZ AGAIN1 ; Jump to AGAIN subroutine
13 RET ; Return control to caller
✌
✆
2.1.2 ADD
It is acronym of ADD WITH ACCUMULATOR. If ADD uses registers or reg-
ister address as second operand then it is one byte long instruction, otherwise
it is two byte long instruction. This functions adds the operand value with
accumulator and stores result in accumulator. The operand value remains
unaffected on execution of this instruction. The syntax of the instruction is
✞
ADD <accumulator >,<data or address >
✌
✆
This instruction is used in following ways
✞
1 ADD A,# data
ADD A,<address >
3 ADD A,@R0
ADD A,@R1
5 ADD A,Rn
✌
✆
The carry flags are set accordingly to reflect the result. The Overflow (OV)
bit is set if there is a carry-out of bit 6 or out of bit 7, but not both.
Illustrated Example To add two hexadecimal numbers 10H and 62H are
given below.
✞
1 10H = 00001010
+62H = 01100010
3 ---------------------
72H = 01101100
✌
✆
The code for 8051 MCU is
✞
CLR C ;Clear carry
2 MOV A ,#10H ;Store 10H in accumulator

ADD A ,#62H ;Add hex 62 with accumulator
4 MOV R1 ,A ;Copy contents of accumulator to R1
END ;End the program
✌
✆
2.1.3 ADDC
It is acronym of ADD TO ACCUMULATOR WITH CARRY. If ADDC
uses registers or register address as second operand then it is one byte long
instruction, otherwise it is two byte long instruction. This functions adds
the operand value and carry with accumulator and stores the result value
in accumulator. The operand value remains unaffected. The syntax of the
instruction is
✞
1 ADDC <accumulator >,<data or address >
✌
✆
✞
1 ADDC A,# data
ADDC A,<address >
3 ADDC A,@R0
ADDC A,@R1
5 ADDC A,Rn
✌
✆
ADDC reset the carry flag to zero. The Overflow (OV) bit is set if there is
a carry-out of bit 6 or out of bit 7, but not both.
✞
1 MOV A ,#20H ; A = 00100000
CLR C ; CY = 0
3 ADDC A ,#20H; A+CY +20H = 01000000
MOV R0 ,A ; R0 = 01000000
5 SETB C ; CY = 1
ADDC A ,#20H; A+CY +20H = 01100001
7 MOV R1 ,A ; R1 = 01100001
✌
✆
2.1.4 AJMP
It is short name of ABSOLUTE JUMP. It is two bytes long instruction. The
instruction let the jump to compiler within 2K block unconditionally indi-

42 Instructions
cated by operand address. The new value for the Program Counter is cal-
culated by replacing the least-significant-byte of the Program Counter with
the second byte of the AJMP instruction, and replacing bit 0-2 of the most-
significant-byte of the Program Counter with 3 bit that indicate the page of
the byte following the AJMP instruction. bit 3-7 of the most-significant-byte
of the Program Counter remain unchanged. The syntax of the instruction is
✞
AJMP page <number from 0 to 7>
✌
✆
2.1.5 ANL
It is short name of BITWISE AND. If ANL uses registers or register address
as second operand then it is one byte long instruction, otherwise it is two
byte long instruction. The syntax of the instruction is
✞
1 ANL <operand a>,<operand b>
✌
✆
✞
1 ANL <Internal RAM Address >,A
ANL <Internal RAM Address >,#datae
3 ANL A,# data
ANL A,<Internal RAM Address >
5 ANL A,@R0
ANL A,@R1
7 ANL A,Rn
ANL C,<bit Address >
9 ANL C,/<bit Address >
✌
✆
This instruction performs a bitwise “AND” operation between two operands.
The result is saved in accumulator or Carry flag. The second operand remains
unaffected. Logical “AND” gives result if both of the comparing bit are high,
otherwise bit is cleared.
Illustrated Example Bitwise AND is performed between bit of two num-
bers rather than number itself as a whole. The hexadecimal numbers F2H
and 20H are equals to their binary values 11110010 and 00100000. The Bit-
wise AND is performed bit-by-bit for all the corresponding bit of these two
binary numbers as shown below:

✞
1 F2H = 11110010
20H = 00100000
3 ------------------- AND
20H = 00100000
5 --------------
✌
✆
In above binary AND operation, the output is binary 1 if both operands are
binary 1 otherwise output is binary 0. The 8051MCU code for above AND
operation is given in following example.
✞
1 MOV A ,#0F2H ; A = 11110010
ANL A ,#20H ; A = 00100000
3 END ; End of program
✌
✆
2.1.6 CJNE
It is acronym of COMPARE AND JUMP IF NOT EQUAL. It is three byte
long instruction. The syntax of the instruction is
✞
1 CJNE <accumulator >,<data or address >,<relative address >
✌
✆
This instruction is used in following ways:
✞
1 CJNE A,#data ,<location >
CJNE A,<Internal RAM Address >,<location >
3 CJNE A,@R0 ,<location >
CJNE A,@R1 ,<location >
5 CJNE A,Rn ,<location >
✌
✆
CJNE compares the value of ‘accumulator’ with ‘data’ or value at ‘address’
and branches to the indicated ‘relative address’ if ‘accumulator’ and ‘data’
or value at ‘address’ are not equal otherwise program moves to next instruc-
tion. The Carry bit (C) is set if ‘accumulator’ is less than ‘data’ or value at
‘address’, otherwise it is cleared.
CY = 1 if A < Data
CY = 0 if A ≥ Data
CJNE either sets or clears the Carry bit so we can use JC, JNC, JB, JNB
and JBC etc bit addressable instructions. For this purpose, CJNE is used as

44 Instructions
✞
1 CJNE A,#data ,THERE
THERE:
3 JC HERE
HERE:
5 END
✌
✆
Illustrated Example Go through the following example:
✞
1 MOV R1 ,#12H
MOV R2 ,#25H
3 MOV R4 ,#10H
MOV A,R1
5 CJNE A ,#12H,HERE
MOV B,R2
7 CJNE A ,#11H,HERE
MOV B,R4
9 HERE:
END
✌
✆
First, registers R1, R2 and R4 are stored by hex values 12H, 25H and 10H
respectively. Now the value of register R1 is copied into accumulator A. Ac-
cumulator value is compared with 12H. If both values are equal then there
is no conditional jump to the address of HERE label and next instruction
MOV B,R2 is executed. In the next instruction accumulator value is com-
pared with 11H. Here both values are not equal hence, here a conditional
jump occurs to the address of label HERE. The instruction
✞
MOV B,R4
✌
✆
is skipped here.
2.1.7 CLR
It is acronym of CLEAR. It is two bytes long if it is used in bit addressable
mode, otherwise it is one byte long. CLR clears (sets to 0) all the bit(s) of the
indicated register. If the operand is a bit (including the carry bit), only that
specified bit is affected. Clearing the Accumulator sets the Accumulator’s
value to 0.

✞
1 CLR bit ;Bit
CLR C ;Carry flat
3 CLR A ; Accumulator
✌
✆
Illustrated Example In the following example, Accumulator, Carry flag
and LSB of port P0 are cleared (set to zero) by using CLR instruction.
✞
1 MOV A ,#0FFH ; A = 11111111
CLR A ; A = 00000000
3 SETB C ; Set carry flag high
CLR C ; C = 1
5 CLR P0.0 ; P0= 11111110
✌
✆
2.1.8 CPL
It is acronym of COMPLEMENT. It complements the current value of bit or
register, i.e. it converts binary 0 to binary 1 and vice-versa. It is two bytes
long instruction if it is used as bit addressable mode, otherwise it is one byte
long instruction.
✞
CPL bit ;Bit
2 CPL C ;Carry flat
CPL A ; Accumulator
✌
✆
Illustrated Example CPL function toggles a bit or a register value. In the
following example, accumulator, Carry flag and LSB of port P0 are comple-
mented by instruction CPL.
✞
1 MOV A ,#0FFH ; A = 11111111
CPL A ; A = 00000000
3 CPL C ; C = 1
CPL P0.0 ; PO= 11111110
✌
✆

46 Instructions
2.1.9 DA
It is short form of DECIMAL ADJUST ACCUMULATOR. It is one byte
long instruction. It is just called as DA. This instruction works only with
Accumulator (A).
1. The contents of the accumulator are changed from a binary value to two
4-bit binary coded decimal (BCD) digits. This is the only instruction
that uses the auxiliary flag to perform the binary to BCD conversion,
and the conversion procedure is described below.
2. If the value of the low-order 4-bits in the accumulator is greater than 9
or if Carry flag is set, the instruction adds 6 to the low-order four bits.
3. If the value of the high-order 4-bits in the accumulator is greater than
9 or if the Carry flag is set, the instruction adds 6 to the high-order
four bits.
The Carry bit (C) is set if the resulting value is greater than 0×99, otherwise
it is cleared. In hexadecimal number system, unit and tenth place digit
ranges from 0 to F but in decimal form of number system, unit and tenth
place digit ranges from 0 to 9. If unit place number is larger than 9 then
6 is added to it and carry is transferred to the tenth place digit. When we
convert the hexadecimal number by using DA instruction into BCD form of
number, the unit and tenth place digits are changes and they represent the
equivalent decimal number as 10 × t + d. Here, t is tenth place digit and
d is unit place digit. In hex form of number representation, the maximum
possible unit and tenth place digits shall be F.
✞
1 +---------------+---------------+
| Tenth place | Unit place |
3 +---------------+---------------+
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
5 +---------------+---------------+
| F | F |
7 +---------------+---------------+
✌
✆
But in BCD form of decimal numbers, the maximum binary arrangement
shall be as shown below.
✞
1 +---------------+---------------+

3 +---------------+---------------+
| 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
5 +---------------+---------------+
| 9 | 9 |
7 +---------------+---------------+
✌
✆
This is why, when unit place digit becomes larger than 9 then 6 (binary
0110) is added. Addition of 6 in the LSB bit in hex larger than 9 returns the
remainder as per mathematics
d = (LSB + 06)%16
Carry is transferred to the left place digit. Consider a decimal number 90
(hex 5A) represented as
✞
1 +---------------+---------------+
3 +---------------+---------------+
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
5 +---------------+---------------+
| 5 | A |
7 +---------------+---------------+
✌
✆
The four LSB bit represents to equivalent decimal 10 or hex A (binary 1010).
To convert it in BCD form, decimal 6 or hex 06 (binary 0110) is added to it.
Now the unit place digit becomes
✞
1 1010
+ 0110
3 -------
(1) 0000
5 -------
✌
✆
This carry (1) is added to four MSB bit as
✞
1 0101
+ 0001
3 -------
(0) 0110
5 -------
✌
✆

48 Instructions
Now the final number after DA instruction is ‘0110 0000’ which is decimal
equivalent to 60.
2.1.10 DEC
It is short form of DECREMENTS. It is two bytes long instruction if it is
used with internal RAM Address, otherwise it is one byte long instruction. It
decrements the value of operand by 1. If initial value is 0 then DEC cause to
reset the operand to FF in hex, i.e. operand overflows. It uses one Machine
Cycle (MC). This instruction is used in either of the following forms.
✞
1 DEC A
DEC <Internal RAM Address >
3 DEC @R0
DEC @R1
5 DEC Rn
✌
✆
Illustrated Example Accumulator has stored the value FFH and it is
subsequently decreases three times by one. The final value on accumulator
is FCH.
✞
1 MOV A,#0 FFH ; A = 11111111
DEC A ; A = 11111110
3 DEC A ; A = 11111101
DEC A ; A = 11111100
✌
✆
2.1.11 DIV
It is short form of DIVISION. One byte long instruction. It divides primary
accumulator A by secondary accumulator B. It affects Carry and Over flow
flags to reflect the result. It is used as
✞
1 DIV AB
✌
✆
The quotient is placed in accumulator A and remainder is placed in the sec-
ondary accumulator B. This instruction always clears the Carry flag. Over-
flow flag is set if division is attempted by 0 otherwise it is cleared.
Illustrated Example

✞
1 MOV A ,#0FFH ; A = 11111111
MOV B ,#10H ; B = 00001010
3 DIV AB ; A = 00001111 & B = 00001111
✌
✆
2.1.12 DJNZ
It is short name of DECREMENT AND JUMP IF NOT ZERO. Three bytes
long instruction if uses internal RAM Address otherwise it is two bytes long
instruction. Machine Cycle (MC) used by this instruction is 2. It is used as
either of the any forms given below.
✞
DJNZ <Int RAM Addr >,<relative address >
2 DJNZ Rn,<relative address >
✌
✆
DJNZ decrements the value of register by 1. If the initial value of register
is 0, decrementing register value by one resets this register to 255 (0×FF).
If the new value of register is not 0 the program will branch to the address
indicated by ‘relative address’. If the new value of register is 0 program flow
continues with the instruction following the DJNZ instruction.
Illustrated Example In the following example, port P1 is assign a hex value
55H. RAM memory location identified by 32H address is storing decimal
value 200. A loop is created to decrements the value stored in this address
and jump to LOOP1 is value at this memory address is not zero. Thus a
total 200 loops are performed by the following example.
✞
MOV P1 ,55H
2 MOV 32H ,#200
LOOP1:
4 CPL P1.1
DJNZ 32H,LOOP1
6 END
✌
✆
Another DJNZ example:
✞
MOV A ,#12H ; A = 00010010
2 MOV R0 ,#00H ; R0= 00000000
MOV R2 ,#05H ; R2= 00000101 Counter
4 LCALL DELAY ; Long Call to DELAY

50 Instructions
INC R0 ; Increment R0
6 DJNZ A, HERE ; If A not zero , Jump to HERE
HERE: ; HERE sub routine
8 MOV R1,A ; Copy value of A in R1
JMP THEEND ; JUMP to THEEND
10 DELAY: ; DELAY sub routine
MOV R3 ,#00H ; Set R3 to 0
12 MOV P0,R3 ; Change full port P0 as output port
RLC A ; A = 00100100, if first loop. In -
14 ; corresponding loops A has values -
; according to RLC A
16 MOV P0.1 ,C ; Copy carry flag to outport port
P0.1
DJNZ R2 , DELAY ; If R2 is not zero flow the loop
DELAY
18 RET ; Return the control to LCALL caller
THEEND: ; The end sub routine
20 END ; End of the program
✌
✆
2.1.13 INC
It increments the value of register by 1. It is two bytes long instruction if
uses Internal RAM Address otherwise it is one byte long instruction. It is
used in any of the following methods.
✞
INC A
2 INC <Internal RAM Address >
INC @R0
4 INC @R1
INC Rn
6 INC DPTR
✌
✆
If the initial value of register is 255 (0×FF), incrementing the value will cause
it to reset to 0. In the case of “INC DPTR”, the value two-bytes unsigned
integer value of DPTR is incremented. If the initial value of DPTR is 65535
(0×FFFF), incrementing the value will cause it to reset to 0. Again, the
Carry Flag is NOT set when the value of DPTR “rolls over” from 65535 to
0. In the following example, increment of accumulator take place four times.
✞
MOV A ,#12H ; A = 0001 0010

2 INC A ; A = 0001 0011
INC A ; A = 0001 0100
4 INC A ; A = 0001 0101
INC A ; A = 0001 0110
6 END
✌
✆
2.1.14 JB
JB describes to JUMP IF BIT SET. It is a three bytes long instruction. It
is used as
✞
JB <bit address >,<relative address >
✌
✆
It jumps to the ‘relative address’ if bit is set otherwise program executes con-
tinue with the instruction following the JB instruction. This is an instruction
which can be used to check the overflow flag via PSW register and jump to a
relative address. The overflow (OV) flag is represented by ‘PSW.2’. Syntax
for OV flag and JB instruction is
✞
1 JB PSW.2 ,<relative address >
✌
✆
Illustrated Example See the example below:
✞
1 MOV A ,#12H ; Set A to 12H
MOV P0 ,#00H ; Clear the port P0
3 JB P0.1 ,IFBIT ; If second bit of port P0 is hight then
; jump to IFBIT label. Here no jump occurs
5 SETB P0.1 ; Set second bit of port P0 high
JB P0.1 ,IFBIT ; If second bit of port P0 is hight then
7 ; jump to IFBIT label. Here jump occurs
MOV R0 ,#0 FFH ; No execution
9 MOV R1 ,#0FH ; No execution
IFBIT: ; IFBIT label
✌
✆
In above example, Accumulator and port P0 are added the values 12H and
00H. JB is used to check the D1 bit of port P0. If D1 bit of port P0 is high
then pointer jumps to IFBIT label address.

52 Instructions
2.1.15 JBC
JBC is short form of JUMP IF BIT SET AND CLEAR BIT. It is a three
bytes long instruction. It is used as
✞
1 JBC <bit address >,<relative address >
✌
✆
It jumps to the ‘relative address’ if bit is high, i.e. is ‘1’, otherwise program
executes continue to the instruction following the JBC instruction. It also
reset the bit after execution of the instruction.
Illustrated Example See the example below:
✞
MOV P0 ,#00H ; Clear the port P0
3 JBC P0.1 ,IFBIT ; If second bit of port P0 is hight then
; jump to IFBIT label. Here no jump occurs
5 SETB P0.1 ; Set second bit of port P0 high
JBC P0.1 ,IFBIT; If second bit of port P0 is hight then
7 ; jump to IFBIT label. Here jump occurs
; The target bit is reset to zero
9 MOV R0 ,#0 FFH ; No execution
MOV R1 ,#0FH ; No execution
11 IFBIT: ; IFBIT label
✌
✆
In above example, Accumulator and port P0 are added the values 12H and
00H. JBC is used to check the D1 bit of port P0. If D1 bit of port P0 is high
then pointer jumps to IFBIT label address. Before jumping to the relative
address, the corresponding conditional bit (here, D1 bit of port P0) is cleared.
2.1.16 JC
JC instruction describes to JUMP IF CARRY. It is two bytes long instruc-
tion. It checks the status of carry bit when executed, and jumps to the
address specified by the operand if carry bit is high. It is used as
✞
JC <address >
✌
✆
If the Carry Bit is not set program execution continues with the instruction
following the JC instruction.

✞
CLR C ; Clear carry flag
3 JC IFCARRY ; If carry flag is high or set to 1, jump
; to IFCARRY label. Here no jump occurs
5 SETB C ; Set carry flag high
JC IFCARRY ; If carry flag is high or set to 1, jump
7 ; to IFCARRY label. Here jump occurs
IFCARRY : ; IFCARRY label
✌
✆
2.1.17 JMP
It describes to JUMP TO DATA POINTER PLUS ACCUMULATOR. It is
one byte long instruction. It jumps to the address represented by the sum of
the value of DPTR and the value of the accumulator specified by operand.
It is used as
✞
1 JMP @A+DPTR
✌
✆
Example is given below:
✞
JMP IFNOBIT ; Jump to IFNOBIT label
3 MOV R0 ,#0 FFH ; No execution
MOV R1 ,#0FH ; No execution
5 IFNOBIT : ; IFNOBIT label
✌
✆
2.1.18 JNB
It specified to JUMP IF BIT NOT SET. It is three bytes long bit addressable
instruction. It is used like
✞
JNB <bit address >,<relative address >
✌
✆
This instruction lets the jump to program to specified address if the indicated
bit is not set otherwise program executes continuously.

54 Instructions
Illustrated Example If bit is low, the instruction let the jump to the
program pointer to the label or to the address location. Here, Carry flag is
used to for comparing its bit level by JNB.
✞
SETB C ; Set carry flag bit to high
3 JNB C,IFNOBIT ; If bit is low or set to 0 jump
; to IFNOBIT label. Here no jump occurs
5 CLR C ; Clear carry flag bit
JNB C,IFNOBIT ; If bit is low or set to 0, jump
7 ; to IFNOBIT label. Here jump occurs
IFNOBIT : ; IFNOBIT label
✌
✆
2.1.19 JNC
It specified to JUMP IF CARRY NOT SET. Two byte long instruction. Used
as
✞
1 JNC <relative address >
✌
✆
This instruction let the jump to program to specified address if the carry flag
is not set otherwise executes continuously.
Illustrated Example In this example, JNC compare to carry bit. If carry
bit is low, this instruction jumps to the program pointer to the label or to
the address location. If it is high, program executed continuously to the next
instructions.
✞
1 MOV A ,#12H ; A = 00010010
CLR C ; CY = 0
3 RLC A ; A = 00100100 & CY = 0
JC ENDHERE ; If CY = 1
5 HERE:
RLC A ;1. A = 01001000 & CY = 0
7 ;2. A = 10010000 & CY = 0
;3. A = 00100000 & CY = 1
9 JNC HERE ; If CY = 0
ENDHERE :

11 MOV R0 ,A ; R0 = 00100000 & CY = 1
END
✌
✆
2.1.20 JNZ
It is short name to JUMP IF ACCUMULATOR IS NOT ZERO. It is two
bytes long instruction and used as
✞
JNZ <relative address >
✌
✆
This instruction let the jump to program to specified address if the accumu-
lator contains any value except zero otherwise executes continuously.
Illustrated Example JNZ jumps to a pointer or label when accumulator
is not zero. In the following program, accumulator is stored value 12H.
Accumulator is decrease by one and JNZ compare its value with zero. If
accumulator is not zero then the JNZ instruction jumps to the program
pointer to the label HERE.
✞
1 MOV A ,#12H ; A = 00010010
MOV R0 ,#00H ; R0 = 00000000
3 HERE:
DEC A ; Decrease A by one
5 INC R0 ; R0++
JNZ HERE ; If A>0
✌
✆
2.1.21 JZ
It specified to JUMP IF ACCUMULATOR IS ZERO. It is two bytes long
instruction. Its operand is always accumulator. As there is no zero flag in
8051 MCU hence, accumulator’s zero value is used for comparison to zero.
Used as
✞
1 JZ <relative address >
✌
✆
This instruction let the jump to program to specified address if the accumu-
lator contains zero value otherwise executes continuously.

56 Instructions
Illustrated Example In this example, accumulator is stored value 02H
which is decremented one by one. Each decrements is followed by JZ instruc-
tion. When accumulator decremented to zero, JZ instruction is executed and
program counter reached to HERE label.
✞
1 MOV A ,#02H ; A = 0000 0010
JZ HERE ; No jump
3 DEC A ; A = 0000 0001
JZ HERE ; No jump
5 DEC A ; A = 0000 0000
JZ HERE ; Jump to HERE Label
7 DEC A ; No execution
HERE: ; HERE label
9 MOV A,#0 FFH; Set A = 1111 1111
✌
✆
2.1.22 LCALL
It specified to LONG CALL. It is three bytes long instruction. Used as
✞
LCALL <code address >
✌
✆
LCALL calls a program subroutine. LCALL increments the program counter
by 3 and pushes that value onto the stack. The Program Counter is then
set to the 16-bit value which follows the LCALL opcode, causing program
execution to continue at that address. The target address for LCALL may
be anywhere within the 64K byte address.
Illustrated Example
✞
1 MOV A ,#12H ; A = 00010010
MOV R0 ,#00H ; R0= 00000000
3 MOV R2 ,#05H ; R2= 00000101 Counter
LCALL DELAY ; Long Call to DELAY
5 INC R0 ; Increment R0
DJNZ A, HERE ; If A not zero , Jump to HERE
7 HERE: ; HERE sub routine
MOV R1,A ; Copy value of A in R1
9 JMP THEEND ; JUMP to THEEND
DELAY: ; DELAY sub routine
11 MOV R3 ,#00H ; Set R3 to 0

MOV P0 ,R3 ; Change full port P0 as output port
13 RLC A ; A = 00100100, if first loop. In
; consecutive loops , A has values
15 ; according to RLC A
MOV P0.1 ,C ; Copy carry flag to outport port
P0.1
17 DJNZ R2, DELAY ; If R2 is not zero flow the loop
DELAY
RET ; Return the control to LCALL caller
19 THEEND: ; The end sub routine
END ; End of the program
✌
✆
2.1.23 LJMP
It specified to LONG JUMP. It is a three bytes long instruction. First byte
is opcode and next two bytes are address of location where jump occurs. The
maximum range of jump by this instruction is 0000H to FFFFH. Machine
Cycle (MC) used by this instruction is 2. It is used as
✞
LJMP <code address >
✌
✆
LJMP instructs to the program to jump unconditionally to the specified code
address.
2.1.24 MOV
It copies the contents into destination register directly, indirectly or imme-
diately. It also copies data from source register to destination register with
some restrictions. Machine Cycle (MC) used by this instruction is 1. Its
syntax is
✞
1 MOV <destination >,<source >
✌
✆
The destination may be a count number or hex number. For example
✞
1 MOV 32 ,#200
✌
✆
Here, memory location is specified in counting number. It stores value 200
in the at 32nd
register of RAM’s memory addresses. If second operand is a

58 Instructions
bit, then MOV instruction uses bit addressing of RAM register method to
store the data. For Example,
✞
1 MOV 05,P1.0
✌
✆
In above example, second operand is a bit hence MOV instruction copies the
D0 bit state of port 1 into the 05th
bit started from the 32nd
register of the
RAM or from 0×20 address of the RAM (See RAM section). Again in the
example given below:
✞
1 MOV 32H ,#200
✌
✆
Here memory location is specified in hex numbers. It stores value 200 in
the at 3 × 161
+ 2 × 160
= 50th
register of RAM’s memory addresses. The
MOV instruction uses direct addressing mode and register addressing mode
to address a register. The register bank locations are accessed by the register
names. For example
✞
1 MOV A,4 ; Direct addressing mode
MOV A,R4; Register addressing mode.
3 ; Both are same
✌
✆
Other method of use of MOV instructions are given below:
✞
1 MOV @Rn ,# data ;2 byte long instruction
MOV @Rn ,A ;1 byte long instruction
3 MOV @Rn ,<Internal RAM Address > ;2 byte long instruction
✌
✆
Here only registers R0 and R1 are pointer addressable. Therefore, @Rn
meant for @R0 and @R1.
✞
1 MOV A,# data ;2 byte long instruction
MOV A,@Rn ;1 byte long instruction
3 MOV A,Rn ;1 byte long instruction
MOV A,<Internal RAM Address > ;2 byte long instruction
5 MOV C,<bit Address > ;2 byte long instruction
MOV <bit address >,C ;2 byte long instruction
✌
✆
In above method of application of MOV instruction, accumulator can be
loaded either by direct addressing or by indirect addressing. Note that Carry
flag can be loaded with only bit value not with a byte value.

✞
MOV DPTR ,# data ;3 byte long instruction
✌
✆
Data pointer can handle two byte long data, hence while copying data to and
from DPTR, the source and destination shall of equal size.
✞
1 MOV Rn ,# data ;2 byte long instruction
MOV Rn ,A ;1 byte long instruction
3 MOV Rn ,<Internal RAM Address > ;2 byte long instruction
✌
✆
All registers can accept data from direct addressing method or they can the
stored data stored in the internal RAM location.
✞
1 MOV <Internal RAM Address >,#data ;3 byte long
instruction
MOV <Internal RAM Address >,@Rn ;2 byte long
instruction
3 MOV <Internal RAM Address >,Rn ;2 byte long
instruction
MOV <Internal RAM Address >,A ;2 byte long
instruction
5 MOV <Int RAM Addr >,<Int RAM Addr > ;2 byte long
instruction
✌
✆
MOV also copies data into internal ram address from registers, accumulators
and MOV can also copy data between internal RAM addresses. Source value
during the execution of this instruction does not change. No flags are affected
unless the instruction is moving the value of a bit into the carry bit in which
case the carry bit is affected or unless the instruction is moving a value into
the PSW register. Movement of data between registers by this instruction is
not allowed.
Illustrated Example See the following example, in which MOV instructino
is used to copy the data in accumulator and registers.
✞
1 MOV A ,#20H ; A = 00100000
CLR C ; CY = 0
3 ADDC A ,#20H; A+CY +20H = 01000000
MOV R0 ,A ; R0 = 01000000
5 SETB C ; CY = 1
ADDC A ,#20H; A+CY +20H = 01100001
7 MOV R1 ,A ; R1 = 01100001

60 Instructions
✌
✆
2.1.25 MOVC
It is short name of MOVE CODE BYTE TO ACCUMULATOR. It is one
byte long instructio and can read internal code memory. Its syntax is
✞
MOVC <destination >, <source >
✌
✆
This instruction is used in the form as given below.
✞
1 MOVC A,@A+DPTR
MOVC A,@A+PC
✌
✆
MOVC moves a byte from Code Memory into the Accumulator. The Code
Memory address from which the byte will be moved is calculated by summing
the value of the Accumulator with either DPTR or the Program Counter
(PC). In the case of the Program Counter, PC is first incremented by 1
before being summed with the Accumulator.
✞
ORG 0
2 MOV DPTR ,# MYDATA
B1: CLR A
4 MOVC A,@A+DPTR
MOV P0,A
6 JZ EXIT
INC DPTR
8 SJMP B1
EXIT:
10 SJMP $
ORG 30H
12 MYDATA:
DB ’This is my world’ ,0
14 END
✌
✆
2.1.26 MOVX
It is MOVE DATA TO/FROM EXTERNAL MEMORY (XRAM). It is one
byte long instruction. Its syntax is

✞
MOVX <destination >,<source >
✌
✆
This instruction is used in the form as given below.
✞
1 MOVX @DPTR ,A
MOVX @R0 ,A
3 MOVX @R1 ,A
MOVX A,@DPTR
5 MOVX A,@R0
MOVX A,@R1
✌
✆
MOVX moves a byte to or from External Memory into or from the Accu-
mulator. If destination is @DPTR, the Accumulator is moved to the 16-bit
External Memory address indicated by DPTR. This instruction uses both P0
(port 0) and P2 (port 2) to output the 16-bit address and data. If source is
DPTR then the byte is moved from External Memory into the Accumulator.
If destination is @R0 or @R1, the Accumulator is moved to the 8-bit Ex-
ternal Memory address indicated by the specified Register. This instruction
uses only P0 (port 0) to output the 8-bit address and data. P2 (port 2) is
not affected. If source is @R0 or @R1 then the byte is moved from External
Memory into the Accumulator.
✞
XDATA EQU 2000H
2 XBYTES EQU 10
MOV DPTR ,# XDATA
4 MOV R2 ,# XBYTES
AGAIN:
6 MOVX A,@DPTR
MOV P1 ,A
8 INC DPTR
DJNZ R2,AGAIN
10 END
✌
✆
2.1.27 MUL
It is short form of MULTIPLY. One byte long instruction. It multiplies
accumulator with secondary accumulator. Machine Cycle (MC) used by this
instruction is 4. Its syntax is used as

62 Instructions
✞
MUL AB ; B source (times) and A destination (number)
2 ; AB = B x A ( mathematically)
; So , A is lower level.
✌
✆
It multiples the unsigned value of the Accumulator by the unsigned value
of the “B” register. The least significant byte of the result is placed in the
Accumulator and the most-significant-byte is placed in the “B” register. In
this operation, Carry flag is always reset to 0. The Overflow Flag is set if
the result is greater than 25, otherwise it is cleared.
Illustrated Example Assume two hex numbers 5FH and 10H whose byte
by byte product is 5FH × 10H = 5F0H. Accumulator stores lower byte
while secondary accumulator stores upper byte.
✞
1 MOV A,#5FH ; A = 01011111
MOV B ,#10H ; B = 00001010
3 MUL AB ; A = 11110000 & B = 00000101
✌
✆
2.1.28 NOP
NOP, is acronym of NO OPERATION. It is one byte long instruction. NOP
is generally used only for timing purposes. Absolutely no flags or registers
are affected. Machine Cycle (MC) used by this instruction is 1. NOP is
an instruction that tells to MCU that there is nothing to execute. This
instruction is just skipped by the MCU. This operation is useful in delay
algorithm where each NOP delays the time equivalent to one clock cycle.
Illustrated Example In the following example, there are three preceding
and two succeeding NOP instruction to the MOV instruction. The preceding
instructions are skipped by the MCU and it takes three clock cycles to reach
MOV instruction. After entertaining to MOV instruction, MCU further waits
for two clock cycles before it reached to END instruction and execute it.
✞
NOP
2 NOP
NOP
4 MOV R3 ,#15H
NOP

6 NOP
END
✌
✆
2.1.29 ORG
ORG instruction is used to relocate the location of start of a program. It
sets the location counter to the value specified by the operand expression.
It is included in a program as first instruction. If no ORG instruction is
included before the first instruction or data type in the program, assembly
begins at location zero. Multiple ORG instructions can be included in a
single program.
✞
1 ORG 0000H ;Loading address
LJMP MAIN ;Jump to main program
3
ORG 0013H ;Timer 0 interrupt address
5 SETB P2.1 ;Set high to D1 pin of port P2
MOV R3 ,#10H ;Store R3 with hex 10H.
7 BACK: DJNZ R3 ,BACK;Loop upto 16 times
CLR P2.1 ;Clear the D2 pin of port P2
9 RETI ;Return from interrupt
11 ORG 0030H ;Main program location
MAIN:
13 MOV IE ,#84H ;HW based interrupt , EA high , EX1
HERE:SJMP HERE ;Return to BACK subroutine
15 END
✌
✆
2.1.30 ORL
ORL is short name of Bitwise OR. The OR output is binary 1 if either of
the two operands or both operands are binary 1 and binary 0 otherwise. It
is a binary operator and it operates on binary bit of the operands. See the
example below, in which two integer values 37 and 82 undergone binary OR
operation. First, these two decimal numbers are converted into their binary
equivalent and then bit-by-bit OR operation is performed. The binary result
is again converted into decimal equivalent. Here, the decimal equivalent of
binary result of OR operation on 37 and 82 is 119.

64 Instructions
✞
1 0010 0101 : X=37
0101 0010 : Y=82
3 ---------------- OR
0111 0111 : 119
✌
✆
This operator ORed the value at first register with the value at second register
and stores the result in first register.
✞
ORL <Internal RAM Address >,A ;2 byte long
instruction.
2 ORL <Internal RAM Address >,#data ;3 byte long
instruction.
ORL A,# data ;2 byte long
instruction.
4 ORL A,<Internal RAM Address > ;2 byte long
instruction.
ORL A,@R0 ;1 byte long
instruction.
6 ORL A,@R1 ;1 byte long
instruction.
ORL A,Rn ;1 byte long
instruction.
8 ORL C,<bit address > ;2 byte long
instruction.
✌
✆
See the example given below:
✞
;10H = 00010000
2 MOV A ,#10H ;Copy hex 10H into ACC
;11H = 00010001
4 MOV R1 ,#11H ;Copy hex 11H into R1
;10H = 00010000
6 ;11H = 00010001
;----------------OR
8 ;11H = 00010001
ORL A,R1 ;Get OR of 10H and 11H
✌
✆
2.1.31 POP
It is two bytes long instruction. Its syntax is

✞
1 POP <Internal RAM Address >
✌
✆
POP removes the last value placed on a stack and copied it into the internal
RAM address specified by its operand. Address of last value at stack pointer
is decreased by one after each POP.
✞
1 ;Begining of stack pointer register in RAM memory
MOV SP ,#31H
3 ;Store data into registers
MOV R2 ,#25H
5 MOV R1 ,#12H
MOV R4 ,#10H
7 ;Push data from register R2 into stack
;pointer addressed at 31H in internal RAM
9 PUSH 2 ; 25H
;Push data from register R1 into address
11 ;of next address of stack pointer
PUSH 1 ; 12H
13 ;Push data from register R4 into address
;of next address of stack pointer
15 PUSH 4 ; 10H
;Pop last value from stack pointer
17 ;into the addressed at 09H in RAM
;Here last value on stack is 10H
19 POP 09H
;Pop next last value from stack pointer
;Here next value in stack is 12H
23 POP 10H
;Pop next last value from stack pointer
;Here next value in stack is 25H
27 POP 11H
✌
✆

66 Instructions
x0 x1 x2 x3 x4 x5 x6 x7
00 00 12 25 10 00 00 00 00
08 00 10 00 00 00 00 00 00
10 12 25 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 00 00 01 00 00 00 00 00
28 00 00 00 00 00 00 00 00
30 00 00 25 12 10 00 00 00
... 00 00 00 00 00 00 00 00
The output can be view in the RAM address started from 32H. Only direct
addressing mode is allowed for popping the stack. Note that while using
POP instruction, we should have knowledge of number of elements present
in stack pointer, otherwise POP starts fetching the value beyond the stake
pointer values.
✞
1 MOV SP ,#31H
MOV R2 ,#25H
3 MOV R1 ,#12H
MOV R4 ,#10H
5 PUSH 2 ; Value 25H
PUSH 1 ; Value 12H
7 PUSH 4 ; Value 10H
POP 10H ; Value 10H
9 POP 11H ; Value 12H
POP 12H ; Value 25H
11 POP 13H ; Fetches value from RAM address 0x31H
POP 14H ; Fetches value from RAM address 0x30H
13 POP 15H ; Fetches value from RAM address 0x2FH
END
✌
✆

2.1.32 PUSH
It is two byte long instruction. Its syntax is
✞
PUSH <Internal RAM Address >
✌
✆
PUSH “pushes” the value of the specified ‘Int. RAM Address’ onto the stack.
PUSH first increments the value of the Stack Pointer by 1, then takes the
value stored in ‘Int. RAM Address’ and stores it in Internal RAM at the
location pointed to by the incremented Stack Pointer.
✞
1 ;Begining of stack pointer
;register in RAM memory
3 MOV SP ,#31H
;Add data into registers
5 MOV R2 ,#25H
MOV R1 ,#12H
7 MOV R4 ,#10H
;Push data from register R2 into stack
9 ;pointer at address 31H in internal RAM
PUSH 2
11 ;Push data from register R1 into stack
;pointer at next address of stack pointer
13 PUSH 1
;Push data from register R4 into stack
15 ;pointer at next address of stack pointer
PUSH 4
✌
✆
The output can be view in the RAM address started from 32H. Only direct
addressing mode is allowed for pushing the stack.

68 Instructions
x0 x1 x2 x3 x4 x5 x6 x7
00 00 12 25 10 00 00 00 00
08 00 00 00 00 00 00 00 00
10 00 00 00 00 00 00 00 00
18 00 00 00 00 00 00 00 00
20 00 00 01 00 00 00 00 00
28 00 00 00 00 00 00 00 00
30 00 00 25 12 10 00 00 00
... 00 00 00 00 00 00 00 00
2.1.33 RET
It is short form of RETURN FROM SUBROUTINE. It is two bytes instruc-
tion. RET is used to return from a subroutine previously called by LCALL
or ACALL. Program execution continues at the address that is calculated
by popping the topmost 2 bytes off the stack. The most-significant-byte is
popped off the stack first, followed by the least-significant-byte. Machine
Cycle (MC) used by this instruction is 2. It is the last instruction of a
sub-routine. It syntax is
✞
RET
✌
✆
Illustrated Example
✞
1 MOV A ,#12H ; A = 00010010
MOV R2 ,#05H ; R2= 00000101 Counter
3 LCALL DELAY ; Long Call to DELAY
JMP THEEND ; JUMP to THEEND
5 DELAY: ; DELAY sub routine
MOV R3 ,#00H ; Set R3 to 0
7 MOV P0,R3 ; Change full port P0 as output port
RLC A ; A = 00100100, if first loop. In -
9 ; corresponding loops A has values -

; according to RLC A
11 MOV P0.1 ,C ; Copy carry flag to outport port
P0.1
DJNZ R2, DELAY ; If R2 is not zero flow the loop
DELAY
13 RET ; Return the control to LCALL caller
THEEND: ; The end sub routine
15 END ; End of the program
✌
✆
2.1.34 RETI
It is acronym of RETURN FROM INTERRUPT. It is one byte long in-
struction. RETI is used to return from an interrupt service routine. RETI
first enables interrupts of equal and lower priorities to the interrupt that is
terminating. Program execution continues at the address that is calculated
by popping the topmost 2 bytes off the stack. The most-significant-byte
is popped off the stack first, followed by the least-significant-byte. RETI
functions identically to RET if it is executed outside of an interrupt service
routine. It s syntax is
✞
1 RETI
✌
✆
On execution of RETI, TCON.1 and TCON.3 bit are cleared, indicating that
the interrupt is finished and MCU is ready for another interrupt. During
the execution of interrupt subroutine, interrupt pins are ideally ignored, no
matter how many times and how long it makes high-to-low transitions.
Illustrated Example For interrupt of MCU via Interrupt Enable (IE) Spe-
cial Function Register (SFR), we use the roll over state of the Timer 0. On
roll over, TF0 flag is set to high. If interrupt flag (ET0) for Timer 0 (TF0)
is set high then on rollover, MCU assumed that it is interrupted for Timer
0. TF0 reset to low on call of interrupt. The MCU gets the address of ROM
location fixed for Timer 0 (TF0) interrupt. It is 0003H. Now MCU executes
the subroutine started from the ROM address 0×0003. On execution of RETI
instruction, it returns to the original address from where it was interrupted.
✞
3

70 Instructions
ORG 000BH ;Timer 0 interrupt address
5 CPL P2.1 ;CPL to D1 pin of port P2
RETI ;Return from interrupt
7
ORG 0030H ;Main program location
9 MAIN:
MOV TMOD ,#02H ;Timer 1 mode 2
11 MOV P0 ,#0 FFH ;Make port P0 input port
MOV TH0 ,#90H ;Load TH of Timer 0 with 90H
13 ;+----------------------------------------------+
;| IE |
15 ;+-----+-----+-----+----+-----+-----+-----+-----+
;| EA | - | ET2 | ES | ET1 | EX1 | ET0 | EX0 |
17 ;+-----+-----+-----+----+-----+-----+-----+-----+
;| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
19 ;+-----+-----+-----+----+-----+-----+-----+-----+
MOV IE ,#82H ;SW based interrupt , EA high ,
21 ;ET0 high enables interrupt
;via TF0 flag.
23 SETB TR0 ;Start Timer 0
25 BACK:
MOV A,P0 ;Copy input into ACC from P0
27 MOV P1,A ;Mov data of ACC into P1
SJMP BACK ;Return to BACK subroutine
29 END
✌
✆
There is another example in which external interrupt is applicable.
✞
3
ORG 0013H ;Timer 0 interrupt address
5 SETB P2.1 ;Set high to D1 pin of port P2
MOV R3 ,#10H ;Store R3 with hex 10H.
7 BACK: DJNZ R3,BACK;Loop upto 16 times
CLR P2.1 ;Clear the D2 pin of port P2
9 RETI ;Return from interrupt
11 ORG 0030H ;Main program location
;+----------------------------------------------+

13 ;| IE |
;+-----+-----+-----+----+-----+-----+-----+-----+
15 ;| EA | - | ET2 | ES | ET1 | EX1 | ET0 | EX0 |
;+-----+-----+-----+----+-----+-----+-----+-----+
17 ;| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
;+-----+-----+-----+----+-----+-----+-----+-----+
19 MAIN:
MOV IE ,#84H ;HW based interrupt , EA high ,
21 ;EX1 high enables interrupt
;via IE1 flag.
23 HERE:SJMP HERE ;Return to BACK subroutine
END
✌
✆
In above example, EA and EX1 flags of IE SRF are set high. EA allows
interrupts and EX1 allows the external interrupt via IE1 flag which is D3 bit
of TCON SRF. On interrupt via IE1 flag or TCON.3 flag, the MCU gets the
address of External Hardware Interrupt 1 (INT1), which is 0013H. On inter-
rupt, MCU starts execution from the address of 0×0013 and returns to the
location from where it was interrupted when RETI instruction is executed.
2.1.35 RL
It is short form of ROTATE ACCUMULATOR LEFT. It is one byte long
instruction. Syntax for this instruction is
✞
RL A
✌
✆
It shifts the bit of accumulator to left. The bit D7 bit is removed from its
place and postfixed after the bit D0.
Illustrated Example Consider an example as given below:
✞
1 MOV A ,#25H ; A = 0010 0101
RL A ; A = 0100 1010
3 RL A ; A = 1001 0100
✌
✆
In above example, D7 bit is removed from its place and placed just after the
bit D0. The new byte thus formed is the result of RL instruction. If RL
instruction is performed by four times then four bit of LSB side and four bit
of MSB side are swapped (like SWAP instruction).

72 Instructions
✞
MOV A ,#25H ; A = 0010 0101
2 RL A ; A = 0100 1010
RL A ; A = 1001 0100
4 RL A ; A = 0010 1001
RL A ; A = 0101 0010 (swapped )
✌
✆
2.1.36 RLC
It is short form of ROTATE ACCUMULATOR LEFT THROUGH CARRY.
It is one byte long instruction. Its syntax is
✞
RLC A
✌
✆
It shifts the bit of the Accumulator to the left. Most significant bit D0 is
loaded on Carry flag and original value of Carry flag is post-fixed after bit D0.
This function can be used to quickly multiply a byte by 2. This instruction
can also be used to get in or out the bytes from I/O ports or port pins
through carry bit taking MSB first. Assume initially, a register has values in
hex represented by bit D7 to D0 where D7 is MSB. These places are assumed
as original places of data bit and Carry. The carry bit is represented by CY .
D7 D6 D5 D4 D3 D2 D1 D0
CY
I/O
Pn
After the execution of instruction RLC for the register, all bit shift to
leftward. The CY bit acquires the original place of bit D0, D0 acquires the
original place of D1 and so on. Bit D7 acquires the place of CY. If we want
to put the MSB at output port. Instruction MOV is used as
✞
1 MOV Pn.X ,C
✌
✆
Here Pn is port either P0 or P2, X is any port bit of its 8 port bits. By this
way at output port, bit D7 is obtained.

D6 D5 D4 D3 D2 D1 D0 CY
D7
I/O
Pn D7
After the execution of instruction RLC for the register again, all bit shift
to leftward. The CY bit acquires the original place of bit D1, D1 acquires
the original place of D2, D7 acquires the original place of D0 and so on. Bit
D6 acquires the place of CY. If we want to put the MSB at output port.
Instruction MOV is used as
✞
1 MOV Pn.X ,C
✌
✆
By this way at output port, bit D6 is obtained. Now, two bit D7 and D6 are
obtained at output port in which MSB comes first.
D5 D4 D3 D2 D1 D0 CY D7
D6
I/O
Pn D7
D6
Next step is performed similarly and three consecutive bit are obtained
at output port in which MSB comes first.
D4 D3 D2 D1 D0 CY D6
D7
D5
I/O
Pn D7
D6
D5
Illustrated Example
✞
1 MOV A ,#25H ; A = 00100101, C=0
RLC A ; A = 01001010, C=0
3 RLC A ; A = 10010100, C=0

74 Instructions
RLC A ; A = 00101000, C=1
5 RLC A ; A = 01010001, C=0
RLC A ; A = 10100010, C=0
✌
✆
2.1.37 RR
It is acronym of ROTATE ACCUMULATOR RIGHT. It is one byte long
instruction. Syntax of this instruction is
✞
1 RR A
✌
✆
It shifts the bit of the Accumulator to the right. The least significant bit D0
is removed from its place and prefixed before the most significant bit D7.
Illustrated Example Consider an example as given below:
✞
1 MOV A ,#25H ; A = 0010 0101
RR A ; A = 1001 0010
3 RR A ; A = 0100 1001
END
✌
✆
In above example, D0 bit is removed from its place and placed just before
the bit D7. The new byte thus formed is the result of RR instruction. If RR
instruction is performed by four times then four bit of LSB side and four bit
of MSB side are swapped (like SWAP instruction).
✞
MOV A ,#25H ; A = 0010 0101
2 RR A ; A = 1001 0010
RR A ; A = 0100 1001
4 RR A ; A = 1010 0100
RR A ; A = 0101 0010 (swapped )
6 END
✌
✆
2.1.38 RRC
It is short form of ROTATE ACCUMULATOR RIGHT THROUGH CARRY.
It is one byte long instruction. Its syntax is
✞
RRC A
✌
✆

It shifts the bit of the Accumulator to the left. Most significant bit D0 is
loaded on Carry flag and original value of Carry flag is prefixed after bit D0.
This function can be used to quickly multiply a byte by 2. This instruction
can also be used to get in or out the bytes from I/O ports or port pins
through carry bit taking LSB first. Assume initially, a register has values in
hex represented by bit D7 to D0 where D0 is LSB. These places are assumed
as original places of data bit and Carry. The carry bit is represented by CY .
D7 D6 D5 D4 D3 D2 D1 D0 CY
I/O
Pn
After the execution of instruction RRC, all bit shift to rightward. D0
acquires the original place of CY , CY acquires the original place of D7 and
so on. If we want to put the LSB at output port. Instruction MOV is used
as
✞
1 MOV Pn.X ,C
✌
✆
Here Pn represents to a port of specific number n ranging from zero to four.
For example, P0 is first port, P2 is third port etc. X is any port pin of its 8
port pins. By this way at output port, bit D0 is obtained.
D7 D6 D5 D4 D3 D2 D1 D0
I/O
Pn
CY
D0
After the execution of instruction RRC again, all bit shift to rightward.
The CY bit acquires the original place of bit D6, D6 acquires the original
place of D5, D0 acquires the original place of D7 and so on. Bit D1 acquires
the original place of CY . If we want to put the next LSB at output port.
Instruction MOV is used as
✞
1 MOV Pn.X ,C
✌
✆

76 Instructions
By this way at output port, bit D1 is obtained. Now, two bit D0 and D1 are
obtained at output port in which LSB comes first.
D7 D6 D5 D4 D3 D2 D1
I/O
Pn
D0 CY
D0
D1
By this way, we can get the other bit consecutively.
✞
1 MOV A ,#25H ; A = 00100101, C=0
RRC A ; A = 00010010, C=1
3 RRC A ; A = 10001001, C=0
RRC A ; A = 01000100, C=1
5 RRC A ; A = 10100010, C=0
RRC A ; A = 01010001, C=0
✌
✆
2.1.39 SETB
It sets the carry bit or bit address. It is used as
✞
1 SETB C ;1 byte long instruction.
SETB <bit address > ;2 bytes long instruction.
✌
✆
Illustrated Example Here is an example in which Carry flag is first clear
and then it is set to high. The carry bit is sent to the first bit of port P0.
✞
MOV A ,#00H
2 CLR C
SETB C
4 MOV P0,A
SETB P0.1
6 END
✌
✆

Notes of 8051 Micro Controller for BCA, MCA, MSC (CS), MSC (IT) & AMIE IEI- by Arun Umrao

Notes of 8051 Micro Controller for BCA, MCA, MSC (CS), MSC (IT) & AMIE IEI- by Arun Umrao

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Notes of 8051 Micro Controller for BCA, MCA, MSC (CS), MSC (IT) & AMIE IEI- by Arun Umrao