Notes of 8085 micro processor Programming for BCA, MCA, MSC (CS), MSC (IT) & AMIE IEI- by Arun Umrao

1
8085 µP
AN INTRODUCTION
Arun Umrao
https://sites.google.com/view/arunumrao
DRAFT COPY - GPL LICENSING

2
Contents
1 µP Introduction 5
1.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.2 Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.4 M-Cycle & T-State . . . . . . . . . . . . . . . . . . . . 9
1.1.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . 10
1.2 Stack & Subroutines . . . . . . . . . . . . . . . . . . . . . . . 12
2 Interrupt & Instructions 15
2.1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Interrupt Table . . . . . . . . . . . . . . . . . . . . . . 15
2.2 RIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 Instruction Sets . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.1 One Byte Instruction Set . . . . . . . . . . . . . . . . . 19
2.5.2 Two Bytes Instruction Set . . . . . . . . . . . . . . . . 77
2.5.3 Three Bytes Instruction Set . . . . . . . . . . . . . . . 88
3 Directives 105
3.1 Assembly Directives . . . . . . . . . . . . . . . . . . . . . . . . 105
3.1.1 Symbol Definition . . . . . . . . . . . . . . . . . . . . . 105
3.1.2 Data Definition . . . . . . . . . . . . . . . . . . . . . . 105
3.1.3 Memory Reservation . . . . . . . . . . . . . . . . . . . 106
3.1.4 Conditional Assembly . . . . . . . . . . . . . . . . . . 106
3.1.5 Assembler Termination . . . . . . . . . . . . . . . . . . 106
3.1.6 Location Counter Control . . . . . . . . . . . . . . . . 107
3.1.7 Program Linkage . . . . . . . . . . . . . . . . . . . . . 107
3.2 Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.2.1 Time Delay . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3.1 Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3.2 IF Like . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3
3.3.3 FOR Like . . . . . . . . . . . . . . . . . . . . . . . . . 111
4 Numerical Problems 113

1.1. STRUCTURE 5
1µP Introduction
1.1 Structure
8085 µP is a 8 bit microprocessor and it is manufactured with N-MOS tech-
nology. It has 16-bit address bus and hence can address up to 216
= 65536
bytes (64KB) memory locations A0 to A15. The first 8 lines of address bus
are multiplexed as AD0 to AD7 and 8 lines of data bus are addressed by D0
to D7. It supports external interrupt (hardware interrupt) request. It has
a 16 bit program counter (PC) and 16 bit stack pointer (SP). It requires a
signal +5V power supply and operates at 3.2 MHZ single phase clock. It is
enclosed with 40 pins DIP (Dual in line package).
1.1.1 Register
8085 has six general purpose registers to store 8-bit data. These are identified
as B, C, D, E, H and L. They are combined as register pairs BC, DE and HL
to perform 16-bit operations. These registers can be assigned data by using
data copying instructions. Here B, D and H are higher order register while
C, E and L are lower order registers. When value from registers is stored into
memory, the content of lower order register is stored in lower memory location
and contents of higher order register is stored in higher memory location.
Similarly, the contents of lower memory location and higher memory location
are copied into lower order register and higher order register respectively.

6 µP Introduction
Register Binary Equiv Register Pairs Binary Equiv
B 000 BC 01
C 001 DE 01
D 010 HL 10
E 011 AF or SP 11
H 100
L 101
A 111
M 110
Table 1.1: Registers.
Accumulator The accumulator is 8-bit register that is part of the arith-
matic/logic unit (ALU). This register is used to store 8-bit data and to per-
form arithmetic and logical operations. The result of an operation is stored
in the accumulator. It is also identified as register A.
Program Counter 8085 MPU has a program counter register. It is 16
bits (2 bytes) long register. It holds the address of opcode and operands
which are to be executed. Program counter incremented by a value such
that it will point to the address of the next opcode, that would be executed
after successfull execution of current opcode. Let us assume that an opcode
at address 0×C000 is being executed. So at this moment of time, program
counter will have value 0×C000. If this opcode is part of two bytes instruction
then next address will be linked to current opcode. Therefore, after successful
execution of this current opcode, program counter will point the memory
address 0×C002. See the following instructions
✞
1 MVI H,04H ;Store 04H in register H
MVI L,1AH ;Store 1AH in register L
✌
✆
in which MVI is two bytes long instruction. The memory arrangement will
be look like

1.1. STRUCTURE 7
0 1 2 3 4 5 6 7 8 9 A B C D E F
C000 26 04 2E 1A 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
C050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
CFF0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 10
The initial program counter value is 0×C000. On execution of first MVI
instruction, its value increases to 0×C002 and after execution of second MVI
instruction, its value becomes to 0×C004.
Stack Pointer It is 16-bit long memory pointer for stack memory. On
PUSH instruction, it holds the address of currently stored data into the
memory. On POP instruction, it holds the address of next memory location
from where data will be read.
1.1.2 Status Flags
The ALU of 8085 includes five flip-flops which are set or reset after an oper-
ation according to data conditions of the result in the accumulator and other
registers. They are called Sign (S), Zero (Z), Auxiliary Carry (AC), Parity
(P) and Carry (CY) flags. The most commonly used flags are Zero, Parity
and Sign. By default all flags are set to zero. All these flags are arranged
as shown below and these 8-bits form one byte word that is called Process
State Word (PSW).
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Sign Flag Bit D7 of a result that is stored in the accumulator after
arithmetic operations indicates whether stored value is either positive or
negative. If this bit is zero then it indicates a positive value, similarly if this
bit is one then it indicates a negative value. This value is duplicated in the

8 µP Introduction
sign flag so that conditional jump or call or return instructions can test for
positive or negative values.
Zero Flag Certain instructions set the zero flag to one to indicate that
the result in the accumulator contains all zeros. These instructions, reset the
flag to zero if the result in the accumulator is other than zero.
Auxiliary Carry Flag The auxiliary carry flag indicates a carry out of
bit D3 of the accumulator. It is present to enable the Decimal Adjust Accu-
mulator (DAA) to perform its functions.
Parity Flag Parity is determined by counting the number of binary digits
1 in the stored value at the accumulator. Instructions that affect the parity
flag set this flag to one for even parity and reset this flag to zero to indicate
odd parity.
Carry Flag The carry flag is commonly used to indicate whether an
addition causes a ‘carry’ into the next higher order digit. The carry flag is
also used as a ‘borrow’ flag in subtraction.
1.1.3 Memory
In computing, memory refers to those computer hardware devices used for
storing information for immediate use in a computer. Computer memory
operates at a high speed. Contents of the computer memory can be trans-
ferred to secondary storage. The term “memory” means “primary storage”
or “main memory”, is often associated with addressable semiconductor mem-
ories. There are two main kinds of semiconductor memories, (i) volatile and
(ii) non-volatile. Most semiconductor memories are organized into memory
cells or bistable flip-flops, each storing one bit (0 or 1). Flash memory or-
ganization includes both one bit per memory cell and multiple bits per cell.
The memory cells are grouped into words of fixed word length, for example
1, 2, 4, 8, 16, 32, 64 or 128 bit. Each word can be accessed by a binary
address of N bit, making it possible to store 2 raised by N (2N
) words in
the memory. In 8085µP, requires an 8-bit wide memory word (data size)
and uses 16-bit address to select a register called memory location. Memory
location is identified by the contents of the 16 bit long HL register pair. The
contents of the HL register pair is known as address of the memory location.

1.1. STRUCTURE 9
Addressable Memory
Location of data in memory is accessed by its address only. A microprocessor
itself never stores values in its memory but it always either retrieves values
from storage memory or stores values into the memory. µP first identifies
the location of memory by address and then µP either reads data from this
memory address or write data into this memory address. Address bus is used
to communicate with addresses. For example a 8 bit address bus can locate
only 28
= 512 different one byte long addresses, like 10001010, 00101010
etc. A 16 bit address bus can locate only 216
= 65536 different two bytes
long addresses, like 10001010 00101010, 10001011 00101010 etc. The maxi-
mum possible memory size that can be accessed by microprocessor with help
of address bus is called addressable memory. If memory size is more than
the addressable memory, then those memory locations/addresses which are
beyond the maximum addressable memory locations are remain unused.
1.1.4 M-Cycle & T-State
CPU takes certain number of clock cycle to execute an instruction. It is
called machine cycles. Length of machine cycle is depends on the frequency
of the crystal cycle. Assume that one machine cycles lasts in n oscillator
period. If a CPU has a crystal frequency of fHz then its machine cycles
frequency in hertz is computed as
MCF =
f
n
The machine cycle period in second is
T =
1
MCF
=
n
f
It means to read or write one byte, machine takes Ts. Delay is a method to
lapse of time in MCU.

10 µP Introduction
Opcode MC Opcode MC Opcode MC Opcode MC
ACI RC DI SBB(R)
ADC RNC EI SBB(M)
ADD 1 RP HLT 1 SBI
ADI RM INR(R) SIM
ANA RZ INR(M) SPHL
ANI RNZ INX STAX
CMA RPE MOV STC
CMC RPO ORA(R) SUI
DDA RET 1 ORA(M) SUB(R)
DAD RIM PCHL SUB(M)
DCR(R) 1 RLC POP XCHG
DCR(M) RRC PUSH XRA(R)
DCX RST RAL XRA(M)
ADI MVI(R) 2 IN OUT
ANI MVI(M) 3 XRI
CPI ORI JNC
ORI JP CNC LDAX
OUT JZ CNZ LHLD
XRI JNZ CP LXI
CALL 5 JPE CPE SHLD
CC JPO CPO STA
CM LDA CZ JC
JMP JM
Table 1.2: Instruction sets and their machine cycles.
1.1.5 Addressing Modes
Instructions can be categorized on the basis of their addressing.

1.1. STRUCTURE 11
Implied Addressing Certain instructions are designed in such pattern
that they implied to specific functions. These instructions do not require
source or destination. The operation, source and destination of these in-
structions are fixed or predefined within the opcode itself. For example,
STC (set carry flag) deals only with carry flag. Similarly, other instructions
are DI and EI. Addressing by these types of instruction is called implied
addressing. Mostly one byte instructions addresses implied addressing.
Register Addressing A type of addressing in which an instruction needs
a register called register addressing. In this type of addressing there may be
8 bit single register or 16 bit register pair.
Immediate Addressing Instruction that uses immediate addressing have
data assembled as a part of the instruction itself. In other words, source
for the instruction is data itself rather than register name. For example,
instruction CPI ’C’ is interpreted as compare the contents of accumulator
with the charcode of symbol ‘C’. This instruction does not require for pointing
of accumulator either as source or as destination. This instruction assumes
automatically that comparison of data ‘C’ is with Accumulator.
Direct Addressing In direct addressing, instruction directly accesses or
addresses to 16-bit memory address. For example, instruction JMP 1000H
causes a jump to the hexadecimal adress 1000 and replaces the value at
address 1000 with new values.
Register Indirect Addressing Register Indirect Addressing instructions
reference memory via a register pair. The instruction MOV M,C moves the
contents of the C register into the memory address stored in the H&L register
pair.
Combined Addressing Modes Some instructions required two or more
combination of addressing modes. For example CALL instruction uses Direct
Addressing and Register Indirect Addressing.
Time Effects of Addressing Modes Addressing modes affects both the
amount of time required for executing an instruction and the amount of
memory required for its storage.

12 µP Introduction
1.2 Stack & Subroutines
Stack is a group of memory locations in the read/write memory that uses for
temporary storage of binary information during the execution of program.
The starting of stack memory location is fixed. The beginning of stack is de-
fined by instruction LXI which loads 16-bit memory address in stack pointer
register.
✞
LXI SP,C058H
✌
✆
The element in stack shall be started to store from memory location C058H.
Next sucessive elements shall be stored in C057H, C056H,... etc. This is
why, stack pointer location always defined to the highest avaialable memory
location.
✞
1 MVI H,04H ;Store 04H in register H
MVI L,1AH ;Store 1AH in register L
3 LXI SP,C058 ;Change the SP pointer to C058
PUSH H ;PUSH HL value into stack
5 PUSH H ;PUSH HL value into stack
✌
✆
After execution of above codes, the memory map is looked like
0 1 2 3 4 5 6 7 8 9 A B C D E F
C000 26 04 2E 1A 31 58 C0 E5 E5 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
C050 00 00 00 00 1A 04 1A 04 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
CFF0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 10
A subroutine is a group of instructions that preforms the sub task in
repeated occurrence. It is separate sub unit of a program. The MPU transfer
the program execution from the main program to the subroutine when it is
called to perform a task. After the completion of of subroutine task, the
MPU returns the main program. A subroutine is called by CALL instruction
and control is transferred to subroutine. After execution of subroutine the

1.2. STACK & SUBROUTINES 13
instruction RET returns the control to caller. RET is the last instruction
which is executed in subroutine.
✞
1 MVI A ,11H
MVI B,1FH
3 CALL MYLABEL ;Call subroutine MYLABEL
;Starts execution from here after subroutine
5 ADD B
CALL MYLABEL ;Call subroutine MYLABEL again
7 ;Starts execution from here after subroutine
DCR A
9 HLT
;---------Start of Subroutine MYLABEL ----------;
11 MYLABEL :
MVI C ,12H
13 RET ;Return to main caller
;----------End of Subroutine MYLABEL -----------;
✌
✆

2.1. INTERRUPT 15
2Interrupt & Instructions
2.1 Interrupt
The microprocessor can be interrupted from the normal execution of instruc-
tions and asked to execute some other instruction, called sub routine. The
microprocessor resumes its operation after completing the service routine.
Each interrupt has its own Interrupt Service Routine (ISR).
2.1.1 Interrupt Table
The interrupt table of 8085 micro processors is given below.
Interrupts Description
INTR Maskable interrupt request.
INTA Interrupt acknowledge.
RST 7.5, RST 6.5, RST 5.5 Restart interrupt. Priority order
is 7.5, 6.5 and 5.5.
TRAP Non maskable interrupt, highest
priority.
HOLD This indicates that a peripheral
controller is requesting the use of
address and data bus.
HLDA Hold acknowledge
READY This signal is used to delay the
microprocessor to read or write
with slow-responding peripheral
devices.

16 Interrupt & Instructions
8085 microprocessor has five interrupt inputs. First is INTR. It is mask-
able interrupt (can be delayed). When the interrupt occurs the processor
fetches one of the 8 RST instructions (RST 0 to RST 7). The processor
saves current program counter into stack and branches to memory location
N × 8. Here N is a 3-bit number from 0 to 7 supplied with the RST in-
struction. RST 5.5, RST 6.5 and RST 7.5 are restart interrupts. When RST
5.5, RST 6.5 and RST 7.5 interrupts are received the processor saves the
contents of the PC register into stack and branches to 2CH (hexadecimal),
34H (hexadecimal) and to 3CH (hexadecimal) address respectively. TRAP
is non-maskable fifth interrupt. It saves the contents of the PC register into
stack and branches to 24H (hexadecimal) address. These five interrupts are
vectored. On applying any of above five interrupts, MPU starts execution
from specific memory location. The interrupt memory location of vectored
interrupts are shown in table below:
Instruction Restart Location Maskable Vectored
INTR - YES NO
TRAP 0024H NO YES
RST 5.5 002CH YES YES
RST 6.5 0034H YES YES
RST 7.5 003CH YES YES
RST 7.5 is positive edge sensitive interrupt while RST 5.5 and RST 6.5
are level sensitive. Note that INTR is not a vectored inerrupts. Interrupts
are asynchronous. It must be active for long enough to allow for execution
of longest instruction and it must be off as soon as INTA signal received to
pervent the successive interrupt. After interrupt all maskable interrupts are
disabled and they will be enabled only after EI execution. The maximum
duration for INTR remain active is 18 machine T-states.
TRAP TRAP is highest priority non maskable interrupt (can not be de-
layed). It is always enable and can not be disabled. It is a level and edge
sensitive, it means that input should go high and stay high to be acknowl-
edged. It can not be acknowledged again until it makes a transition from
high to low to high. It is used for power failure and emergency shutoff.

2.1. INTERRUPT 17
RST 5.5, 6.5 and 7.5 These are maskable interrupts and are enabled
under program control with two instructions, EI and SIM.
RST The RST instruction is used to transfer the program execution to
a specific page location. It is 1 byte long instruction. The restart sequence is
made of three machine cycles. In first machine cycle, microprocessor sends
the INTA signal, reads the opcode data from the interrupting device for the
specific RST instruction. During second and third machine cycles, 16-bit
address of the next instruction is saved on the stack and microprocessor
jumps to the address associated with the specified RST instruction. There
are 8-types of non vectored RST instructions which are shown in table given
below:
Instruction Restart Location
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
An interrupt vector is a pointer to where the ISR is stored in memory. All
interrupts (vectored or otherwise) are mapped onto a memory area called the
Interrupt Vector Table (IVT). The IVT is usually located in memory page 00
(0000H-00FFH). The purpose of the IVT is to hold the vectors that redirect
the microprocessor to the right place when an interrupt arrives. The IVT is
divided into several blocks. Each block is used by one of the interrupts to
hold its “vector”.
Interrupt Priority Order TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR
are arranged from highest to lowest interrupt priority.

2.2 RIM
RIM is short form of Read Interrupt Mask. It is one byte long instruction.
It is used to read interrupt masks, to indentify pending interrupts and to
receive serial data. RIM instruction byte is
D7 D6 D5 D4 D3 D2 D1 D0
SID 17.5 16.5 15.5 IE M7.5 M6.5 M5.5
If digits D0, D1 and D2 are set high then they are said masked. D3 is
used for Interrupt Enable. D4, D5 and D6 are used for checking status of
pending interrupts. If these are high then the interrupts are pending. D7 is
used for Serial Input Data.
2.3 SIM
It is short name of Set Interrupt Mask. This is a one byte instruction and
can be used for three different functions. SIM byte is explained below:
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE xxx R7.5 MSE M7.5 M6.5 M5.5
The digits D0, D1 and D2 are for RST 5.5, RST 6.5 and RST 7.5 inter-
rupts. D3 bit is for Mask Set Enable. D4 bit is for REST RST7.5 if RST7.5
flip-flop is reset OFF. D5 bit is reserved. D6 is set high if D7 is to be used
for Serial Output Data Latch. D7 is for Serial Output Data. D7 is ignored
if D6 is set low.
2.4 I/O Devices
Input output devices in 8085MPU can be interfaced in two ways. Peripheral
I/O, in which the MPU uses an 8-bit address to identify an I/O and IN/OUT
instructions for data transfer. In memory mapped I/O, the MPU uses a
16-bit address to identify and I/O and memory related instructions for data

2.5. INSTRUCTION SETS 19
transfer. The 8085 MPU has two signals to impliment the serial transmission,
SID (Serial Input Data) and SOD (Serial Output Data). Data bits are sent
over a signal line as one bit at a time.
2.4.1 Address Bus
It has 16 signal lines which are used as address bus. These sixteen lines are
separated in two bytes long lines, i.e. AD0 −AD7 and A8 −A15. The address
bus lines A8 −A15 are unidirectional. Address bus lines AD0 −AD7 are 8 bits
long and bidirectional, and are multiplexed (time shared). The address bus
lines AD0 − AD7 serve two purposes. These lines carry addresses from CPU
to memory (acts like A0 − A7) and they carry 8 bits long data from memory
to CPU (acts like D0 −D7). A latch is used to save the value before function
of these 8 lines is changed from address bus to data bus or vice-versa.
2.5 Instruction Sets
There are two methods of instruction representations. In GAS type instruc-
tions, instruction sets are used like
✞
<instruction > src , dest
✌
✆
while in Intel type sytax, instruction sets are used like
✞
1 <instruction > dest , src
✌
✆
There are three types of instruction sets.
2.5.1 One Byte Instruction Set
One byte instruction includes the opcode and operand in the same byte. In-
stuction sets which implies register addressing, register & memory addressing
or vice versa are called one byte instruction sets. Memory to memory ad-
dressing is not allowed. All return instructions are one byte long. One byte
instruction sets are given in the table 2.1.

Opcode Bin Equiv Hex Equiv Opcode Bin Equiv Hex Equiv
ACI 11001110 CE RC 11011000 D8
ADC 10001SSS RNC 11010000 D0
ADD 10000SSS RP 11110000 F0
ADI 11000110 C6 RM 11111000 F8
ANA 10100SSS RZ 11001000 C8
ANI 11100110 E6 RNZ 11000000 C0
CMA 00101111 2F RPE 11101000 E8
CMC 00111111 3F RPO 11100000 E0
DDA 00100111 37 RET 11001001 C9
DAD 00RP1001 RIM 00100000 10
DCR(R) 00DDD101 RLC 00000111 07
DCR(M) 00110101 35 RRC 00001111 0F
DCX 00RP1011 RST 11CCC111
DI 11110011 F3 SBB(R) 10011SSS
EI 11111011 FB SBB(M) 10011110 9E
HLT 01110110 76 SBI 11011110 DE
INR(R) 00DDD100 SIM 00110000 30
INR(M) 00110100 34 SPHL 11111001 F9
INX 00RP0011 STAX 000r0010
MOV 00DDDSSS STC 00110111 37
ORA(R) 10110SSS SUI 11010110 D6
ORA(M) 10110110 B6 SUB(R) 10010SSS
PCHL 11101001 E9 SUB(M) 10010110 96
POP 11RP0001 XCHG 11101011 EB
PUSH 11RP0101 XRA(R) 10101SSS
RAL 00010111 17 XRA(M) 10101110 AE
RAR 00011111 1F XTHL 11100011 E3
Table 2.1: One Byte Instruction Set (Opcodes)

ACI
It is acronym of ADD IMMEDIATE WITH CARRY. The 8-bit data (operand)
and the Carry flag are added to the contents of the accumulator and the re-
sult is stored in the accumulator. All flags are modified to reflect the result
of the addition. The syntax is
✞
1 ACI <data in hex >
✌
✆
For example
✞
1 ACI A4
✌
✆
Illustrated Example
✞
1 MVI A,2A
ACI A4
3 HLT
✌
✆
It is an example for instruction “ACI”. Accumulator is first stored data 2A
hex. Immediate data A4 hexadecimal is added to accumulator along with
carry and result is stored in the accumulator. In this case result is hex CE.
✞
1 A : 00101010 ;Hex equivalent to 2A
ID: 10100100 ;Hex equivalent to A4
3 CY: _______0
--------------------- On summation
5 R : 11001110 ;Hex equivalent to CE
✌
✆

Register Hex Value D7 D6 D5 D4 D3 D2 D1 D0
Accumulator CE 1 1 0 0 1 1 1 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
And the flag register becomes
S Z * AC * P * CY
Flag 80 1 0 0 0 0 0 0 0
Illustrated Example
✞
1 MVI A,2A
STC
3 ACI A4
HLT
✌
✆
It is an example for instruction “ACI”. Accumulator is first stored data
2A hex. Carry flag is set to 1 by instruction “STC”. Immediate data A4
hexadecimal is added to accumulator along with carry and result is stored in
the accumulator. In this case result is hexadecimal CF.
✞
A : 00101010 ;Hex equivalent to 2A
2 ID: 10100100 ;Hex equivalent to A4
CY: _______1
4 --------------------- On summation
R : 11001111 ;Hex equivalent to CF
✌
✆

Accumulator CF 1 1 0 0 1 1 1 1
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 84 1 0 0 0 0 1 0 0
ADC
It is acronym of ADD WITH CARRY. The contents of the operand (register
or memory) and the Carry flag are added to the contents of the accumulator
and the result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL registers. All
flags are modified to reflect the result of the addition.
✞
1 ADC <source register >
;or
3 ADC <source memory register >
✌
✆
In other form:
✞
1 ADC B
;or
3 ADC M
✌
✆

Illustrated Example An example is given below:
✞
1 MVI A,47
MVI B,47
3 MVI C,5F
ADC C
5 HLT
✌
✆
The sum of hexadecimal ‘47’ and ‘5F’ is given below
✞
1 01000111 ; hexadecimal equal to 47
+01011111 ; hexadecimal equal to 5F
3 ---------
10100110 ; hexadecimal equal to A6
5 ---------
✌
✆
The left most bit is ‘1’, hence sign flag is set to ‘1’. Number of bit ‘1’ is
even so that parity flag is set to high. Addition of D2 bits generates carry,
so Auxiliary Carry flag is also set to high.
Accumulator A6 1 0 1 0 0 1 1 0
Register B 47 0 1 0 0 0 1 1 1
Register C 5F 0 1 0 1 1 1 1 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0

S Z * AC * P * CY
Flag 94 1 0 0 1 0 1 0 0
ADD
It is acronym of ADDITION. The contents of the operand (register or mem-
ory) are added to the contents of the accumulator and the result is stored
in the accumulator. “ADD” instruction excludes the carry flag from the ad-
dition but the sets the flag to indicate the outcome of the operation. If the
operand is a memory location, its location is specified by the contents of the
HL registers. All flags are modified to reflect the result of the addition.
✞
1 ADD <source register >
;or
3 ADD <source memory register >
✌
✆
i.e.
✞
1 ADD B
;or
3 ADD M
✌
✆
Illustrated Example
✞
1 MVI B,A1 ;Load register B with hexadecimal A1
MVI C,A2 ;Load register C with hexadecimal A2
3 MOV A,B ;Copy data from register B to Accumulator
ADD C ;Add data at register C with accumulator data
5 HLT
✌
✆
“MVI B,A1” instructs to store hexadecimal (hexadecimal value) ‘A1’ (Bi-
nary equivalent to 10100001) in register B. “MVI C,A2” instructs to store
hexadecimal (hexadecimal value) ‘A2’ (Binary equivalent to 10100010) in
register C. Instruction “MOV A,B” stores data from register B into accumu-
lator A. Now “ADD C” adds data from register C with data of accumulator
as given below.
✞
1 10100001

+ 10100010
3 -----------
(1) 01000011
✌
✆
This data is stored into the accumulator. In this binary addition, there is a
carry ‘1’ shown inside paranthesis. This is why ‘CY’ bit of flag register is set
to up (ie ‘1’).
Accumulator 43 0 1 0 0 0 0 1 1
Register B A1 1 0 1 0 0 0 0 1
Register C A2 1 0 1 0 0 0 1 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 81 1 0 0 0 0 0 0 1
ANA
It is acronym of LOGICAL AND WITH ACCUMULATOR. The contents
of the accumulator are logically ANDed with the contents of the operand
(register or memory), and the result is placed in the accumulator. If the
operand is a memory location, its address is specified by the contents of HL
registers. S, Z, P are modified to reflect the result of the operation. The
carry flag is reset. AC is set.

✞
ANA <register or memory address >
✌
✆
✞
1 ANA B
;or
3 ANA M
✌
✆
Illustrated Example The logical AND operation results true if all of its
inputs are true otherwise it gives false. Two input AND operation has trugh
table like
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
In assembly language, example of AND operation is given below.
✞
1 MVI A,2A
MVI B,A2
3 ANA B
HLT
✌
✆
At first accumulator and register B has hexadecimal values 2A and A2 re-
spectively. Instruction “ANA B” gives ANDed output as hexadecimal 22 and
stores it into accumulator. Explaination is given below.
✞
A : 00101010 ;Hex equivalent to 2A
2 B : 10100010 ;Hex equivalent to A2
---------------
4 AND : 00100010 ;Hex equivalent to 22
✌
✆
Final state of register shall be looked like

Accumulator 22 0 0 1 0 0 0 1 0
Register B A2 1 0 1 0 0 0 1 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
CMA
It is acronym of COMPLEMENT ACCUMULATOR. The contents of the
accumulator are complemented. All conditional flags remain unchanged. To
produce the two’s complement, add one to the contents of the accumulator
after the CMA instruction.
✞
CMA
✌
✆
Illustrated Example
✞
1 MVI B,05 ;Store register B with hexadecimal 05
MOV A,B ;Copy from register B to register A
3 CMA ;Complement to accumulator
✌
✆
Instruction “MVI B,05” loads hexadecimal 05 into register B. The binary
equivalent to hexadecimal 05 is ‘00000101’. This data is copied into accumu-
lator by instruction “MOV A,B”. Instruction “CMA” makes 1’s complement
to the data at accumulator and stores the result in accumulator. The final
result is ‘11111010’ which is hexadecimal equivalent to ‘FA’. The output will
appear in register set as given below.

Accumulator FA 1 1 1 1 1 0 1 0
Register B 05 0 0 0 0 0 1 0 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
CMC
It is acronym of COMPLEMENT CARRY. The carry flag is complemented.
If carry flag is one then it is reset to zero. And if carry flag is zero then it is
reset to one. No other flags are affected.
✞
1 CMC
✌
✆
Illustrated Example First we store the value in accumulator by using
instruction
✞
1 MVI A,A7
✌
✆
The register and flags value will be like

Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0
Using ‘RRC’ instruction
✞
1 MVI A,A7
RRC
3 HLT
✌
✆

Accumulator D3 1 1 0 1 0 0 1 1
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 01 0 0 0 0 0 0 0 1
Hex value ‘A7’ is binary equivalent to ‘10100111’. On using of instruction
‘RRC’, the right most bit is stored into carry flag. Binary value ‘10100111’
is rotated counter clockwise (right) by one bit and it becomes ‘11010011’.
Final result in the accumulator is ‘D3’ in hexadecimal. ‘CMC’ Instruction
complements to the carry flag.
✞
1 MVI A,A7
RRC
3 CMC ;Converts to carry flag to its complement
HLT
✌
✆
S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0

CMP
It is acronym of COMPARE WITH ACCUMULATOR. The contents of the
operand (register or memory) are compared with the contents of the accumu-
lator. Both contents are preserved . The result of the comparison is shown
by setting the flags of the PSW as follows:
1. If (A) < (reg/mem): carry flag is set
2. If (A) = (reg/mem): zero flag is set
3. If (A) > (reg/mem): carry and zero flags are reset to zero
✞
CMP <source register >
2 ;or
CMP <source memory register >
✌
✆
Illustrated Example
✞
1 MVI A,A7
MVI B,10
3 CMP B
HLT
✌
✆
S Z * AC * P * CY
Flag 80 1 0 0 0 0 0 0 0
✞
MVI A,10
2 MVI B,11
CMP B
4 HLT
✌
✆
S Z * AC * P * CY
Flag 85 1 0 0 0 0 1 0 1

DAA
It is acronym of DECIMAL ADJUST ACCUMULATOR. It has no operands.
DDA operates as follows.
1. The contents of the accumulator are changed from a binary value to two
4-bit binary coded decimal (BCD) digits. This is the only instruction
that uses the auxiliary flag to perform the binary to BCD conversion,
and the conversion procedure is described below. S, Z, AC, P & CY
flags are altered to reflect the results of the operation.
2. If the value of the low-order 4-bits in the accumulator is greater than
9 or if AC flag is set, the instruction adds 6 to the low-order four bits.
3. If the value of the high-order 4-bits in the accumulator is greater than
9 or if the Carry flag is set, the instruction adds 6 to the high-order
four bits.
✞
DAA
✌
✆
Illustrated Example
✞
1 MVI A,2A
MVI B,2A
3 DAA
HLT
✌
✆
It is an example for instruction “DAA”. Accumulator and register B are first
stored data 2A in hex. The binary equivalent of hexadecimal ‘2A’ is ‘0010
1010’. “DAA’ compares the four low order bits ‘1010’ with ‘9’ in decimal.
Here, four low order bits are greater than decimal ‘9’. Now “DAA” adds the
decimal ‘6’ to low order four bits.
✞
1010 ; Equivalent to decimal 10
2 0110 ; Equivalent to decimal 06
;Addition is
4 ------------
(1) 0000
✌
✆
The final eight digit binary number becomes ‘00110000’. It is hexadecimal
equivalent to ‘30’.

Accumulator 30 0 0 1 1 0 0 0 0
Register B 2A 0 0 1 0 1 0 1 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
Flag register status is like
S Z * AC * P * CY
Flag 04 0 0 0 0 0 1 0 0
Illustrated Example
✞
1 MVI A,A2
MVI B,A2
3 DAA
HLT
✌
✆
It is an example for instruction “DAA”. Accumulator and register B are first
stored data ‘A2’ in hex. The binary equivalent of hexadecimal ‘A2’ is ‘1010
0010’. “DAA’ compares the four low order bits ‘0010’ with ‘9’ in decimal.
Here, four low order bits are lesser than decimal ‘9’. Again, “DAA’ compares
the four high order bits ‘1010’ with ‘9’ in decimal. Here, four high order bits
are greater than decimal ‘9’. Now “DAA” adds the decimal ‘6’ to low order
four bits.
✞
1010 ;Equivalent to decimal 10

2 0110 ; Equivalent to decimal 06
;Addition is
4 ------------
(1) 0000
✌
✆
The final eight digit binary number becomes ‘00000010’ and set the Carry
flag to high. It is hexadecimal equivalent to ‘02’.
Accumulator 02 0 0 0 0 0 0 1 0
Register B A2 1 0 1 0 0 0 1 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 81 1 0 0 0 0 0 0 1
DAD
It is acronym of DOUBLE REGISTER ADD. The 16-bit contents of the
specified register pair are added to the contents of the HL register and the
sum is stored in the HL register. The contents of the source register pair
are not altered. If the result is larger than 16 bits, the CY flag is set. No
other flags are affected. DAD may add only the contents of the B&C, D&E,
H&L or the SP (Stack Pointer) register pairs to the contents of H&L. Notice

that the letter H must be used to specify that the H&L register pair is to be
added to itself.
✞
1 DAD <register >
✌
✆
✞
1 DAD H
✌
✆
Illustrated Example
✞
1 MVI B,02
MVI C,02
3 MVI H,03
MVI L,04
5 DAD B
HLT
✌
✆
It is an example for instruction “DAD”. Registers B, C, H and L are first
stored data ‘02’, ‘02’, ‘03’ and ‘04’ in hex. Instruction “DAD” adds contents
of register B with register H and register C with register L and stores the
result in H and L registers respectively. Data in binary form in registers are
✞
B => 02h :00000010
2 C => 02h :00000010
H => 03h :00000011
4 L => 04h :00000100
✌
✆
Before execution of instruction “DAD”, the register status is as given below.

Accumulator 02 0 0 0 0 0 0 1 0
Register B 02 0 0 0 0 0 0 1 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 03 0 0 0 0 0 0 1 1
Register L 04 0 0 0 0 0 1 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
Addition is takes place as
✞
+---B--+ +---C--+
2 00000010 00000010
4 +---H--+ +---L--+
00000011 00000100
6 ---------------------------------------------
DAD instruction adds above two 16 bit values
8 in binary form. The binary sum is given below
---------------------------------------------
10 00000101 00000110
+---H--+ +---L--+
✌
✆
After the execution of instruction “DAD”, the register status is becomes as
shown below.

Accumulator 02 0 0 0 0 0 0 1 0
Register B 02 0 0 0 0 0 0 1 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 05 0 0 0 0 0 1 0 1
Register L 06 0 0 0 0 0 1 1 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0
DCR
It is acronym of DECREMENT. The contents of the designated register or
memory are decremented by 1 and the result is stored in the same place. If
the operand is a memory location, its location is specified by the contents of
the HL registers. It affects all the conditional flags except the carry flag. Be-
cause it preserves the carry flag, it can be used within multi-byte arithmatic
routines for decrementing character counts and similar purposes.
✞
1 DCR <source register >
;or
3 DCR <source memory register >r
✌
✆
✞
1 DCR H
;or
3 DCR M
✌
✆

Illustrated Example
✞
1 MVI A ,05 ; Set Counter control
MVI B ,00 ; Set Counter control
3 LOOP :
INR B ; Increase B by one
5 DCR A ; Decrease A by one
JNZ LOOP ; Jump to loop while
7 ; accumulator is not zero
HLT
✌
✆
In above example, registers A and B are stored hexadecimal values 05 and
00 respectively. LOOP subroutine is used to increase the value of register
B and decrease the register A. If Accumulator (register A) becomes zero,
subroutine LOOP is cease to performed.
DCX
It is acronym of DECREMENT REGISTER PAIR. The contents of the des-
ignated register pair are decremented by 1 and the result is stored in the
same place. DCX does not affect any conditional flag. Due to preservation
of all the flags, it can be used for address modification in any instruction
sequence that relies on the passing of the flags. DCX considers the contents
of two consecutive registers to be a single 16-bit value and therefore performs
a borrow from the high order 8-bit register. For example HL register contain
the address 9800H and when DCX H is executed, it borrows from the H
register to produce 97FFH. Syntax of the instruction is
✞
DCX <source register >
✌
✆
For example
✞
1 DCX H
✌
✆
✞
1 MVI D,A1
;Fill register D by hexadecimal A1 as ;;;;;;;;
3 ; D :- 10100001
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5 MVI E ,00
;Fill register E by hexadecimal 00 as ;;;;;;;;
7 ; E :- 00000000

;The register pairs are combines as DE
9 ; DE :- 1010000100000000
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11 DCX D
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13 ;Decrement the DE by 1 ;;;;;;;;;;;;;;;
; DE :- 1010000100000000
15 ; -1
;---------------------------
17 ; DE :- 1010000011111111
;---------------------------
19 ;Now registers D & E has binary values
; D :- 10100000
21 ; E :- 11111111
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
23 HLT ;Halt the program
✌
✆
Illustrated Example
✞
1 MVI D,A1
DCX D
3 HLT
✌
✆
Instruction “MVI” adds hexadecimal ‘A1’ in the register D. Instruction
“DCX” decrements the value of register E (pair of register D) by 1 and
stores it in the same register. If pair register E has value zero then it stores
‘FF’ hexadecimal value and register D is decrement by 1. If pair register E
has value other than zero value then it is decrement by 1.

Accumulator 00 0 0 0 0 0 0 0 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D A0 1 0 1 0 0 0 0 0
Register E FF 1 1 1 1 1 1 1 1
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
Again
✞
1 MVI D,A1
MVI E,A1
3 DCX D
HLT
✌
✆
“DCX” decrements the value of register E (pair of register D) by 1 and
stores it in the same register E.
Accumulator 00 0 0 0 0 0 0 0 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D A1 1 0 1 0 0 0 0 1
Register E A0 1 0 1 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0

DI
It is acronym of DISABLE INTERUPTS. The interrupt enable flip-flop is
reset and all the interrupts except the TRAP are disabled. It is used when a
code sequence must not be interrupted. For example, time-dependent code
sequences become inaccurate when interrupted. Hence at the begining of
code sequence, this opcode must be included. To enable the system interrupt,
EI opcode is used. No flags are affected.
✞
DI
✌
✆
EI
It is acronym of ENABLE INTERUPTS. The interrupt enable flip-flop is set
and all interrupts are enabled. No flags are affected. After a system reset or
the acknowledgement of an interrupt, the interrupt enable flip-flop is reset,
thus disabling the interrupts. This instruction is necessary to reenable the
interrupts (except TRAP).
✞
1 EI
✌
✆
HLT
The CPU finishes executing the current instruction and halts any further
execution. An interrupt or reset is necessary to exit from the halt state.
✞
1 HLT
✌
✆
INR
It is acronym for INCREMENT. The contents of the designated register or
memory are incremented by 1 and the result is stored in the same place. If
the operand is a memory location, its location is specified by the contents
of the HL registers. It affects all of the condition flags except the carry flag.
Because of INR preserves the carry flag, it can be used within multibyte
arithmatic routines for incrementing character counts and similar purposes.
✞
1 INR <source register >
;or

3 INR <source memory register >r
✌
✆
✞
1 INR B
;or
3 INR M
✌
✆
Illustrated Example
✞
1 MVI A,A1 ;Load accumulator with hexadecimal A1
CMA ;Complement it
3 INR A ;Add binary 1 in accumulator
STA C010 ;Store result at memory location C010
✌
✆
“MVI A,A1” instructs to accumulator to store hexadecimal (hexadecimal
value) A1 (Binary equivalent to 10100001). Instruction “CMA” cause the
1’s complement to the accumulator whose binary value becomes ‘01011110’.
“INR A” adds binary ‘1’ into the value of accumulator and stores the result
into the accumulator.
✞
1 01011110
+ 1
3 -----------
01011111
✌
✆
This binary value is equal to hexadecimal 5F and it is stored into the accu-
mulator. Now instruction “STA C010” copies the accumulator value into the
memory location ‘C010’. Register output looks like as given below.

Accumulator 5F 0 1 0 1 1 1 1 1
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
INX
The contents of the designated register pair (B&C, D&E and H&L) are in-
cremented by 1 and the result is stored in the same place. It does not affects
any condition flags. As it preserves all the condition flags, it can be used for
address modification within multi-bytes arithmatic routines.
✞
INX <source register >
✌
✆
For example
✞
1 INX H
✌
✆
The method of execution of instruction is:
✞
1 MVI D,A1
;Fill register D by hexadecimal A1 as ;;;;;;;;
3 ; D :- 10100001
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5 MVI E,FF
;Fill register E by hexadecimal FF as ;;;;;;;;
7 ; E :- 11111111
;The register pairs are combines as DE
9 ; DE :- 1010000111111111
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11 INX D

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13 ;Increment the DE by 1 ;;;;;;;;;;;;;;;
; DE :- 1010000111111111
15 ; +1
;---------------------------
17 ; DE :- 1010001000000000
;---------------------------
19 ;Now registers D & E has binary values
; D :- 10100010
21 ; E :- 00000000
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
✌
✆
Illustrated Example See the following instruction codes, where in the
register pair DE, register D is stored by a data value while register E keeps
empty.
✞
1 MVI D,A1
INX D ;INX works with register pair.
3 ;INX D, means increment of
;designated register pair DE.
5 HLT
✌
✆
“INX” increments the value of register E (pair of register D) by 1 and stores
it in the same register.

Accumulator 00 0 0 0 0 0 0 0 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D A1 1 0 1 0 0 0 0 1
Register E 01 0 0 0 0 0 0 0 1
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
Again, when pair register E is not empty.
✞
1 MVI D,A1
MVI E,A1
3 INX D ;INX works with register pair.
;INX D, means increment of
5 ; designated register pair DE.
HLT
✌
✆
it in the same register E.

Accumulator 00 0 0 0 0 0 0 0 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D A1 1 0 1 0 0 0 0 1
Register E A2 1 0 1 0 0 0 1 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
If pair register E stores hexadecimal value ‘FF’. Then increment takes
place in the register D and value of pair register E alters to zero. Again if
both D&E register pair have hexadecimal value ‘FF’ then both stores 0s and
there is no change in flag registers.
✞
MVI D,A1
2 MVI E,FF
INX D ;INX works with register pair.
4 ;INX D, means increment of
;designated register pair DE.
6 HLT
✌
✆
it in the same register E.

Accumulator 00 0 0 0 0 0 0 0 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D A2 1 0 1 0 0 0 1 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
MOV
It is short form of MOVE. This instruction copies the contents of the source
register into the destination register. The contents of the source register
are not altered. If one of the operands is a memory location, its location is
specified by the contents of the HL registers. When same register is specified
for both operands, the MOV functions as a NOP and there is no other
noticeable effect. Similary MOV operation from a memory register M to
memory register M is not allowed. Instruction’s operands specify whether
the move is from register to register, from a register to memory or from
memory to a regsiter. It operation synopsys is given by
✞
MOV <destination register >,<source register >
✌
✆
✞
1 MOV B,C
;or
3 MOV B,M
✌
✆
Note that there is one space after opcode ‘MOV’ and operands are separated
with comma without spaces. Here B is destination register and C is source
register.
Illustrated Example An example is given below:
✞
1 MVI A,05 ;store hexadecimal value 05 in register A

MOV B,A ;copy value from register A into B
3 HLT ;stop the execusion of program
✌
✆
The output is
Accumulator 05 0 0 0 0 0 1 0 1
Register B 05 0 0 0 0 0 1 0 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
If accumulator data is copied in memory register then data is appeared
at the memory location. Above instruction sets are rewritten as given below
to copy accumulator data into memory.
✞
1 MVI A ,05 ;store hexadecimal value 05 in register A
MOV M,A ;copy value from register A into memory
register M
3 HLT ;stop the execusion of program
✌
✆
The output is

Accumulator 05 0 0 0 0 0 1 0 1
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 05 0 0 0 0 0 1 0 1
NOP
Short form of NO OPERATION. No operation is performed. This instruction
is only fetched and decoded, however no operation is executed.
✞
1 NOP
✌
✆
ORA
Acronym of INCLUSIVE OR WITH ACCUMULATOR. The contents of the
accumulator are logically ORed with the contents of the operand (register
or memory), and the result is placed in the accumulator. If the operand is
a memory location, its address is specified by the contents of HL registers.
S, Z, P are modified to reflect the result of the operation. CY and AC are
reset.
✞
1 ORA <register or memory >
✌
✆
✞
1 ORA B
;or
3 ORA M
✌
✆

Illustrated Example In binary number systems, output in inclusive OR
between two inputs is always high if either or both inputs are high. The OR
operation on two 8-bit numbers is given below.
✞
1 85H => 10000101
23H => 00100011
3 ---------------------
OR : 10100111 => A7
5 ---------------------
✌
✆
Here is a working example that is well explaining the OR operation in 8085
microprocessor using ORA instruction.
✞
1 MVI A ,85 ; Load A by hexadecimal 85
MVI B ,85 ; Load B by hexadecimal 85
3 MVI C ,23 ; Load C by hexadecimal 23
ORA C ; Inclusive OR Operation
5 ; resets A to hexadecimal A7
HLT
✌
✆
PCHL
Acronym of MOVE H&L TO PROGRAM COUNTER. The contents of reg-
isters H and L are copied into the program counter. The contents of H are
placed as the high-order byte and the contents of L as the low-order byte.
PCHL has the effect of a jump instruction. Operands are not permitted with
PCHL instruction.
✞
PCHL
✌
✆
POP
It is acrony of ‘POP OFF STACK TO REGISTER PAIR’. The contents of
the memory location pointed out by the stack pointer register are copied to
the low-order register (C, E, L & status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that memory location are
copied to the high-order register (B, D, H & A) of the operand. The stack
pointer register is again incremented by 1.

✞
1 POP <register >
✌
✆
Illustrated Example The example is
✞
1 MVI H,10 ; Load H by hexadecimal 10
POP H ; Remove contents from H
3 MVI L,10 ; Load L by hexadecimal 10
MOV A,L ; Copy contents of L into A
5 HLT ; Stop program execusion
✌
✆
The registers H and L are stored hexadecimal values 10 each. POP instruc-
tion is used to remove the data stored in register H. Content of L is transferred
to accumulator.
PUSH
It is acrony of ‘PUSH REGISTER PAIR ONTO STACK’. The contents of
the register pair designated in the operand are copied onto the stack in the
following sequence.
1. The stack pointer register is decremented and the contents of the
high-order register (B, D, H & A) are copied into that location.
2. The stack pointer register is decremented again and the contents of
the low-order register (C, E, L & flags) are copied to that location. The
operand may specify the B&C, D&E or H&L register pair.
✞
1 PUSH <register >
✌
✆
Illustrated Example On execution of program given below, Stack Pointer
is set to CFFF. PUSH stores the high order value into the memory location
CFFF. Stack Pointer is decremented again and it stores the low order value
at memory location CFFE.
✞
1 MVI B,10 ; Load B by hexadecimal 10
MVI C,20 ; Load C by hexadecimal 20
3 PUSH B ; Load contents of BC pair in
; memory location CFFF & CFFE
5 HLT
✌
✆

0 1 2 3 4 5 6 7 8 9 A B C D E F
C000 06 10 0E 20 C5 76 00 00 00 00 00 00 00 00 00 00
C010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
CFF0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 10
Table 2.2: Required memory addresses with their values. Others are not
mentioned here.
RAL
It is acronym of ROTATE LEFT THROUGH CARRY. Each binary bit of
the accumulator is rotated left by one position through the Carry flag. Bit
D7 removed from its place and it is placed in the Carry flag, and the original
value of Carry flag is placed after the least significant position D0. CY is
modified according to bit D7. S, Z, P, AC are not affected. Initial carry bit
becomes part of the accumulator data.
✞
1 RAL
✌
✆
Illustrated Example Consider the assembler codes as given in following
example
✞
1 MVI A ,47
MVI B ,47
3 MVI C,5F
ADD C
5 HLT
✌
✆
The register and flag status will be like

Register B 47 0 1 0 0 0 1 1 1
Register C 5F 0 1 0 1 1 1 1 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 94 1 0 0 1 0 1 0 0
As per difinition of “RAL” instruction, D7 bit replaces to the bit of carry
flag. The accumulator value is shifted left by one position. The original bit
of Carry Flag is placed in D0.
✞
1 MVI A,47
MVI B,47
3 MVI C,5F
ADD C
5 RAL
HLT
✌
✆

Accumulator 4C 0 1 0 0 1 1 0 0
Register B 47 0 1 0 0 0 1 1 1
Register C 5F 0 1 0 1 1 1 1 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 95 1 0 0 1 0 1 0 1
The bit value of Carry flag is placed just after the digit D0.
D7 D6 D5 D4 D3 D2 D1 D0
CY
Now the bit arrangement is looked like:
D7 D6 D5 D4 D3 D2 D1 D0 CY

The bit value of D7 digit is removed from its original position and is
placed in Carry flag.
D7 D6 D5 D4 D3 D2 D1 D0 CY
The one byte data at accumulator is modified according the equivalent
hexadecimal value of all bits are in the order as shown in the figure below.
D6 D5 D4 D3 D2 D1 D0
D7
CY
RAR
It is acronym of ROTATE RIGHT THROUGH CARRY. Each binary bit
of the accumulator is rotated right by one position through the Carry flag.
Bit D0 is removed from its place and it is placed in the Carry flag, and the
original value of Carry flag is placed before the most significant position D7.
CY is modified according to bit D0. S, Z, P, AC are not affected.
✞
RAR
✌
✆
Illustrated Example Consider the assembler codes as given in following
example
✞
1 MVI A,47
MVI B,47
3 MVI C,5F
ADD C
5 HLT
✌
✆

Register B 47 0 1 0 0 0 1 1 1
Register C 5F 0 1 0 1 1 1 1 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 94 1 0 0 1 0 1 0 0
As per difinition of “RAR” instruction, D7 bit is replaced by bit of carry
flag. The accumulator value is shifted right by one position. The original D0
bit is placed in Carry Flag.
✞
1 MVI A ,47
MVI B ,47
3 MVI C,5F
ADD C
5 RAR
HLT
✌
✆

Accumulator 53 0 1 0 1 0 0 1 1
Register B 47 0 1 0 0 0 1 1 1
Register C 5F 0 1 0 1 1 1 1 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 94 1 0 0 1 0 1 0 0
The bit value of Carry flag is placed just before the digit D7.
D7 D6 D5 D4 D3 D2 D1 D0
CY
Bit positions are as shown in below figure.
D7 D6 D5 D4 D3 D2 D1 D0
CY

The bit value of D0 digit is removed from its placed and placed in the
Carry flag.
D7 D6 D5 D4 D3 D2 D1 D0
CY
D7 D6 D5 D4 D3 D2 D1
D0
CY
RET
It is acronym of RETURN FROM SUBROUTINE. The program sequence
is transferred from the subroutine to the calling program. After execution of
RET instruction, the two bytes from the top of the stack are copied into the
program counter, and program execution begins at the new address.
✞
RET
✌
✆
Illustrated Example In this example, the whole code is partioned in three
parts. One is main part and two are subroutines. The main part calls
subroutines and hands over control to them. The RET instruction returns
the control back to the main program.
✞
1 MVI A ,11H
;---------Start of Main -----------
3 MAIN :
CALL SUBROUT_1
5 CALL SUBROUT_2

DCR A
7 JNZ MAIN ;Loop the MAIN till
; accumulator is not
9 ;became equal to zero
;---------End of Main -------------
11 ;
;---------Start of SUBROUT_1 ------
13 SUBROUT_1:
MVI B,12H
15 RET ;Return to CALL
;---------End of SUBROUT_1 -------
17 ;
;---------Start of SUBROUT_2 ------
19 SUBROUT_2:
MVI C,13H
21 RET ;Return to CALL
;---------End of SUBROUT_2 -------
23 HLT;End of the program.
✌
✆
RIM
Acronym of READ INTERRUPT MASK. This is a multipurpose instruction
used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input
bit. The instruction loads eight bits in the accumulator. The bit pattern
indicates the current setting of the interrupt mask, the setting of the interrupt
flag, pending interrupts and one bit of serial input data. Operands are not
permitted with RIM.
✞
1 RIM
✌
✆
RLC
It is acronym of ROTATE ACCUMULATOR LEFT & SET CARRY FLAG.
Each binary bit of the accumulator is rotated left by one position. Bit D7 is
removed from its position and is postfixed after D0 as well as in the Carry
flag. CY is modified according to bit D7. S, Z, P, AC are not affected. This
instruction set is useful in serial communication as each bit of accumulator
data is copied into the carry flag sequentially. Initial carry bit does not
become part of the accumulator data.

✞
1 RLC
✌
✆
instruction
✞
1 MVI A,A7
✌
✆
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0
Using ‘RLC’ instruction
✞
1 MVI A,A7
RLC
3 HLT
✌
✆

Accumulator 4F 0 0 1 0 1 1 1 1
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 01 0 0 0 0 0 0 0 1
‘RLC’, the left most bit is stored into carry flag. Binary value ‘10100111’ is
rotated clockwise (left) by one bit position and it becomes ‘01001111’. Final
result in the accumulator is ‘4F’ in hexadecimal. In following figure, the
“RRC” is explained. First pick the D7 digit from the binary data of the
accumulator.
D7 D6 D5 D4 D3 D2 D1 D0
CY
The bit value of D7 digit is placed in the place of Carry flag.

D6 D5 D4 D3 D2 D1 D0
D7
Now the Carry flag is modified accordingly. Now the bit value of Carry
flag is placed just after the bit D0.
D6 D5 D4 D3 D2 D1 D0
D7
D6 D5 D4 D3 D2 D1 D0
D7
D7
RRC
It is acronym of ROTATE ACCUMULATOR RIGHT & SET CARRY FLAG.
Each binary bit of the accumulator is rotated right by one bit position. Bit
D0 is removed from its own position and prefixed before the bit D7 as well
as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are
not affected.
✞
1 RRC
✌
✆
instruction

✞
1 MVI A,A7
✌
✆
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0
Using ‘RRC’ instruction
✞
1 MVI A,A7
RRC
3 HLT
✌
✆

Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 01 0 0 0 0 0 0 0 1
‘RRC’, the right most bit is stored into carry flag. Binary value ‘10100111’
is rotated counter clockwise (right) by one bit and it becomes ‘11010011’.
Final result in the accumulator is ‘D3’ in hexadecimal. In following figure,
the “RRC” is explained. First pick the D0 digit from the binary data of the
accumulator.
D7 D6 D5 D4 D3 D2 D1 D0
CY
The bit value of D0 digit is placed in the place of Carry flag.

D7 D6 D5 D4 D3 D2 D1
D0
Now the Carry flag is modified accordingly. Now the bit value of Carry
flag is placed just before the digit D7.
D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3 D2 D1
D0
D0
R< X >
The program sequence is transferred from the subroutine to the calling pro-
gram based on the specified flag of the PSW as described below. The two
bytes from the top of the stack are copied into the program counter, and
program execution begins at the new address.
✞
1 R<X>
✌
✆
✞
1 RZ
✌
✆

Other conditional jumping instruction sets are shown in the table given be-
low.
Opcode Description Flag Status
RC Return on carry CY = 1
RNC Return on no carry CY = 0
RP Return on positive S = 0
RM Return on minus S = 1
RZ Return on zero Z = 1
RNZ Return on no zero Z = 0
RPE Return on parity even P = 1
RPO Return on parity odd P = 0
Table 2.3: Conditional Return.
RST
It is short form of RESTART. The RST instruction is equivalent to a 1-
byte call instruction to one of eight memory locations depending upon the
number. The instructions are generally used in conjunction with interrupts
and inserted using external hardware. However these can also be used as
software instructions in a program to transfer program execution to one of
the eight locations. The restart number and their corresponding restarting
addresses are given in the following table.

Instruction Restart Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
Table 2.4: Instruction for restart addresses.
See the example below:
✞
1 MVI A,11H
MVI B,1FH
3 CALL MYLABEL ;Call subroutine MYLABEL
ADD B ;Due to RST 0, It will never executed.
5 DCR A ;Due to RST 0, It will never executed.
HLT ;Due to RST 0, It will never executed.
7 ;---------Start of Subroutine MYLABEL ----------;
MYLABEL :
9 RST 0;Restart from begining , so execution
;restarted from the line of MVI A,11H
11 RET ;Due to RST 0, It will never executed.
✌
✆
The above example is modified for RST 1.
✞
MVI A,11H
2 MVI B,1FH
CALL MYLABEL ;Call subroutine MYLABEL
4 ADD B ;Due to RST 1, It will never executed.
DCR A ;After returning from subroutine
6 ;execution starts from here
HLT ;Halt the program

8 ;---------Start of Subroutine MYLABEL ----------;
MYLABEL :
10 RST 1;Restart from 0008H location.
;It is from the line of DCR A
12 RET ;Return to main caller
✌
✆
Interrupt Restart Address
TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
Table 2.5: Interrupt for restart addresses.
The 8085 has four additional interrupts and these interrupts generate RST
instructions internally and thus do not require any external hardware. These
instructions and their restart addresses are shown in above table.
SBB
It is acronym of SUBTRACT WITH BORROW. The contents of the operand
(register or memory ) and the Borrow flag are subtracted from the contents of
the accumulator and the result is placed in the accumulator. If the operand
is a memory location, its location is specified by the contents of the HL
registers. All flags are modified to reflect the result of the subtraction.
✞
1 SBB <source register >
;or
3 SBB <source memory register >r
✌
✆
✞
1 SBB B
;or
3 SBB M
✌
✆
Illustrated Example In the following example

✞
1 MVI A,15
MVI B,05
3 STC
SBB B
5 HLT
✌
✆
Instruction “MVI” stores the hexadecimal data 05 in register B. “STC” sets
the Carry flag to high. “SBB B” subtracts the contents of register B consid-
ering borrow bit and stores the final result in accumulator. After execution
of program, the register holds the values as shown below.
Register B 05 0 0 0 0 0 1 0 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
The flag registers modified accordingly to reflect the result.
S Z * AC * P * CY
Flag 85 1 0 0 0 0 1 0 1
SBI
It is acronym of SUBTRACT IMMEDIATE WITH BORROW. The 8-bit
data (operand) and the Borrow flag are subtracted from the contents of

the accumulator and the result is stored in the accumulator. All flags are
modified to reflect the result of the subtracion.
✞
1 SBI <data in hex >
✌
✆
✞
1 SBI 45
✌
✆
Illustrated Example In the following example
✞
1 STC
SBI 05
3 HLT
✌
✆
“STC” sets the Carry flag to high. “SBI 05” subtracts the hexadecimal 05
considering the borrow bit and stores the final result in accumulator. After
execution of program, the register holds the values as shown below.
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
The flag registers modified accordingly to reflect the result.
S Z * AC * P * CY
Flag 85 1 0 0 0 0 1 0 1

SIM
This is a multipurpose instruction and used to implement the 8085 interrupts
7.5, 6.5, 5.5, and serial data output.
✞
1 SIM
✌
✆
SPHL
It is acrony of ‘COPY H AND L REGISTERS TO THE STACK POINTER’.
The instruction loads the contents of the H and L registers into the stack
pointer register, the contents of the H register provide the high-order address
and the contents of the L register provide the low-order address. The contents
of the H and L registers are not altered.
✞
1 SPHL
✌
✆
STAX
It is acronym of ‘STORE ACCUMULATOR INDIRECT’. The contents of
the accumulator are copied into the memory location specified by the contents
of the operand (register pair). The contents of the accumulator are not
altered.
✞
1 STAX <register >
✌
✆
✞
1 MVI A,10
MVI B,C0 ;Higher level register
3 MVI C,10 ;Lower level register
STAX B ;B for register pair B&C
5 ;the address is C010
✌
✆
STC
It is acronym of ‘SET CARRY’. The Carry flag is set to 1. No other flags
are affected. Operands are not permitted with this instruction.
✞
1 STC
✌
✆

Illustrated Example
✞
1 STC
HLT
✌
✆
S Z * AC * P * CY
Flag 01 0 0 0 0 0 0 0 1
SUB
It is short form of ‘SUBTRACT’. The contents of the operand (register or
memory) are subtracted from the contents of the accumulator, and the result
is stored in the accumulator. If the operand is a memory location, its location
is specified by the contents of the HL registers. All flags are modified to reflect
the result of the subtraction.
✞
SUB <source register >
2 ;or
SUB <source memory register >r
✌
✆
✞
1 SUB B
;or
3 SUB M
✌
✆
Illustrated Example
✞
1 MVI A ,47 ; Load Accumulator with hexadecimal 47
MVI C ,10 ; Load C with hexadecimal 10
3 SUB C ; Subtract C in A and load result in A
HLT ; Halt the program execusion
✌
✆
Accumulator and register C are stored with hexadecimal 47 and hexadecimal
10 values respectively. Now, value in register C is subtracted from accumu-
lator by the instruction SUB C. The result is stored in the accumulator.

Accumulator 37 0 0 1 1 0 1 1 1
Register B 00 0 0 0 0 0 0 0 0
Register C 10 0 0 0 1 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
SUI
It is acronym of ‘SUBTRACT IMMEDIATE’. The 8-bit data (operand) is
subtracted from the contents of the accumulator and the result is stored in
the accumulator. All flags are modified to reflect the result of the subtraction.
✞
SUI <data in hex >
✌
✆
✞
1 SUI 45
✌
✆
Illustrated Example
✞
1 MVI A,47 ; Load Accumulator with hexadecimal 47
SUI 45 ; Subtract 45 directly in A and load result in
A
3 HLT ; Halt the program execusion
✌
✆
Accumulator is stored with hexadecimal 47. Now, hexadecimal 45 is sub-
tracted immediate from accumulator by the instruction SUI 45. The result
is stored in the accumulator.

Accumulator 02 0 0 0 0 0 0 1 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
XCHG
It is acronym of ‘EXCHANGE H AND L WITH D AND E’. The content of
register H and L are exchanged with registers D and E respectively.
✞
1 XCHG
✌
✆
Illustrated Example
✞
1 MVI D,A1
MVI E,A2
3 MVI H,A3
MVI L,A4
5 XCHG
HLT
✌
✆
Using instruction “MVI” registers D, E, H & L are assigned hexadecimal
values. Instruction “XCHG” exchanges the hexadecimal values of H and L
with D and E respectively. The output will appear in register set as given
below.

Accumulator 00 0 0 0 0 0 0 0 0
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D A3 1 0 1 0 0 0 1 1
Register E A4 1 0 1 0 0 1 0 0
Register H A1 1 0 1 0 0 0 0 1
Register L A2 1 0 1 0 0 0 1 0
Memory (M) 00 0 0 0 0 0 0 0 0
XRA
It is acronym of ‘EXCLUSIVE OR WITH ACCUMULATOR’. The contents
of the accumulator are Exclusive ORed with the contents of the operand
(register or memory), and the result is placed in the accumulator. If the
operand is a memory location, its address is specified by the contents of HL
registers. S, Z, P are modified to reflect the result of the operation. CY and
AC are reset.
✞
XRA <register or memory >
✌
✆
✞
1 XRA B
;or
3 XRA M
✌
✆
Illustrated Example In binary number systems, output in exclusive OR
between two inputs is always high if either of the two inputs are high. In two
8-bit numbers, exclusive OR is operated as
✞
1 85H : 10000101
23H : 00100011
3 ----------------
OR : 10100110
5 ----------------
✌
✆

Here is an working example explaining the XRA instruction.
✞
1 MVI A ,85 ; Load A by hexadecimal 85
MVI B ,85 ; Load B by hexadecimal 85
3 MVI C ,23 ; Load C by hexadecimal 23
XRA C ; Exclusive OR Operation
5 ; resets A to hexadecimal A6
HLT
✌
✆
XTHL
It is acronym of ‘LOAD H AND L WITH TOP OF STACK’. The content of
the L register is exchanged with the stack location pointed out by the content
of the stack pointer register. The content of the H register is exchanged with
the next stack location (SP+1); however, the contents of the stack pointer
register are not altered.
✞
XTHL
✌
✆
Note that, Stack Pointer is 16 bits (2 bytes) long register. Hence it can store
two bytes long data, i.e. addresses of two one byte long memory cells. The
first memory cell is lower level cell while second memory cell is higher level
cell. This is why, first byte is stored in L register (lower level of register pair
H & L) and second byte is stored in H register (higher level of register pair
H & L).
2.5.2 Two Bytes Instruction Set
Two bytes instruction includes the 8-bit opcode and 8-bit operand in the two
bytes. First byte specified the operation code and second byte specified to
operand. Mostly all the instruction sets at immediate addressing mode and
IN,OUT instructions are two bytes instructions. Two bytes instruction sets
are given in the table below.

Opcode Bin Equiv Hex Equiv
ADI 11000110 C6
ANI 11100110 E6
CPI 11111110 FE
IN 11011011 DB
MVI(R) 00DDD110
MVI(M) 00110110 36
ORI 11110110 F6
OUT 11010011 D3
XRI 11101110 EE
Table 2.6: Two Byte Instruction Set (Opcodes)
ADI
It is acronym of ADD IMMEDIATE. The 8-bit data (operand) is added to
the contents of the accumulator and the result is stored in the accumulator.
All flags are modified to reflect the result of the addition.
✞
1 ADI <data in hex >
✌
✆
✞
1 ADI 45
✌
✆
Illustrated Example
✞
1 MVI A,AF
MVI B,AF
3 ADI 4F
HLT
✌
✆
In above example, accumulator and register B are stored by hexadecimal
AF each by instruction set MVI. Accumulator is added by hexadecimal 4F
immediately by using instruction set ADI. The result is stored in the accu-
mulator.

Register B AF 1 0 1 0 1 1 1 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 90 1 0 0 1 0 0 0 0
ANI
It is acronym of AND IMMEDIATE WITH ACCUMULATOR. The contents
of the accumulator are logically ANDed with the 8-bit data (operand) and
the result is placed in the accumulator. S, Z & P flags are modified to reflect
the result of the operation. CY flag is reset to zero. AC is also set. The
assembler’s reloction feature treats all external and relocatable symbols as 16-
bit addresses. When on of these symbols appears in the operand expression
of an immediate instruction, it must be preceded by either the HIGH or LOW
operator to specify which byte of the address is to be used in the evaluation of
the expression. Whether neither operator is present, the assembler assumes
the LOW operator and issues an error message.
✞
ANI <data in hex >
✌
✆
✞
1 ANI 86
✌
✆

Illustrated Example
✞
1 MVI A,AF
MVI B,AF ;Instruction is used to compare accumulator
data
3 ;before and after ANI instruction
ANI 86
5 HLT
✌
✆
In above example, accumulator and register B are stored by hexadecimal
AF each by instruction set MVI. Accumulator is ANDed with hexadecimal
86 immediately by using instruction set ANI. The result is stored in the
accumulator.
Accumulator 86 1 0 0 0 0 1 1 0
Register B AF 1 0 1 0 1 1 1 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 90 1 0 0 1 0 0 0 0
CPI
It is acronym of COMPARE IMMEDIATE. The second byte (8-bit data) is
compared with the contents of the accumulator. Zero and carry flags are

sets accordingly to indicate the result. The values being compared remain
unchanged. The result of the comparison is shown by setting the flags of the
PSW as follows:
1. If (A) < data: carry flag is set
2. If (A) = data: zero flag is set
3. If (A) > data: carry and zero flags are reset
✞
1 CPI <data in hex >
✌
✆
✞
1 CPI 89
✌
✆
Illustrated Example
✞
1 MVI A,AF
data
3 ;before and after CPI instruction
CPI 4F
5 HLT
✌
✆
In above example, accumulator and register B are stored by hexadecimal AF
each by instruction set MVI. Accumulator is compared with hexadecimal
4F immediately by using instruction set CPI. The result is stored in the
accumulator.

Accumulator AF 1 0 1 0 1 1 1 1
Register B AF 1 0 1 0 1 1 1 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 14 0 0 0 1 0 1 0 0
IN
This instruction provides the address of port for data input to accumulator.
Opened port is a 8-bit address. The contents of the input port designated in
the operand are read and loaded into the accumulator. IN instruction does
not set any of the condition flags. The flags can be set without altering the
data by adding 00H to the contents of the accumulator.
✞
1 IN <8-bit port address >
✌
✆
Illustrated Example An example for “IN” instruction is given below.
✞
1 MVI B,06
IN 00
3 HLT
✌
✆

“MVI B,06” stores the hexadecimal value ‘06’ in register B. Data in input
port address ‘00’ is stored into accumulator by instruction “IN 00”. The
inport data matrix is shown below.
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
After the execution of the program, the register states are changed as
shown below.
Accumulator 05 0 0 0 0 0 1 0 1
Register B 06 0 0 0 0 0 1 1 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
MVI
It moves immediately 8-bit data to a destination register or memory. If the
destination is a memory location, its location is specified by the contents of
the HL registers.
✞
1 MVI <destination register or Memory >,<8-bit data in hex >
✌
✆

✞
1 MVI B,57
;or
3 MVI M,57
✌
✆
Remember that one byte (8-bit) data should be in paired format.
Illustrated Example For MVI instruction, decimal ‘1’ is equivalent to ‘1’
in hexadecimal format, but when it is placed as operand to opcode, must be
written as ‘01’ instead of ‘1’. It can be better understand from the following
example.
✞
1 MVI A,05 ;store hexadecimal value 05 in register A
(accumulator)
MVI B,06 ;store hexadecimal value 06 in register B
3 MVI C,07 ;store hexadecimal value 07 in register C
HLT ;stop the execusion of program
✌
✆
In above example, MVI instruction is used for storing hexadecimal data
immediately in registers. The output of the above example is
Accumulator 05 0 0 0 0 0 1 0 1
Register B 06 0 0 0 0 0 1 1 0
Register C 07 0 0 0 0 0 1 1 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
ORI
Acronym of INCLUSIVE OR IMMEDIATE. The contents of the accumulator
are logically ORed with the 8-bit data (operand) and the result is placed in

the accumulator. S, Z, P are modified to reflect the result of the operation.
CY and AC are reset.
✞
ORI <data in hex >
✌
✆
✞
1 ORI 86
✌
✆
Illustrated Example
✞
1 MVI A,AF
data
3 ;before and after ORI instruction
ORI 86
5 HLT
✌
✆
MVI instruction is used to add hexadecimal data AF to accumulator and reg-
ister B each. ORI instruction is used for OR operation immediately between
accumulator and hexadecimal 86. The result is stored in the accumulator.
Accumulator AF 1 0 1 0 1 1 1 1
Register B AF 1 0 1 0 1 1 1 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0

S Z * AC * P * CY
Flag 84 1 0 0 0 0 1 0 0
OUT
Short form of OUTPUT TO PORT. It outputs data from accumulator to a
port with 8-bit address. The contents of the accumulator are copied into the
I/O port specified by the operand.
✞
1 OUT <8-bit port address >
✌
✆
Illustrated Example An example for “OUT” instruction is given below.
✞
1 MVI A,05
OUT 00
3 HLT
✌
✆
“MVI A,05” stores the hexadecimal value ‘05’ into accumulator. Data in
accumulator is copied into output port ‘00’ by using instruction “OUT 00”.
During the execution of program, when program instructs “MVI A,05” ac-
cumulator register stores the data 05 in hex.
Accumulator 05 0 0 0 0 0 1 0 1
Register B 00 0 0 0 0 0 0 0 0
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0

And when, program instructs “OUT 00”, the contents of accumulator are
stored in the outport at 00 port address. The output port status is shown
below.
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Table 2.7: Required I/O port matrix with value. Others are not mentioned
here.
XRI
It is acronym of ‘EXCLUSIVE OR IMMEDIATE WITH ACCUMULATOR’.
The contents of the accumulator are Exclusively ORed with the 8-bit data
(operand) and the result is placed in the accumulator. S, Z, P are modified
to reflect the result of the operation. CY and AC are reset to zero.
✞
1 XRI <data in hex >
✌
✆
✞
1 XRI 86
✌
✆
✞
1 MVI A,AF
3 ;data before and after XRI instruction
XRI 86
5 HLT
✌
✆

Accumulator 29 0 0 1 0 1 0 0 1
Register B AF 1 0 1 0 1 1 1 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0
2.5.3 Three Bytes Instruction Set
Three bytes instruction include the 8-bit opcode and 16-bit address. First
byte specified the operation code and next two bytes specified to address.
Three bytes instruction sets are given in the table below. Mostly all the
instruction sets addressed data at 16bit memory location or directly ad-
dress/access to 16bit memory address are three byte instructions. In three
byte instructions, destination register comes first and source register comes
later.

Opcode Bin Equiv Hex Equiv Remarks
CALL 11001101 CD
CC 11011100 6E
CM 11111100 FC
CNC 11010100 D4
CNZ 11000100 C4
CP 11110100 F4
CPE 11101100 EC
CPO 11100100 E4
CZ 11001100 CC
JMP 11000011 C3
JC 11011010 DA
JM 11111010 FA
JNC 11010010 D2
JP
JZ 11001010 CA
JNZ 11000010 C2
JPE 11101010 EA
JPO 11100010 E2
LDA 00111010 3A
LDAX 000r1010 (r=0 for register pair B &
r=1 for register pair D)
LHLD 00101010 2A
LXI 00RP0001
SHLD 00100010 22
STA 00110010 32
Table 2.8: Three Byte Instruction Set (Opcodes)

CALL
It is acronym of CALL. It is the combination of the PUSH and JMP instruc-
tions (combined addressing mode). The program sequence is transferred to
the memory location specified by the 16-bit address given in the operand.
Before the transfer, the address of the next instruction after CALL (the
contents of the program counter) is pushed onto the stack. Each CALL in-
struction or one of its variants implies the use of a subsequent RET (return)
instruction. When a call has no corresponding return, excess addresses are
built up in the stack.
✞
1 CALL <memory address >
✌
✆
✞
1 CALL 2034
✌
✆
Illustrated Example
✞
1 MVI B,05 ;Load register B with hexadecimal 05
MOV C,B ;Copy register B into register C
3 JMP GO ;Conditional jump to memory location GO
MVI D,A7 ;Load register D with hexadecimal A7
5 GO:
CALL C002;Call pointer to the memory location C002
7 ;At which the command MOV C,B started.
;
9 CMA ; Complement to accumulator
✌
✆
CALL instruction is also used to cerate subroutines with RET instruction.
See the example below.
✞
1 MVI A,11H
;---------Start of Main --------------------
3 MAIN :
CALL SUBROUT_1
5 CALL SUBROUT_2
DCR A
7 JNZ MAIN;Loop the MAIN till accumulator
; is not becomes equal to zero
9 ;---------End of Main ----------------------
;
11 ;---------Start of SUBROUT_1 ---------------

SUBROUT_1:
13 MVI B ,12H
RET ;Returns to caller of SUBROUT_1
15 ;---------End of SUBROUT_1 ----------------
;
17 ;---------Start of SUBROUT_2 ---------------
SUBROUT_2:
19 MVI C ,13H
RET ;Returns to caller of SUBROUT_2
21 ;---------End of SUBROUT_2 ----------------
HLT;End of the program.
✌
✆
In this example, the whole code is partioned in three parts. One is main part
and other two parts are subroutines. The main part CALLs to subroutines
and hands over the control to subroutiens. The RET instruction returns the
control to the CALL instruction.
C< X >
The program sequence is transferred to the memory location specified by the
16-bit address given in the operand based on the specified flag of the PSW
as described below. Before the transfer, the address of the next instruction
after the call (the contents of the program counter) is pushed onto the stack.
The Conditional CALL test the case and if it is true then it jumps to the
address specified. If the test of the case is false then program execution is
simply continues with the next sequential instruction. Syntax is
✞
C<X> <label >
✌
✆
‘CALL on Zero’ instruction can be specified as given below.
✞
1 CZ XX
✌
✆
If Z is set to 1 (ie all the bits of a 8 bit register are zero), the program jumps
to label ‘XX’. Other conditional C< X > instruction sets are explained in
the following table.

CC Call on Carry CY = 1
CNC Call on No Carry CY = 0
CP Call on Positive S = 0
CM Call on Minus S = 1
CZ Call on Zero Z = 1
CNZ Call on No Zero Z = 0
CPE Call on Parity Even P = 1
CPO Call on Parity Odd P = 0
Table 2.9: Conditional Call.
Illustrated Example
✞
1 MVI A,12 ; Add hexadecimal value 12 to register A
MVI B,FE ; Add hexadecimal value FE to register B
3 ADD B ; Add contents of B with A
; result is hexadecimal 10 with CY = 1
5 CC XX ; If CY =1 then jump to label XX
MVI D,05 ; In this case this instruction
7 ; is not executed.
XX: ;Label
9 MOV C,A ; Copy contents of A into C
HLT ; Halt the program
✌
✆
Above example is well commented and explained. Similary, the group of
these instructions can be used as given in the following example.
✞
MVI A,12 ; Add hexadecimal value 12 to register A
2 MVI B,1E ; Add hexadecimal value 1E to register B
ADD B ; Add contents of B with A
4 ; result is hexadecimal 30 with CY = 0
CC XX ; CY =0 then no jump to label XX
6 MVI D,05 ; This instruction is executed.
; Register D is assigned hexadecimal value 05
8 XX: ; Label

MOV C,A ; Copy contents of A into C
10 HLT ; Halt the program
✌
✆
J< X >
The program sequence is transferred to the new memory location (branching)
specified by the 16-bit address given in the operand based on the specified flag
of the PSW as described below. These jump instructions provide conditional
branching or conditional jump.
✞
J<X> <label >
✌
✆
✞
1 JZ GOHERE
✌
✆
Other conditional jumping instruction sets are shown in the table given be-
low.
JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0
JP Jump on positive S = 0
JM Jump on minus S = 1
JZ Jump on zero Z = 1
JNZ Jump on no zero Z = 0
JPE Jump on parity even P = 1
JPO Jump on parity odd P = 0
Table 2.10: Conditional Jump
Illustrated Example
✞
1 MVI B ,05 ;Load register B with hexadecimal 05
3 JNC GO ;Conditional jump to memory location GO

GO:
5 MOV A,B ;Copy contents of register B into register
A
CMA ; Complement to accumulator
7 HLT
✌
✆
The output is
Register B 05 0 0 0 0 0 1 0 1
Register C 05 0 0 0 0 0 1 0 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
JMP
The program sequence is transferred to the memory location specified by
the 16-bit address given in the operand. The address may be specified as a
number, a label or an expression. The assembler inverts the high and low
address bytes when it assembles the address.
✞
1 JMP <memory address /label >
✌
✆
✞
1 JMP 2034
✌
✆
✞
1 MVI B,05 ;Load register B with hexadecimal 05
3 JMP GO ;Conditional jump to memory location GO
MVI D,A7 ;Load register D with hexadecimal A7
5 GO:

MOV A,B ;Copy contents of register B into register
A
7 CMA ;Complement to accumulator
HLT
✌
✆
The register output is
Register B 05 0 0 0 0 0 1 0 1
Register C 05 0 0 0 0 0 1 0 1
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
LDA
It is acronym of LOAD ACCUMULATOR DIRECT. It copies the contents
of a memory location into the accumulator. Memory location is identified by
the address in the operand. It does not change the contents of the source.
Its synopsis is
✞
LDA <16-bit address >
✌
✆
✞
1 LDA xxxx
✌
✆
Where xxxx is the address of memory in hexadecimal code. Assume a mem-
ory matrix and working example as given below:

0 1 2 3 4 5 6 7 8 9 A B C D E F
C000 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
C010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
CFF0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Illustrated Example
✞
1 MVI B,AF
LDA C000
3 HLT
✌
✆
After execution of program, the output is stored in the accumulator. The
register states are changed accordingly to show the result. For this given
program, the register state shall be as
Accumulator 3A 0 0 1 0 1 0 0 1
Register B AF 1 0 1 0 1 1 1 1
Register C 00 0 0 0 0 0 0 0 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 00 0 0 0 0 0 0 0 0
Register L 00 0 0 0 0 0 0 0 0
Memory (M) 00 0 0 0 0 0 0 0 0
The flag register also modified accordingly to reflect the result.

S Z * AC * P * CY
Flag 00 0 0 0 0 0 0 0 0
LDAX
It is acronym of LOAD ACCUMULATOR EXTENDED. The contents of
the designated register pairs (B&C or D&E) point to a memory location.
This instruction copies the contents of that memory location into the accu-
mulator. The contents of either register pair or memory location are not
altered. It does not accepts register pair HL.
✞
1 LDAX <register pair >
✌
✆
For example
✞
1 LDAX B
;or
3 LDAX D
✌
✆
The operand B specifies the register pair B and C; D specifies the register
pair D and E. This instruction accepts only B or D register pair. Assume that
register D contains 87H and E contains 10H then on call of the instruction
LDAX D loads the accumulator with the contents of memory location 8710H.
Illustrated Example
✞
1 MVI B,C0 ; Register B has contents C0
MVI C ,02 ; Register C has contents 02
3 LDAX B ; Load contents from memory
; location represent by register
5 ; pair BC. And in this case memory
; lcoation is C002
7 HLT
✌
✆

Accumulator 0E 0 0 0 0 1 1 1 0
Register B C0 1 1 0 0 0 0 0 0
Register C 02 0 0 0 0 0 0 1 0
Register D 00 0 0 0 0 0 0 0 0
Register E 00 0 0 0 0 0 0 0 0
Register H 06 0 0 0 0 0 1 1 0
Register L 05 0 0 0 0 0 1 0 1
Memory (M) 00 0 0 0 0 0 0 0 0
0 1 2 3 4 5 6 7 8 9 A B C D E F
C000 06 C0 0E 02 0A 76 00 00 00 00 00 00 00 00 00 00
C010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
CFF0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Table 2.11: Only required memory addresses with their values are shown
above. Others memory cells are not mentioned here for simplification pur-
poses.
LHLD
It is acronym of ‘LOAD H AND L DIRECT’. This mnemonic copies the
contens of the two consecutive memory locations pointed by 16-bit address
respectively into L and H registers without altering the contents of the source
memory registers.
✞
1 LHLD <16-bit memory address >
✌
✆

Notes of 8085 micro processor Programming for BCA, MCA, MSC (CS), MSC (IT) & AMIE IEI- by Arun Umrao

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