Datasheet of EPC2012

1. eGaN® FET DATASHEET EPC2012
EPC2012 – Enhancement Mode Power Transistor
VDSS , 200 V NEW PRODUCT
RDS(ON) , 100 mW EFFICIENT POWER CONVERSION
ID , 3 A HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coefficient allows very low RDS(ON), while its lateral device structure
and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.
EPC2012 eGaN® FETs are supplied only in
passivated die form with solder bars
Maximum Ratings Applications
VDS Drain-to-Source Voltage 200 V • High Speed DC-DC conversion
• Class D Audio
Continuous (TA =25˚C, θJA = 70) 3
ID A • Hard Switched and High Frequency Circuits
Pulsed (25˚C, Tpulse = 300 µs) 15
Benefits
Gate-to-Source Voltage 6
VGS V • Ultra High Efficiency
Gate-to-Source Voltage -5 • Ultra Low RDS(on)
TJ Operating Temperature -40 to 125 • Ultra low QG
˚C • Ultra small footprint
TSTG Storage Temperature -40 to 150
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 60 µA 200 V
IDSS Drain Source Leakage VDS = 160 V, VGS = 0 V 10 50 µA
Gate-Source Forward Leakage VGS = 5 V 0.2 1
IGSS mA
Gate-Source Reverse Leakage VGS = -5 V 0.1 0.5
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.7 1.4 2.5 V
RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 3 A 70 100 m
Source-Drain Characteristics (TJ= 25˚C unless otherwise stated)
IS = 0.5 A, VGS = 0 V, T = 25˚C 1.9
VSD Source-Drain Forward Voltage V
IS = 0.5 A, VGS = 0 V, T = 125˚C 2
All measurements were done with substrate shorted to source.
PARAMETER Thermal Characteristics
TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Characteristics (TJ= 25˚C unless otherwise stated) TYP
Rθ
CISSJC Thermal Resistance, Junction to Case
Input Capacitance 128 8.2 145 ˚C/W
CRθJB
OSS Thermal Resistance, Junction to Board VDS = 100 V, VGS = 0 V
Output Capacitance 73 36 95 ˚C/W pF
CRθJA
RSS Reverse Transfer Capacitance to Ambient (Note 1)
Thermal Resistance, Junction 3.3 85 4.4 ˚C/W
Note 1: RθJAQG
is determined with the device mounted on one(VGS = inch of copper pad, single layer 2 oz copper on FR4 board.
Total Gate Charge square 5 V) 1.5 1.8
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
QGD Gate to Drain Charge 0.57 0.75
VDS = 100 V, ID = 3 A
QGS Gate to Source Charge
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PAGE
QOSS Output Charge 11 14

2. Source-Drain Characteristics (TJ= 25˚C unless otherwise stated)
IS = 0.5 A, VGS = 0 V, T = 25˚C 1.9
eGaN®VFET DATASHEET
SD Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V, T = 125˚C 2
V
EPC2012
All measurements were done with substrate shorted to source.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS Input Capacitance 128 145
COSS Output Capacitance VDS = 100 V, VGS = 0 V 73 95 pF
CRSS Reverse Transfer Capacitance 3.3 4.4
QG Total Gate Charge (VGS = 5 V) 1.5 1.8
QGD Gate to Drain Charge 0.57 0.75
VDS = 100 V, ID = 3 A
QGS Gate to Source Charge 0.33 0.41 nC
QOSS Output Charge 11 14
QRR Source-Drain Recovery Charge 0
All measurements were done with substrate shorted to source.
Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics
15 15
VGS = 5
VGS = 4 25˚C
VGS = 3 125˚C
VGS = 2 VD = 3 V
ID – Drain Current (A)
10 10
ID – Drain Current (A)
5 5
0 0
0 0.5 1 1.5 2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
VDS – Drain to Source Voltage (V) VGS – Gate to Source Voltage (V)
Figure 3: RDS(ON) vs. VGS for Various Drain Currents Figure 4: RDS(ON) vs. VGS for Various Temperatures
200 250
25˚C
RDS(ON) – Drain to Source Resistance (m )
125˚C
RDS(ON) – Drain to Source Resistance (m )
200 ID = 3 A
150
150
100
100
50 ID = 3 A
ID = 6 A 50
ID = 10 A
ID = 15 A
0 0
2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5
VGS – Gate to Source Voltage (V) VGS – Gate to Source Voltage (V)
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3. eGaN® FET DATASHEET EPC2012
Figure 5: Capacitance Figure 6: Gate Charge
5
0.25
COSS = CGD + CSD ID = 3 A
CISS = CGD + CGS VD = 100 V
CRSS = CGD 4
0.2
VG – Gate Voltage (V)
C – Capacitance (nF)
0.15 3
0.1 2
0.05 1
0 0
0 50 100 150 200 0 0.5 1 1.5 2
VDS – Drain to Source Voltage (V) QG – Gate Charge (nC)
Figure 7: Reverse Drain-Source Characteristics Figure 8: Normalized On Resistance vs. Temperature
15 1.8
25˚C
125˚C ID = 3 A
Normalized On-State Resistance – RDS(ON) VGS = 5 V
1.6
ISD – Source to Drain Current (A)
10
1.4
1.2
5
1
0 0.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 -20 0 20 40 60 80 100 120 140
VSD – Source to Drain Voltage (V) TJ – Junction Temperature ( ˚C )
Figure 9: Normalized Threshold Voltage vs. Temperature Figure 10: Gate Current
1.6 .025
25˚C
1.4 125˚C
.02
Normalized Threshold Voltage (V)
1.2
IG – Gate Current (A)
.015
1
0.8
.01
0.6
.005
0.4
ID = 1 mA
0.2 0
-20 0 20 40 60 80 100 120 140 0 1 2 3 4 5 6
TJ – Junction Temperature ( ˚C ) VGS – Gate-to-Source Voltage (V)
All measurements were done with substrate shortened to source.
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4. eGaN® FET DATASHEET EPC2012
Figure 11: Transient Thermal Response Curve
Normalized Maximum Transient Thermal Impedance
1
Duty Factors:
0.5
0.1 0.2
0.1
ZθJB, Normalized Thermal
0.05 PDM
0.01 0.02
Impedance
0.01 t1
t2
0.001 Single Pulse
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
0.0001
10-5 10-4 10-3 10-2 10-1 1 10 100
tp, Rectangular Pulse Duration, seconds
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7” reel
b d e f g Loaded Tape Feed Direction
7” reel Die
orientation
dot
c Gate
a solder bar is
under this
corner
Die is placed into pocket
solder bar side down
EPC2012 (note 1) (face side down)
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
f (note 2) 2.00 1.95 2.05
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
g 1.5 1.5 1.6 not the pocket hole.
DIE MARKINGS
2012
YYYY Laser Markings
Die orientation dot Part
Number Part # Lot_Date Code Lot_Date Code
Gate Pad solder bar ZZZZ Marking Line 1 Marking line 2 Marking Line 3
is under this corner EPC2012 2012 YYYY ZZZZ
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5. eGaN® FET DATASHEET EPC2012
A
DIE OUTLINE d f MILLIMETERS
x2 DIM
Solder Bar View MIN Nominal MAX
A 1.681 1.711 1.741
2 3 4 B 0.889 0.919 0.949
X2
d
c 0.660 0.663 0.666
d 0.251 0.254 0.257
B
c
e 0.230 0.245 0.260
1
f 0.251 0.254 0.257
g 0.600 0.600 0.600
e g g
Side View
815 Max
(685)
100 +/- 20
SEATING PLANE
RECOMMENDED The land pattern is solder mask defined 1711
LAND PATTERN
(units in µm)
1 1
234
3 4 3 4
643
409
919
2 2
600 600 234 234
X2
Pad no. 1 is Gate
Pad no. 2 is Substrate
Pad no. 3 is Drain
Pad no. 4 is Source
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any productor circuit Information subject to
described herein; neither does it convey any license under its patent rights, nor the rights of others. change without notice.
eGaN® is a registered trademark of Efficient Power Conversion Corporation. Revised September, 2011
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2011 | | PAGE 5