A DC-6 GHz, Packaged 100 Watt GaN SPDT Switch MMIC
A DC-6 GHz, Packaged 100 Watt GaN SPDT
Ritu Jain, Sushil Kumar, Bernie Stocklingsky, Jeff Shealy
RFMD, 105 E Tasman Drive
San Jose, CA, USA
Abstract—A Low insertion loss, high isolation and high power
DC-6GHz SPDT has been developed using GaN on SiC using
0.5um HEMT technology. The developed switch has CW P0.1dB
as 100W and Pulsed Pmax >126W. Insertion loss of this SPDT is
≤0.8dB with isolation ≥30dB & RL ≥20dB across the band.
Measured ON/OFF switching time was <20nS. Switch performed
very well during hot switching test for pulsed control voltage (Vc)
=-30 to -60V. No degradation in IL or Isolation was observed
between hot and cold switching. The switch is packaged in a
plastic 5X5 QFN package.
Index Terms—SPDT switches, Gallium Nitride (GaN),
HEMT, FETs, High Power, High Isolation, Low insertion loss,
Stacked series/shunt FETs.
RF and microwave switches find extensive application in
wireless, radar and aerospace systems for signal routing and
switching between transmit and receive chain. Switches are
widely used in microwave and RF test systems as well for
There are two major types of switches available for RF &
microwave application; one is electromechanical (MEMS) and
other is solid-state (PIN/FET or Hybrid of PIN and FET)
switches. Electromechanical switches rely on mechanical
contacts for switching mechanism.
Semiconductor materials used for FET based switches are
GaAs, GaN, Si-On-Sapphire (SOS) and Si-On-Insulator (SOI).
All these technologies and devices based switches have certain
benefits relative to each other, like MEMS based switch has
low insertion loss, high isolation, low power consumption,
extreme linearity and the ability to be integrated with other
electronics. Reliability, especially for hot switching is a major
issue with MEMS switch and this technology is still emerging.
So far GaAs based switches were workhorse for most of the
RF and microwave solid-state circuit based low to moderate
power applications. Recent advancement of CMOS SOS and
SOI based switch has started gaining ground in RF and low
microwave frequency range. Solid-state PIN/FET based
switches are typically more reliable and exhibit longer lifetime
than electromechanical switches, plus offer faster switching
time. However, solid-state switches typically have higher
intrinsic ON resistance and more harmonic distortion than
For moderate to high power and high frequency applications
PIN diode based switches are widely used. GaAs based FET
has low breakdown voltage and so power handling capability
is limited to a few watts compared to PIN based switches. The
emergence of new wideband gap device technology based on
GaN material has significantly enhanced the power handling
capability of GaN FET based switches due to the key
properties, high electric field strength and low on resistance.
GaN based switch provide very large power handling from
almost DC to very high frequency and consumes negligible
power. These are added benefit of GaN switches. GaN on SiC
has been used for development of SPDT switch discussed in
this paper. High thermal conductivity (>330 W/m.K) of SiC
substrate prevents extreme channel temperature and reduce
A DC- 6GHz High Power 100W (CW) MMIC SPDT switch
has been developed using GaN on SiC. The developed switch
has very low insertion loss (<0.8 dB) and high isolation (> 30
dB) over the entire DC-6GHz band. Switching speed is <
20ns. Switch did not show any degradation in RF performance
during hot switching test with pulsed Vc from -30 to -60V
range. To the author’s best knowledge, this switch has highest
power, lowest insertion loss, highest isolation and fastest
switching speed compared to any other reported commercially
or published switch in the DC-6GHz frequency band.
II. GAN SEMICONDUCTOR DEVICE PROCESS
The developed switch MMIC was fabricated using Gallium
Nitride HEMT technology on 4 mil SiC substrate. Source and
Drain was formed using ohmic contacts and uses 0.5µm
Schottky gate. For device passivation and MIM capacitors,
thin layers of Si3N4 with cap-density of 135pF/mm2
The gate resistance was defined by the bulk GaN mesa
resistivity 500 Ω/sq. The switch MMICs were fabricated using
a two-level metal interconnects with dielectric crossover
technology. The wafers were thinned to 4 mil and uses back
side via to DC and low parasitic RF ground. The wafer
backsides were Au plated. Idmax for this process is 1.1A/mm
PREPRESS PROOF FILE CAUSAL PRODUCTIONS1
and BV1mA is 200V. Peak Ft and Fmax are 12 GHz and
45GHz respectively for this process. Extracted on-state
resistance is ~2.3Ohm-mm, Cds is ~0.078 pF/mm and off-state
capacitance Cgd =Cgs ≈0.27 pF/mm and 0.11 pF/mm at -10V
and -40V Vgs, respectively. High breakdown voltage (400V)
enables operation at control voltage -60 V and excellent
III. FET MODEL AND SWITCH DESIGN
To design the SPDT switch a Verilog-A nonlinear passive
FET model based on  has been developed using Agilent’s
ICCAP and implemented in ADS. Various sizes of symmetric
devices in CS and CG configuration have been layout and
measured to extract proper model and check model device size
Developed AlGaN/GaN PHEMT models are specifically
fitted to address the switch design simulations. It provides the
flexibility to model Hetero structure Field Effect Transistors
for both switch and amplifier applications. Main features of
these models are symmetry w.r.t. Drain and Source terminals,
better description and fitting of sub-threshold regime and the
continuous conduction and charge equations and their
derivatives. It enables the elimination of discontinuities in
current and capacitance formulations which plagues the
typical FET models especially at VDS =0V. Model includes
two gate diodes and two linear gate-drain and gate-source
resistors to appropriately model the gate current. It also
includes appropriate scaling relationships between device
geometries including length, width and number of fingers of
the device. Dispersion is treated as a frequency dependent
output conductance in the form of a RC network between
drain and source. Metallization capacitances are formulated in
two parts, a gate-width-independent fringing portion and a
width-dependent overlap portion.
The design goals for developed SPDT switch were;
insertion loss≤1 dB, isolation ≥ 30 dB, P0.1 dB ≈100Watt, I/O
RL ≥ 10dB in the frequency range DC-6GHz and switching
speed <30nS. The simplified switch design circuit
configuration and the die picture are shown in Fig. 1a & 1b.
Fig. 1a. Simplified Schematic of Fig. 1b. Layout of SPDT Switch
SPDT Switch 1940µm x 1100µm x 100µm
It consists of two stacked series and two stacked shunt
transistors in each arm. Series transistors’ periphery has been
selected to satisfy the power design requirements at common
port for ON and OFF arm. For the high power switches, the
power handling ability is determined by the ability of OFF
state transistor to handle the max RF voltage without turning
ON and the ability of series FETs to handle max RF current
without burning. Following equations have been used to
initially estimate series device size.
Pmax = Imax
* Zo/2 (ON State) (1)
And power delivered by single FET device shunt
configuration in OFF state is
Pmax = (Vbr+Vg) 2
/ 2*Zo (OFF State) (2)
Where Vg = (Vbr – Vp)/2, and Vbr, Vg and Vp, is the breakdown
voltage, the bias voltage, and the pinch-off voltage of the FET.
Zo is the characteristic impedance.
Once series device size has been estimated, a proper large
signal simulation for SPDT was performed with only series
FETs in ON and OFF arm connected together without any
shunt FET to ensure that both ON and OFF arm could handle
>100W. Series FET’s sizes has been adjusted by this method.
Same method has been used for shunt FETs. It was ensured
that shunt FET could also handle Pin>100W independently.
Advantage of stacked FETs is, it distributes RF swing and so
higher power handling can be achieved. Disadvantage of
stacked FETs is higher Ron. This increases IL and reduces
Isolation. Coff of stacked FET is also lower as compared to a
single device. This helps to improve isolation of OFF series
stacked FETs but affects isolation of ON stack shunt FETs at
lower frequencies. Shunt stack FETs also help to improve
failures due to VSWR mismatch.
The developed AlGaN/GaN PHEMT SPDT was housed in
5x5, 24 pin QFN plastic package. A proper package transition
model has been developed and used during SPDT design.
IV. MEASUREMENT RESULTS
Fig.2. shows test fixture used to measure RF performance of
SPDT switch, for thermal reason a large Aluminum heat sink
was used. The switch has been characterized for Vc=-40 to -
60V and insignificant change in [S]-parameter and other
parameters have been observed.
Fig.3 shows measured insertion loss from DC-10GHz. It
shows that @ 2GHz IL ~0.4dB and @ 6GHz IL ~0.8dB.
Fig. 2. Test Fixture used for Fig. 3. Measured IL vs. Frequency
Fig.4. shows return loss of all the ports. It shows that RF
input return loss and ON arm output return loss are >20dB
over entire frequency range from DC-6GHz.
Fig.5 shows Isolation of OFF arm. It shows that @ 2GHz
Isolation ~38dB and @ 6GHz Isolation ~30dB.
Fig. 4. Measured RL vs. Frequency Fig. 5. Measured Isol vs. Frequency
Fig.6 shows measured Pin vs. IL (Pin-Pout) for switch
operation in CW mode @ 2GHz. This plot shows that input
P0.1dB of the switch is > 50dBm (100W).
Fig.7 shows pulsed power compression at 10, 20, 50 & 75%
duty cycle @ 3.1GHz, 200µs pulse width was used for testing.
Measured pulsed P0.2dB was >126W. CW and Pulsed
measurement were done on two different location and unit.
The unit used for pulsed has non-optimal bond wire length and
so it has slightly higher IL compared to unit used for CW test.
With optimum bond wire length pulsed power is supposed to
improve. This work is still in progress.
Fig. 6. Pin-Pout vs. Pin (P0.1dB) Fig. 7. Pulsed Pout vs. Duty Cycle
Fig.8 shows measured IIP3 @ 2GHz and 'f =50GHz. It was
most difficult measurement of all. With the use of several
isolators and filtering, system intermodulation could not be
suppressed enough to ensure a highly accurate DUT
intermodulation measurement. Measured IIP3 is ~ +82dBm.
Fig.9 shows hot Switching performance measured for
RFin= 1 GHz at 0dBm using spectrum analyzer in time
domain at different Vcontrol. Measured insertion loss is -
0.4dB and isolation is -42dB or less for all Vc= -30 to -60V.
Fig.10 (a) & (b) Switching time is measured using 100
KHz, Vc= -40 V control pulse, for RF= 1GHz. Rise time of
control pulse is 32 ns. Measured switching ON and OFF time
is ~ 20ns.
Fig. 8. IIP3 vs. Pin Fig. 9. Hot Switching IL & ISOL
@ Vc= -30 to -60 V, RFin= 1 GHz
Fig. 10a. Measured Switch ON Fig. 10b. Measured Switch OFF
COMPARATIVE PERFORMANCE OF SPDT GaN SWITCHES
Parameters This work ,  ,  
Freq. (GHz) DC-6 DC-6 DC-4 DC-3.5
P0.1dB (W) 100 40 25 100
>126W - - -
I L (dB) ≤0.8 ≤1.0 ≤0.7 ≤0.97
Isolation (dB) ≥ 30 ≥ 40 ≥ 30 ≥ 18.7
On 20 50 30 -
Off 20 50 30 -
I/O RL (dB) >20 >18 >16 >17.5
IIP3@2GHz 81dBm 66dBm >60dBm -
Package 5x5 4x4 5x5 die
This paper discusses design and measured performances of
a DC-6GHz, 100W SPDT MMIC in a QFN package. To the
best of author’s knowledge as shown in Table-I, measured
performance in terms of small signal, power, IIP3 and
switching speed are one of the best in comparison to any
published or commercially available similar SPDT switch.
Authors are thankful to RFMD fab team for helping to
make this circuit into real part, Dain Miller and Dan Henry for
useful discussion. Authors are also thankful to Gorden Cook,
Rick Montgomery for their market feedback, Eric Carpenter
for helping as PM, Kalaya Gilstrap for testing the parts. Lin Ng
and Lili Gong (assemblers) for doing all assembly work.
Gautham Heeraguppe and Gunjan Pandey for helping with
PCB design. We are thankful to Trishul VP, Carl Hinshaw and
Rob Dry for package design and selection.
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 CMSA30025S, “25 Watt, 0.1-3.0 GHz GaN SPDT Reflective Switch”
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