1. Design of Low Power Fast Full Adder using Domino
Logic Based on magnetic tunnel junction and
Memristor
Under the guidance of
Dr. Rakshith B
Assistant professor
Department of Electronics and Communication Engineering
JSS Science and Technology University, SJCE
By,
Radhika H R
Prakruthi K P
3. Abstract
Domino CMOS circuits are widely used in high-performance very large scale integrated (VLSI) systems.
The topology of domino circuits for high-speed operation, lower power consumption and robustness is of
great importance in designing digital systems. Here we are designing a low-power high-speed full adder
circuit, which uses a new CMOS domino logic family based on magnetic tunnel junction (MTJ) elements
and memristor in gate diffusion input (GDI) technique. In comparison with a static CMOS logic circuit, a
dynamic logic circuit is of importance since it provides higher speed and requires fewer transistors. In
comparison with the recently proposed circuits for dynamic logic styles, very low dynamic power
consumption and less delay are the features of the proposed circuit. The problem with dynamic circuits is
the lack of a stable output at different times, while the proposed circuit preserves the output value using
memory elements such as MTJ and memristor during the clock cycle. The proposed technique shows a
maximum power consumption of 0.317 μW in MTJ/memristor-based full adders. The proposed technique
shows a maximum delay of 0.35 ns.
4. Introduction
In last few years, the use of internet of things (IoT) devices, cell phones, tablets and sensors has been
dramatically increased. Most of these devices are battery-powered, so power consumption (battery life) can
be considered as a design challenge. Non-conventional CMOS and nano-technology pave the way for
designing low-power electronics, which reduce the leakage power consumption, so low-power applications
can rely on emerging technologies in this area.
For reducing dynamic power consumption, the energy stored in load capacitors can be recovered instead of
being dissipated as heat. This technique is referred to as adiabatic (reversible) circuit design . Magnetic
tunnel junction (MTJ) is a non volatile memory with short access time and small dimensions as well as
compatibility with CMOS technology .
5. Introduction
Thus, it is well suited for using in logic-in-memory (LiM) architectures. LiM structures use MTJs and are
very suitable for low-power designs because of almost zero static power dissipation. Here a memristor is
also used as a memory element to design 1-bit full adder based on domino logic, and the results are
eventually compared with MTJ family. Low-power designs are of great importance as the demand for
battery-operated portable devices is ever-increasing. In a large number of this type of devices, the battery
life is more important than the operating speed. Nano-devices and adiabatic designs are used in LiM
structures to reduce, respectively, the static and dynamic power consumption. As an emerging technology,
MTJ has many advantages when used in LiM structures along with CMOS technology. The power
consumption of the proposed adiabatic MTJ/CMOS full adder is more than 7 times less than those of the
previous MTJ/CMOS full adders. In the presented domino logic is based on MTJ elements in gate
diffusion input (GDI) technique.
6. Introduction
A dynamic logic circuit is more interesting than a static CMOS logic circuit since it has higher speed and
requires fewer transistors. In comparison with the recently proposed circuits for dynamic logic styles, very
low dynamic power consumption and less delay are the features of the proposed circuit. Additionally, the
proposed circuit shows extreme fault tolerance. Standard 0,18 μm CMOS technology is used to simulate
the proposed full adder. Both memory cell and sensing amplifier in this type of circuit, however, are less
reliable, and this greatly limits the practical application of this type of circuit in logic computation. To
resolve this issue, a new magnetic full adder (MFA) is presented based on pre-charge sensing amplifier
(PCSA) and thermally assisted switching (TAS)-MTJ cell. A memristor is the fourth basic two–terminal
passive circuit element apart from well-known resistor, capacitor and inductor.
7. Motivation
The motivation to design a fast full adder circuit using domino logic and magnetic tunnel junctions is to
overcome the limitations of traditional CMOS-based adder circuits and create high-speed, low-power, and
accurate arithmetic circuits that can meet the growing demands of modern computing and other applications.
8. Problem statement
Traditional CMOS-based adder circuits are limited in speed and power efficiency, which can be a
bottleneck in high-performance computing, machine learning, cryptography, and other applications. The
goal is to design a fast full adder circuit using domino logic and magnetic tunnel junctions that can
operate at higher speeds and consume less power than traditional CMOS-based adder circuits. However,
designing such a circuit poses several challenges, including: High-speed operation, Power consumption,
Noise and reliability, Area efficiency.
9. Objectives
To create an arithmetic circuit that meets the following requirements
• High speed: The circuit should be able to perform addition operations quickly, with a short delay
between the input and output.
• Low power consumption: The circuit should consume minimal power, making it suitable for use in
low-power applications, such as mobile devices or IoT devices.
• High accuracy: The circuit should produce accurate results, with minimal errors or noise in the output.
10. Circuit diagram
Traditional CMOS-based adder circuits are limited in speed and power efficiency, which can be a bottleneck
in high-performance computing, machine learning, cryptography, and other applications. The goal is to
design a fast full adder circuit using domino logic and magnetic tunnel junctions that can operate at higher
speeds and consume less power than traditional CMOS-based adder circuits. However, designing such a
circuit poses several challenges, including: High-speed operation, Power consumption, Noise and reliability,
Area efficiency.
12. Proposed logic
Fig. 3: Proposed domino logic circuit.
Fig. 4: Schematic of the proposed final full adder based on MJT and memristor
13. Methodology
• Define the specifications of the full adder circuit, including its input and output bit- widths, power supply
voltage, operating frequency, and any other relevant parameters.
• Choose a suitable domino logic circuit topology for the full adder. Domino logic is a fast and energy-efficient
logic style that uses precharged nodes to reduce the delay of logic gates. Some common domino logic circuits
used for full adders include complementary CMOS (C2MOS), pass-transistor logic (PTL), and transmission
gate logic (TGL).
• Choose a suitable magnetic tunnel junction (MTJ) device for implementing the logic gates in the full adder
circuit. MTJs are non-volatile memory devices that can also be used as logic gates due to their high-speed
switching and low-power consumption.
14. Methodology
• Design the individual MTJ-based logic gates that will be used in the full adder circuit. This will involve
selecting the appropriate MTJ device parameters, such as the tunnel magnetoresistance (TMR) ratio,
switching current density, and critical current density, to ensure fast and reliable operation.
• Combine the individual logic gates to form the full adder circuit. This may involve cascading multiple stages
of domino logic gates to achieve the desired speed and performance.
• Simulate the full adder circuit using a cadence virtuoso simulator to verify its functionality and performance.
This will involve analyzing the circuit's timing, power consumption, and noise immunity, among other
parameters.
• Optimize the full adder circuit design as necessary to improve its performance or reduce its power
consumption. This may involve adjusting the device parameters or the circuit topology, or adding additional
stages of logic gates.
15. Working
In figure 3, the circuit consists of two clock transistor elements. In this circuit, when the clock and A both are
low, Z will be high and the output node will not change. The same is true when the clock is grounded and
input A is high. When the clock and A both are high, both Z and the output will be high. When the clock is
high and input A is low, Z will not change. In this condition, if Z is high (grounded), the output will be low
(high).
In figure 4, a full adder based on the novel domino logic circuit as well as MTJ and memristor components
as shown . In the proposed circuit, MTJ components are used in the output inverter to improve the circuit
performance to stay at stable values. Additionally, to reduce the delay due to the use of memory elements in
these circuits, we use discharge transistors to remove the electric charge from the z-storage node. This
reduces the power consumption and delays the main nodes.
20. Advantages
• High speed: Domino logic is a fast and efficient logic style that can operate at high clock frequencies, while
magnetic tunnel junctions can switch at high speeds. This makes a fast full adder circuit using these
technologies ideal for high-speed arithmetic circuits.
• Low power consumption: Domino logic and magnetic tunnel junctions both have low power consumption
compared to other logic styles and memory devices, respectively. This makes a fast full adder circuit based on
these technologies well-suited for low-power computing applications, such as mobile devices or IoT devices.
• Small area: Magnetic tunnel junctions are small in size and can be integrated into existing CMOS technology,
making a fast full adder circuit using these technologies compact and space-efficient.
21. Advantages
• Non-volatile memory: Magnetic tunnel junctions are non-volatile memory devices that can retain their state
even when power is turned off. This makes a fast full adder circuit based on these technologies well-suited for
use in memory applications, such as cache memory or register files.
• High noise immunity: Magnetic tunnel junctions are immune to noise and interference, making them reliable
and robust in noisy environments.
22. Applications
• High-speed arithmetic circuits: The fast and energy-efficient nature of domino logic and magnetic tunnel
junctions makes them well-suited for use in high-speed arithmetic circuits, such as adders and multipliers. A
fast full adder circuit using these technologies can be used to improve the performance and efficiency of such
circuits.
• Low-power computing: Magnetic tunnel junctions are non-volatile memory devices that can also be used as
logic gates. This makes them well-suited for use in low-power computing applications, such as mobile devices
or Internet of Things (IoT) devices, where energy efficiency is a critical consideration.
23. Applications
• Cryptography: Fast full adder circuits can also be used in cryptography applications, such as symmetric-key
encryption and decryption. The speed and efficiency of a full adder circuit using domino logic and magnetic
tunnel junctions can help to improve the performance of such cryptographic algorithms.
• Neural networks: Artificial neural networks (ANNs) are a type of machine learning algorithm that are used for
tasks such as image recognition and natural language processing. ANNs require high-speed and energy-
efficient arithmetic circuits, and a fast full adder circuit using domino logic and magnetic tunnel junctions can
be used to improve the performance and efficiency of such circuits in ANNs.
24. Conclusion
The design of a low-power, fast full adder using domino logic based on magnetic tunnel junction (MTJ)
and memristor technology presents a promising approach for improving the performance and energy
efficiency of digital circuits.
By utilizing MTJs and memristors, the proposed design takes advantage of their unique properties to
achieve low power consumption and high-speed operation. The use of domino logic, known for its
dynamic and energy-efficient nature, further enhances the overall performance of the full adder.
The magnetic tunnel junctions offer non-volatile memory capabilities, which can be utilized for storage
and retention of data. This feature enables the full adder to retain its state and reduce power consumption
during idle periods. The memristor technology provides additional benefits such as high scalability, low
energy operation, and compatibility with existing CMOS technology.
The combination of these advanced technologies in the design of the full adder results in improved power
efficiency and faster operation compared to traditional designs. This makes it suitable for applications
where low power consumption and high-speed processing are essential, such as in portable devices,
Internet of Things (IoT) systems, and battery-powered devices.
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