Computer Architecture refers to those attributes of a system that have a direct impact on the logical execution of a program. Examples: o the instruction set o the number of bits used to represent various data types o I/O mechanisms o memory addressing techniques

1. Computer Organization &Architecture
(CSIT-404)
B.Tech, 4th Sem CSIT

2. Overview
 Computer Arithmetic's
Addition and Subtraction
Tools compliment Representation
Signed Addition and Subtraction
 Multiplication Algorithms
 Division Algorithms
Booths Algorithm
Division Operation
Floating Point Arithmetic Operation
Design of Arithmetic unit
Unit-2
Computer Arithmetic

3. Computer Arithmetic’s
 Arithmetic Instruction Manipulate data to produce results necessary for
the solution of computational problem
 Four Basic Arithmetic Operations are – Addition, Subtraction,
Multiplication and Division
An arithmetic processor is the part of a processor unit that executes
arithmetic operations
Arithmetic operations can be performed for following data types
•Fixed point binary data in signed magnitude representation
•Fixed point binary data in signed 2’s complement representation
• Floating Point binary data
• Binary coded decimal data

4. Find 2’s complement of binary
number 10101110.

8. Addition and Subtraction
Example: Represent +9 and -9 in 7 bit-binary number
Only one way to represent + 9 ==> 0 001001
Three different ways to represent - 9:
In signed-magnitude: 1 001001
In signed-1's complement: 1 110110
In signed-2's complement: 1 110111
Fixed point numbers are represented either integer part only or fractional part only.
Representation of both positive and negative numbers
- Following 3 representations
Signed magnitude representation
Signed 1's complement representation
Signed 2's complement representation

9. Addition and Subtraction
Addition and Subtraction with Signed Magnitude Data
Operation Add
Magnitudes
Subtract Magnitudes
A>B A<B A=B
( + A ) + ( +
B )
+ ( A + B )
( + A ) + ( - B
)
+ ( A - B ) - ( B - A ) + ( A - B )
( - A ) + ( + B
)
- ( A - B ) + ( B - A ) + ( A - B )
( - A ) + ( - B ) - ( A + B )
( + A ) - ( + B
)
+ ( A - B ) - ( B - A ) + ( A - B )
( + A ) - ( - B ) + ( A + B )
( - A ) - ( + B ) - ( A + B )
( - A ) - ( - B ) - ( A - B ) + ( B - A ) + ( A - B )

10. Computer Arithmetic’s
 Addition (subtraction) Algorithm
 When the sign of A and B are identical (different) , add the
magnitudes and attach the sign of A to the result.
When the signs of A and B are different (identical), compare the
magnitudes and subtract the smaller number from the larger.
 Choose the sign of result to be same as A if A>B
 or the complement of sign of A if A<B
 if A=B subtract B from A and make the sign of result positive

11. Hardware Implementation
B Register
Complementer
Parallel Adder
A Register
Bs
E
AVF
As Load Sum
Input Carry
M (ModeControl)
Output Carry

12. Flow Chart for Add and Subtract Operation

13. Signed 2’s Complement Representation
 Addition :
 Addition of two numbers in signed 2’s complement form consists of
adding the numbers with the sign bits treated the same as the other
bits of the number. Carry out of sign bit is discarded
Sum is obtained by adding the content of AC and BR (including the
sign bit). Overflow bit is set to 1 if EX-OR of last two carries if 1
Subtraction :
Here Subtraction consists of first taking the 2’s complement of the
subtrahend and then adding it to minuend
Subtraction done by adding the content of AC to 2’s Complement of
BR.

15. Signed 2’s Complement Representation

16. Binary Multiplication
Sign of product determined from sign of Multiplicand and Multiplier , if same +ve else -ve

18. H/W implementation -Multiplication
For multiplication in hardware, process is slightly changed
1. In place of as Register equal to no. of multiplier bits, use
one adder and one Register
2. Instead of shifting multiplicand to left , partial product is
shifted right
3. When corresponding bit of multiplier is 0, no need to add
zero to partial product

19. H/W implementation -Multiplication

20. Flow Chart Binary Multiplication

22. Booth’s Multiplication Algorithm
Used for multiplication in Signed 2’s complement representation
It operates on the fact that strings of 0’s in the multiplier require no
addition but just shifting
And a string of 1’s in the multiplier from bit weight 2k to 2m can be
treated as 2k+1 – 2m
E.g. +14 (001110 ) here k=3, m=1 represented as 24-21 = 16-2 = 14
Thus M x 14= M x 24 – M x 21

23. Booth’s Multiplication Algorithm
Used for multiplication in Signed 2’s complement representation
Prior to shifting the multiplicand can be added to the partial product ,
subtracted from the partial product or left unchanged according to the
following rules :
1. The multiplicand is subtracted from partial product upon encountering
the first least significant 1 in the string of 1’s in the multiplier
2. The multiplicand is added to the partial product upon encountering the
first 0 (provided that there was a previous 1) in the string of 0’s in the
multiplier.
3. The partial product does not change when the multiplier bit is identical
to the previous multiplier bit

25. Booth’s Multiplication Algorithm

26. Example - Booth’s Multiplication Algorithm

27. Binary Division

28. Binary Division
For Division in hardware, process is slightly changed
1. Instead of shifting divisor to right, dividend or partial
remainder is shifted left
2. Subtraction achieved by adding A to 2’s complement of B
3. Information about Relative magnitude is available from
the end carry
Hardware components identical to that of multiplication

29. Flow Chart - Division

30. Example - Division

31.  The floating-point representation can implement operations for high
range values. The numerical evaluations are carried out using
floating-point values. It can create calculations easy, scientific
numbers are described as follows −
 The number 5,600,000 can be described as 0.56 * 107.
 Therefore, 0.56 is the mantissa and 7 is the value of the exponent.
 Binary numbers can also be described in exponential form. The
description of binary numbers in the exponential form is called
floating-point representation. The floating-point representation
breaks the number into two parts, the left-hand side is a signed.
fixed-point number known as a mantissa and the right-hand side of
the number is known as the exponent. The floating-point values are
also authorized with a sign; 0 denoting the positive value and 1
denoting the negative value.
 The general structure of floating-point representation of a binary
number −
x=(x0*20+x1*21+x2*22±−−∓b−(n−1)*2−(n−1) )
mantissa*2Exponent
In the following syntax, the decimal point is transferred left for negative
exponents of two and right for positive exponents of two. Both the mantissa and
the exponent are signed values enabling negative numbers and negative
exponents commonly.

32. Example − Convert 111101.1000110 into floating-point value.
111101.1000110 = 1.111011000110 * 25Converted to floating-point
value
→ Denotes negative sign value
 In this example, the integer value is converted to a floating-point
value by changing the radix point next to the signed integer and
scaling up the number to the exponential form by multiplying the
value with the base 2. The value remains unaltered and this phase
is known as the normalized method.
 Numbers too large for standard integer
representations or that have fractional
components are usually represented in
scientific notation, a form used commonly
by scientists and engineers.
• Examples:
4.25 ´ 101 10-3
-3.35 ´ 3 -1.42 ´ 102