This document provides a tutorial for using Quartus II's SignalTap II Logic Analyzer. It explains how to compile a design project, select the SignalTap II tool, add nodes to analyze signals, choose a clock, set the sample depth and triggers, compile and program the design on an FPGA board, and run signal analysis. Some tips are provided, such as selecting the proper clock and reducing unnecessary nodes to view more signal transitions within the sample depth limitations. References for more information are also included.
A summary of current conveyors is presented, with focus on origin, ideal terminal behaviour, hardware implementations, parasitic elements & their effects, comparison with op amps, varieties and current research areas.
This presentation demonstrate:
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- Basics of Multi-Standard receivers.
- How to select receiver's specifications from the selected standard.
- Subsampling basics.
A summary of current conveyors is presented, with focus on origin, ideal terminal behaviour, hardware implementations, parasitic elements & their effects, comparison with op amps, varieties and current research areas.
This presentation demonstrate:
- Different RF receiver architectures.
- Basics of Multi-Standard receivers.
- How to select receiver's specifications from the selected standard.
- Subsampling basics.
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In telecommunication, an eye pattern, also known as an eye diagram, is an oscilloscope display in which a digital signal from a receiver is repetitively sampled and applied to the vertical input, while the data rate is used to trigger the horizontal sweep. It is so called because, for several types of coding, the pattern looks like a series of eyes between a pair of rails. It is a tool for the evaluation of the combined effects of channel noise and intersymbol interference on the performance of a baseband pulse-transmission system. It is the synchronised superposition of all possible realisations of the signal of interest viewed within a particular signaling interval.
This presentation covers:
Some basic definitions & concepts of digital communication
What is Phase Shift Keying(PSK) ?
Binary Phase Shift Keying – BPSK
BPSK transmitter & receiver
Advantages & Disadvantages of BPSK
Pi/4 – QPSK
Pi/4 – QPSK transmitter & receiver
Advantages of Pi/4- QPSK
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
Challenges and experiences with IPTV from a network point of viewbrouer
OpenSource IPTV MPEG2-TS analyzer.
This presentation was given at OpenSourceDays 2010 (and in earlier stages of the project at Bifrost Workshop 2009 and 2010)
Prometheus - Intro, CNCF, TSDB,PromQL,GrafanaSridhar Kumar N
https://www.youtube.com/playlist?list=PLAiEy9H6ItrKC5PbH7KiELiSEIKv3tuov
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Tutorial for Quartus II’s SignalTap II Logic Analyzer
1. Tutorial for Quartus II‟s SignalTap
II Logic Analyzer
Compiler and Microarchitecture Lab.
Korea University
Joon Goo Lee
11/27, 2013
2. Purpose
• To analyze post-layout signals for
debugging without an actual logic analyzer.
• To capture meaningful signals for a report,
a paper, or further analysis.
3. Tested Environment
• FPGA Board
– DE0-Nano: Cyclone IV EP4CE22F17C6N
• IDE
– Quartus II 64-Bit 13.1 Web Edition (This is
free version)
• JTAG programmer
– USB-Blaster
5. Compile a completed project
• Compile your project.
– Set pin assignments.
– Should have no error.
6. Select SignalTap II Logic Analyzer
• After compilation
– Ensure the JTAG programmer (USB-Blaster) is
connected between the board and your PC.
– Your board should be powered.
• With DE0-Nano, connected USB cable for JTAG gives
power as well.
– Open SignalTap II Logic Analyzer by selecting
“Tools | SignalTap II Logic Analyzer”
• You can open pre-existing SignalTap II Logic Analyzer
file (*.stp) from “File | Open”.
• You can also open the SignalTap II Logic Analyzer by
selecting “File | New | Other Files | SignalTap II Logic
Analyzer File”.
7. Select Hardware
• Select Hardware
– If not appear USB-Blaster, click Setup to
select the programmer
8. Add nodes to be analyzed (1/2)
• Double click to add necessary nodes.
• Click List to view nodes. (You can use Filter)
9. Add nodes to be analyzed (2/2)
• Select nodes.
• Click OK
– You may see warning
message when you
add netlist type nodes
or unassigned nodes).
– Whenever you see
the message, simply
click Yes.
10. Select proper clock
• Basically, the clock need to
be set to FPGA clock.
• If you want to see signals
based on other clock,
choose the clock.
– However, signals may be
distorted.
• Quartus II may remove
duplicated signal if you
added the same node. Just
click OK.
11. Choose Sample depth and Set trigger(s)
• Sample depth depends on
RAM attached to FPGA and
the number of nodes (or the
frequency of transition) you
added.
• You can set multiple
triggers.
– Select node you want by
using Node Finder.
– Set Pattern.
12. Compile your project
• After setting for SignalTap II Logic Analyzer,
you need to compile your project again.
– If you see the warning message, click Yes.
– If you want to save all the configurations, save
„stp‟ file.
– Enable SignalTap II file for the current project.
(You‟ll see the related message. Click Yes.)
• Rest until compilation done.
– When you see error messages, halve the sample
depth until compilation done without error.
13. Select „sof‟ file and program your code
• Select „sof‟ file to be
downloaded first.
• Program your project
on the board.
2. Program
your code
1. Click to
choose sof file
14. Run analysis
• Run analysis to view signals.
– Note: Clock will not be viewed.
Autorun analysis to view signals continually.
Run analysis to view signal transitions. It only shows transitions until buffer is full.
15. Limitations and tips
•
If you add nodes that have high-frequency transition, the time duration will be shorten.
–
–
•
As I mentioned before, „Sample depth‟ depends on RAM and the nodes you added.
If you add small number of nodes, you may increase the „Sample depth‟.
Tips.
–
–
–
–
Select proper clock to see more transitions.
Remove unnecessary nodes.
Set trigger(s) carefully.
For bus signals
•
•
Add individual nodes for a bus, and then group the nodes in the signal view window.
Grouped signals can choose “Bus Display Format”.
You can see more transitions
by choosing proper clock
and reduced number of nodes.
16. References
• Mike Pridgen, “Tutorial for Quartus‟
SignalTap II Logic Analyzer”,
http://www.mil.ufl.edu/4712/docs/SignalTa
p_Tutorial.pdf
• Altera homepage.
http://quartushelp.altera.com/13.1/master.
htm