Tran Thanh An is a design verification engineer at Renesas Design Vietnam with over 2 years of experience in SOC verification. He has strong skills in formal verification using Jasper Gold tools and experience with functional design, logic design, front-end verification using SystemVerilog and ARM Assembly. He has verified modules like PFC, GPIO, and PAD using simulation and formal verification methods. He is currently working on designing and verifying the PFC and GPIO modules in an SOC.

1. TRAN THANH AN
Design Verification Engineer
Date of birth: September 27, 1994
Gender: Male
Phone: +84382651530
Email: antrandx@gmail.com
Address: Quang Nam, Vietnam
BACKGROUND
From 2012 – 2017 : Studied Electronic at Da Nang University of Science and Technology
GPA: 3.05/4
EXPERIENCE SUMMARY
I am working as a Design verification engineer at Renesas Design Vietnam and have 2 years in SOC verification. I am
very strong in Formal Verification by using Jasper Gold tool (JG-FPV, JG-CSR and JG-Xprop, JG-CNN and JG-
COV).In addition to it, I have hands on experience in Functional Design and Logic Design. I intent to build my career
in the area of VLSI by working on the emerging technologies related to this filed and further strengthening my skill
sets.
 Experience in front-end verification using ARM Assembly, System Verilog and RTL design
 Expertise in verification tool Synopsys VCS, Cadence Xcelium
 Good in Assertion based verification
 Exposure to AMBA protocols (APB, AXI)
 Strong in Analytical, Coding, Logic Thinking and Debug skill
 Good team work
SKILL SUMMARY
Operation systems : Window and Linux
Languages : Verilog , System Verilog Assertion , C, ARM Assembly , Perl, Cshell
Tool : VCS, Xcelium , Verdi, Jasper Gold
OTHER SKILL
English language :
- TOEIC 730
- Good communication both of written and spoken
HONORS & AWARDS
1.Gold annual prize of Renesas for project by using Formal verification in December 2018
2. 24th
MVP (Most Valuable Person ) nominee in April 2019

2. PROJECT SUMMARY
Bus motoring system
(University Project In 2017)
This is project of my team in Vietnam Makers contest with Intel Galileo
2017
My role : - Make the idea for project
- Coding and building up system
Award: Top 15 excellent team
Capstone project at FPT Software
Da Nang
(From Jan.2017 – June.2017)
Project name : Control home devices by using Raspberry Pi and ARM
board
-This project is focused on embedded system
-My role : Coding in ARM board to connect all devices with Gateway
Rcar-Gen3 (1st)
(From Oct. 2017 – Jan.2019)
Verification of Pin function control (PFC) module in SOC
This module is used to control pin of SOC. It has a lot of registers. In
pervious projects, it was verified by directed testing, so the verification
cannot be cover all cases
So that, I used the Jasper Gold Control and Status Register ( JG CSR) tool
to verify all registers of PFC module
Responsibilities :
- Investigating guideline document and having discussions with
Cadence to build up environment from zero
- Main debugging and analyzing results
- Using Jasper Gold Coverage (JG COV) to get coverage of
environment and design
Verification of General Purpose Input/Output (GPIO ) module in SOC
Responsibilities :
I used simulation and formal verification methodology to verify this module
For simulation: using VCS tool
I made strategy for testing plan, made patterns to checking and used SVA to
check result of simulation
For formal verification : using Jasper Gold Formal Property Verification (
JG FPV) tool
I have responsibilities for building up environment, executing and
debugging
Verification of Pin arrangement design (PAD) module in SOC
I used Jasper Gold Connectivity (JG - CNN)
Responsibilities :
Referred old environment to build up according environment with
improvement
Executed environment , analyzed and debugging fail results

3. Rcar-Gen3 (2nd)
(From Feb.2019- Till date)
Design and Verification PFC, GPIO modules in SOC
Responsibilities :
Design :
-Make updating specification as request of customer
-Implement updating specification by coding RTL
-Design clock specification
- Synthesis
-Confirm checker errors (STA, DFT, HLDRC)
Verification :
-Make verification strategy and checking items list
-Creating pattern from checklist
- Judgement , analyzing and debugging result
BUS System Test (Checking performance of SOC )
Responsibilities :
-Building up environment base on UVM
-Analyzing, judgment result and debug if any failed patterns