Bachelor's Thesis: Use of CAD technologies to optimize the productivity of a ...Pietro Galli
The Thesis was developed during the Internship at Plurigest SRL. It deals with one of the projects done during that experience. In particular the aim of this was to provide a plant layout for a Pellet Heating system.
All the components of the plant were designed on Solidworks and AutoCAD. Then was performed a study of the layout of the components in order to provide best solution in terms of space used and functioning.
If you’d like discover more about this project in the attachment there is the pdf version of the thesis (Italian language) and some pictures. For more info please contact me
TravelStory is a cross-platform mobile application developed with Xamarin.forms. The application and the related back-end (Microsoft Azure) have been developed for my bachelor thesis.
The application is aimed at tourists who want to share their travel experience. The application is launched and the user can create a new account or just log in. On the home they are asked to create a new trip or if already it's present they continue with the last. It will be the tourist to choose when to save his important points. These points are identified by a GPS position and can be enhanced with photos, videos and notes. These contents are pinpointed and at the end of the trip the entire path can be shared through an external platform. The finished trips can be viewed at any time and can be managed completely.
Bachelor's Thesis: Use of CAD technologies to optimize the productivity of a ...Pietro Galli
The Thesis was developed during the Internship at Plurigest SRL. It deals with one of the projects done during that experience. In particular the aim of this was to provide a plant layout for a Pellet Heating system.
All the components of the plant were designed on Solidworks and AutoCAD. Then was performed a study of the layout of the components in order to provide best solution in terms of space used and functioning.
If you’d like discover more about this project in the attachment there is the pdf version of the thesis (Italian language) and some pictures. For more info please contact me
TravelStory is a cross-platform mobile application developed with Xamarin.forms. The application and the related back-end (Microsoft Azure) have been developed for my bachelor thesis.
The application is aimed at tourists who want to share their travel experience. The application is launched and the user can create a new account or just log in. On the home they are asked to create a new trip or if already it's present they continue with the last. It will be the tourist to choose when to save his important points. These points are identified by a GPS position and can be enhanced with photos, videos and notes. These contents are pinpointed and at the end of the trip the entire path can be shared through an external platform. The finished trips can be viewed at any time and can be managed completely.
“50 ft Daysailer’s Preliminay Design” - master's degree thesis by Stefano MaranoStefano Marano
“50 ft Daysailer’s Preliminay Design” - master's degree thesis by Stefano Marano.
General plans, sail plan, performance prediction, stability and scantlings according to ISO regulations, canting keel, zero-emission propulsion, rig design
Presentation of the thesis - FIrst degree (April 2006). Design and development of a Network Management System for wireless networks in Mesh AP configuration.
Presentazione della tesi triennale (Aprile 2006). Progettazione e sviluppo di un Network Management System per reti wireless in configurazione Mesh-AP.
This document contains the final presentation slides for Bogdan Vasilescu's analysis of advanced aggregation techniques for software metrics. The presentation explores using inequality indices from econometrics to measure the concentration of software metrics across different levels of a system. It studies properties of traditional aggregation, inequality indices, and threshold-based techniques. An empirical evaluation of correlations between aggregated metrics and defects is presented, with results showing that some inequality indices convey the same information.
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1) The document introduces Alexei Kapterev, who published a popular presentation on presentation skills 4 years ago and has since become an expert in the field.
2) While most presentations still suffer from issues like poor structure, bad slides, and boring delivery, Kapterev believes everyone can learn to present well by focusing on a few key principles rather than rules.
3) The principles of focus, contrast, and unity are described as more effective than rules, and examples are given of how to apply these principles to structure, slides, and delivery.
The document provides tips for designing and delivering effective presentations. It discusses the importance of design principles like contrast, alignment, proximity and using visuals like photos and charts to engage audiences. Specific tips include limiting text on slides, using no more than two font styles, constraining the number of words and bullet points per slide. For delivery, it recommends practicing your presentation, engaging the audience, speaking conversationally and finishing strongly by reiterating your key messages. The overall message is that effective presentation requires considering both design and delivery techniques to communicate clearly and hold audience attention.
7 Tips to Beautiful PowerPoint by @itseugenecEugene Cheng
Short talk about presentations given at Startup Dynamo, a workshop held by Startup@Singapore NUS using the Learn Startup Methodology.
My segment was on Presentation Design to make an impact on VCs. Many thanks to @ryanlou for the invite. And not to forget Emiland De Cubber for his amazing slide deck inspirations and invaluable advice. Disclaimer: this is a reimagination off some of Emiland's presentations. I do not make any money of this.
Download for just a tweet: http://goo.gl/fbM4j
Want something similar done for your next pitch? Contact me at my site: http://itseugene.me/contact/
This document is a presentation about designing effective PowerPoint slides. It provides tips over several slides on how to design slides with a killer title and opening slide, use of color schemes and images, getting the text right, using the principles of contrast, repetition, alignment and proximity (CRAP), incorporating video, sharing the presentation online, and recapping the key tips. The presentation emphasizes the importance of visual design over text-heavy slides and using techniques like strong images and video to engage the audience in a way words alone cannot. It provides examples throughout to illustrate its tips.
This is a basic implementation of the famous game Arkanoid running on a FPGA that I've developed for the final project of Electronic II FPGA course at the University of Trieste.
The development board I've used is TERASIC DE1 with Cyclone II FPGA by Altera.
Features:
- 6 different angles of impact for the sphere.
- The ball striking a brick causes the brick to disappear.
- When all the bricks are gone, the player has won.
- Some bricks are indestructible.
- The Player has 3 lives to win the game.
- Start/Pause and restart game button.
For More Informations and for the english version look at this: http://www.vuolsavest.net/t3o/arkanoidFpga/
Relazione sul progetto di realizzazione di un algoritmo di localizzazione (mediante trilaterazione) attraverso l'utilizzo del controllore cRIO e del software LabVIEW.
Relazione sul progetto di realizzazione di un algoritmo di localizzazione (mediante trilaterazione) attraverso l'utilizzo del controllore cRIO e del software LabVIEW.
Il progetto SINERGIE si propone di sviluppare nuove soluzioni integrate hardware/software per la movimentazione ad elevata dinamica in macchine automatiche. In particolare, il progetto affronta in modo sinergico due aree tematiche principali, con l’obiettivo di migliorare le prestazioni dinamiche e le caratteristiche costruttive delle macchine di domani:
Strumenti SW per la progettazione e il controllo
Dispositivi contactless e wireless per misure, trasmissione segnali ed attuazione
Principali filiere coinvolte: Macchine automatiche, Meccanica, Packaging, ICT
Sito web del progetto: www.sinergieproject.it
SOFREL S4W - La telegestione 4.0 per reti idriche connesseLACROIX Sofrel Srl
SOFREL S4W: LA TELEGESTIONE 4.0
PER RETI IDRICHE CONNESSE
SOFREL S4W rientra in una strategia aziendale orientata alle tecnologie connesse. Con S4W, LACROIX Sofrel affronta nuove sfide e adotta un nuovo approccio nella gestione in remoto degli impianti, facendo entrare la telegestione in una nuova era, quella della telegestione 4.0.
Frutto di 5 anni di sviluppo e di 40 anni di esperienza nel settore della telegestione, SOFREL S4W è progettato per rispondere alle nuove esigenze dei gestori delle reti idriche. Oltre a essere un prodotto industriale compatto, ergonomico, facile da implementare e totalmente connesso, la piattaforma S4W è associata a una serie di soluzioni destinate a semplificare la gestione delle reti di telegestione e ad affrontare con successo le principali sfide di cybersicurezza.
1. The document discusses Diopsis940, a microcontroller product from Atmel that features an ARM9 processor and floating point DSP for consumer applications.
2. It provides details on target applications including hands-free phones, high-end car audio, and sound processors. The microcontroller supports complex audio processing algorithms.
3. hArtes, an Atmel division, aims to reduce application development time through tools that streamline the process from conceptual design to implementation using their microcontroller products.
The document proposes a coarse-grain reconfigurable array (CGRA) for accelerating digital signal processing. The CGRA aims to provide an intermediate tradeoff between flexibility and performance compared to FPGAs and ASICs. It consists of an array of processing elements and distributed memory interconnected via programmable switches. Evaluation shows the CGRA achieves 4.8-8X speedup, 24-58% improved energy efficiency, and up to 40% reduced area compared to a Xilinx Virtex-4 FPGA for applications like color space conversion, FIR filtering, and DCT.
This document discusses Altera's FPGA strategy for reconfigurable hardware in industry applications. It defines reconfigurable hardware as an architecture that does not require on-the-fly timing analysis because product qualification is extensively done through temperature and cycle testing without hardware architecture changes. It then shows how programmable solutions have evolved from single CPU and DSP cores to multi-core processors and coarse-grained arrays with FPGAs moving to fine-grained, massively parallel arrays with embedded hard IP blocks. Future trends include challenges of scaling CPUs due to physical limits and the benefits of parallelism through hardware reconfiguration.
The document describes processes in VHDL. It defines a process as a concurrent statement that contains sequential logic. Processes run in parallel and can be conditioned by a sensitivity list or wait statement. Local variables retain their values between executions. It provides an example of a process with a sensitivity list and one with a wait statement. It also summarizes the general structure of a VHDL program and describes different types of process control including if-then-else, case statements, and decoders. Additional topics covered include flip-flops, counters, and finite state machines.
The document discusses requirements for enabling self-adaptivity at both the software and hardware levels. It proposes a layered model with controllers at the application, run-time environment, and hardware levels. A component-based approach is suggested to allow adaptations such as replacing or modifying components. Simulation results demonstrate how controllers at each level can coordinate to meet goals like high throughput while minimizing power usage. Reconfigurable computing platforms need to allow hardware components to be instantiated and interconnected to enable self-adaptation across software and hardware.
The document summarizes research on task scheduling techniques for dynamically reconfigurable systems. It presents (1) an integer linear programming model to formally define the scheduling problem, (2) the Napoleon heuristic scheduler to solve the problem in reasonable time based on the ILP model, and (3) experimental results validating that Napoleon obtains an average 18.6% better schedule length than other algorithms. Future work is outlined to integrate Napoleon into a general design framework and scheduling-aware partitioning flow.
The document summarizes key topics in reconfigurable computing, including motivations for reconfigurable systems, types of flexibility they provide, and challenges in reconfiguration. It discusses design flows to reduce complexity, maximizing reuse of reconfigurable modules to reduce latency, hiding reconfiguration times, and using relocation to further optimize schedules. Areas of reconfiguration and possible implementation scenarios involving relocation are illustrated.
The document discusses an approach for identifying cores for reconfigurable systems driven by specification self-similarity. It involves partitioning a specification graph into subsets of operations that can be mapped to reusable configurable modules. The approach identifies recurrent subgraphs in the specification that are good candidates for these cores. It works in two phases: first identifying isomorphic subgraph templates, and then selecting templates for implementation as reconfigurable modules based on metrics like largest size, most frequent usage, or minimizing communication. Experimental results on encryption benchmarks show the approach can cover a large portion of the specification with a small set of identified templates.
This document summarizes techniques for core allocation and relocation management in self-dynamically reconfigurable architectures. It introduces basic concepts like cores, IP cores, and reconfigurable regions. It then describes proposed 1D and 2D relocation solutions like BiRF and BiRF Square that allow runtime relocation with low overhead. A core allocation manager is introduced to choose core placements optimizing criteria like rejection rate and completion time with low management costs. Evaluation shows the techniques improve metrics like rejection rate and routing costs compared to other approaches.
The document discusses an hardware application platform developed for the hArtes project. It provides heterogeneous computing resources like DSPs, CPUs and FPGAs. Demonstrator applications focus on advanced audio processing for car infotainment and teleconferencing. The platform supports these applications by integrating different components, scaling computational power, and accommodating future additions. It also provides adequate I/O channels for audio signal processing.
The document describes the Janus system, an FPGA-based approach for simulating spin glass systems using Monte Carlo algorithms. The key aspects are:
1) Spin glass systems are computationally challenging to simulate due to the huge number of possible configurations.
2) The Janus system uses FPGAs to implement a large number of parallel update engines that can flip spins and accept/reject changes according to a Metropolis algorithm.
3) Each FPGA processor grid contains 4x4 processors that can communicate with neighbors. This allows simulations to be massively parallelized across the FPGA network.
The document outlines the agenda for the Reconfigurable Computing Italian Meeting held on December 19, 2008 at Politecnico di Milano in Milan, Italy. The agenda included four sessions on trends in reconfigurable computing, the hArtes European project, applicative scenarios, and the High Level Reconfiguration project. Each session included 3-4 presentations on technical topics within the session theme, such as FPGA strategies, multi-core signal processing, evolvable hardware, and runtime core relocation management. The meeting concluded with wishes for a merry Christmas and a happy new year.
This document provides an overview of architectural description languages (ADLs). It discusses that ADLs capture the structure and behavior of processor architectures to enable high-level modeling, analysis, and automatic prototype generation. ADLs can be classified as structural, behavioral, or mixed. Structural ADLs focus on low-level hardware details while behavioral ADLs model instruction sets for compiler generation. The document outlines different ADL types and their applications.
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