The document discusses the BondMachine Toolkit, which enables machine learning on FPGA. It provides an overview of FPGAs and modern computer architectures. The BondMachine architecture dynamically generates computer architectures composed of many small heterogeneous cores on an FPGA. The cores are connected processors that can be configured and interconnected in different ways. The goal is to optimize architectures for specific computational problems like machine learning.
The BondMachine: a fully reconfigurable computing ecosystemMirko Mariotti
The aim of the BondMachine (BM) project is to implement a computing system to enable a real and full exploitation of the underlying hardware. This is a key to the success in the era of hybrid computing. In order to achieve this objective the BM has been designed to create a heterogeneous and flexible architecture on top of FPGAs. Moreover the overall vision is based on a reduction of the number of hardware/software layers which by product guarantees a simpler software development. As such, the BM project has been thought as a complete reconfigurable computing ecosystem that, starting from a high-level description, creates both the hardware and the software that runs on it.
The two architectural pillars are computing elements (processors) and non-computing elements (for example memories, channels, barriers). The latter are meant to be shared among processors. Finally, thanks to a custom network protocol, many BondMachines can be interconnected together, therefore building heterogeneous multi-core systems or even clusters of multi-cores.
The flexibility of the BM makes possible the implementation of any computing system ranging from networks of small agents, like IoT (Internet of Things), to high-performance devices for ML (Machine Learning) or real time data analysis, and even systems that mix all this different characteristics together. The BM can interact with standard Linux workstations both as a special purpose hardware accelerator or as part of a computer/BM hybrid clusters.
BondMachine slides for the InnovateFPGA 2018 Grand FinalMirko Mariotti
The BondMachine Project reached the InnovateFPGA 2018 Grand Final. These are the slides of the presentation of the project given at the Intel Campus in San Jose on the 15th of August 2018
Hardware/Software Co-Design for Efficient Microkernel ExecutionMartin Děcký
While the performance overhead of IPC in microkernel multiserver operating systems is no longer considered a blocker for their practical deployment (thanks to many optimization ideas that have been proposed and implemented over the years), it is undeniable that the overhead still does exist and the more fine-grained the architecture of the operating system is (which is desirable from the reliability, dependability, safety and security point of view), the more severe performance penalties due to the IPC overhead it suffers. A closely related issue is the overhead of handing hardware interrupts in user space device drivers. This talk discusses some specific hardware/software co-design ideas to improve the performance of microkernel multiserver operating systems.
One reason for the IPC overhead is the fact that current hardware and CPUs were never designed with microkernel multiserver operating systems in mind, but they were rather fitted for the traditional monolithic operating systems. This calls for an out-of-the-box thinking while designing instruction set architecture (ISA) extensions and other hardware features that would support (a) efficient communication between isolated virtual address spaces using synchronous and asynchronous IPC primitives, and (b) treating object references (e.g. capability references) as first-class entities on the hardware level. A good testbed for evaluating such approaches (with the potential to be eventually adopted as industry standard) is the still unspecified RV128 ISA (128-bit variant of RISC-V).
This talk discusses some specific hardware/software co-design ideas to improve the performance of microkernel multiserver operating systems.
The BondMachine: a fully reconfigurable computing ecosystemMirko Mariotti
The aim of the BondMachine (BM) project is to implement a computing system to enable a real and full exploitation of the underlying hardware. This is a key to the success in the era of hybrid computing. In order to achieve this objective the BM has been designed to create a heterogeneous and flexible architecture on top of FPGAs. Moreover the overall vision is based on a reduction of the number of hardware/software layers which by product guarantees a simpler software development. As such, the BM project has been thought as a complete reconfigurable computing ecosystem that, starting from a high-level description, creates both the hardware and the software that runs on it.
The two architectural pillars are computing elements (processors) and non-computing elements (for example memories, channels, barriers). The latter are meant to be shared among processors. Finally, thanks to a custom network protocol, many BondMachines can be interconnected together, therefore building heterogeneous multi-core systems or even clusters of multi-cores.
The flexibility of the BM makes possible the implementation of any computing system ranging from networks of small agents, like IoT (Internet of Things), to high-performance devices for ML (Machine Learning) or real time data analysis, and even systems that mix all this different characteristics together. The BM can interact with standard Linux workstations both as a special purpose hardware accelerator or as part of a computer/BM hybrid clusters.
BondMachine slides for the InnovateFPGA 2018 Grand FinalMirko Mariotti
The BondMachine Project reached the InnovateFPGA 2018 Grand Final. These are the slides of the presentation of the project given at the Intel Campus in San Jose on the 15th of August 2018
Hardware/Software Co-Design for Efficient Microkernel ExecutionMartin Děcký
While the performance overhead of IPC in microkernel multiserver operating systems is no longer considered a blocker for their practical deployment (thanks to many optimization ideas that have been proposed and implemented over the years), it is undeniable that the overhead still does exist and the more fine-grained the architecture of the operating system is (which is desirable from the reliability, dependability, safety and security point of view), the more severe performance penalties due to the IPC overhead it suffers. A closely related issue is the overhead of handing hardware interrupts in user space device drivers. This talk discusses some specific hardware/software co-design ideas to improve the performance of microkernel multiserver operating systems.
One reason for the IPC overhead is the fact that current hardware and CPUs were never designed with microkernel multiserver operating systems in mind, but they were rather fitted for the traditional monolithic operating systems. This calls for an out-of-the-box thinking while designing instruction set architecture (ISA) extensions and other hardware features that would support (a) efficient communication between isolated virtual address spaces using synchronous and asynchronous IPC primitives, and (b) treating object references (e.g. capability references) as first-class entities on the hardware level. A good testbed for evaluating such approaches (with the potential to be eventually adopted as industry standard) is the still unspecified RV128 ISA (128-bit variant of RISC-V).
This talk discusses some specific hardware/software co-design ideas to improve the performance of microkernel multiserver operating systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of Quintuple Processor Architecture Using FPGAIJERA Editor
The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.
SIT is proud to be part of the global movement in confronting COVID-19 by moving some SIT operations into an online format.
At the #SITinsights in Technology talk, we’re blending computing and economics, bringing knowledge and expertise from all relevant fields to help enable global efforts.
There are many challenges on FPGA design such as: FPGA Selection, System Design Challenges, Power and Resource optimization, Verification of Design etc.
Each and every FPGA Engineer face this challenges, so if they prepare for such challenges then they can accomplish and optimize FPGA based project or design in time and within budget.
For more details and consultation: www.digitronixnepal.com, email: digitronixnepali@gmail.com
FPGA Selection Methodology for Real time projectsKrishna Gaihre
How to Select FPGA Chip (Vendor/Family/Series) for your Project?
Different FPGA families from Xilinx, Altera,Microsemi and Lattice have different features and cost range, so we are assisting you for how to select FPGA chip according to your project requirement.
If you are interested to design your project on FPGA platform, then you can consult us for how to select best FPGA Family and Class.
for more detail: www.digitronixnepal.com or email: digitronixnepali@gmail.com
Course: "Introductory course to HLS FPGA programming"Mirko Mariotti
Slides of the course: "Introductory course to HLS FPGA programming", Nov 27 – 30, 2023. ICSC National research center on HPC, big data and Quantum Computing
Slides of the talk at: "Joint ICTP-IAEA School on FPGA-based SoC and its
Applications to Nuclear and Scientific Instrumentation". 14 November - 02 December 2022 ICTP, Trieste, Italy
International Journal of Computational Engineering Research(IJCER) ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Performance Optimization of SPH Algorithms for Multi/Many-Core ArchitecturesDr. Fabio Baruffa
In the framework of the Intel Parallel Computing Centre at the Research Campus Garching in Munich, our group at LRZ presents recent results on performance optimization of Gadget-3, a widely used community code for computational astrophysics. We identify and isolate a sample code kernel, which is representative of a typical Smoothed Particle Hydrodynamics (SPH) algorithm and focus on threading parallelism optimization, change of the data layout into Structure of Arrays (SoA), compiler auto-vectorization and algorithmic improvements in the particle sorting. We measure lower execution time and improved threading scalability both on Intel Xeon (2.6× on Ivy Bridge) and Xeon Phi (13.7× on Knights Corner) systems. First tests on second generation Xeon Phi (Knights Landing) demonstrate the portability of the devised optimization solutions to upcoming architectures.
An FPGA is a programmable logic device with a reconfigurable gate array logic circuits matrix.
To know more about “FPGA Design, Architecture and Applications,” click on the link https://www.logic-fruit.com/blog/fpga/fpga-design-architecture-and-applications/
About Logic Fruit Technologies
Logic Fruit Technologies is a product engineering R&D & consulting services provider for embedded systems and application development. We provide end-to-end solutions from the conception of the idea and design to the finished product. We have been servicing customers globally for over a decade.
The company has specific experience in various fields, such as
-FPGA Design & hardware design
-RTL IP Design
-A variety of digital protocols
-Communication buses as1G, 10G Ethernet
-PCIe
-DIGRF
-STM16/64
-HDMI.
Logic Fruit Technologies is also an expert in developing,
-software-defined radio (SDR) IPs
-Encryption
-Signal generation
-Data analysis, and
-Multiple Image Processing Techniques.
Recently Logic Fruit technologies are also exploring FPGA acceleration on data centers for real-time data processing.
**Our Social Media Channels**
Facebook: https://www.facebook.com/LogicFruit/
Twitter: https://twitter.com/logicfruit
LinkedIn: https://www.linkedin.com/company/logi…
Website: https://www.logic-fruit.com/
#LFT #LogicFruitTechnologies #LogicFruit
Interested to view more Slide Shares, Click on the below links,
https://www.slideshare.net/LogicFruit/a-designers-practical-guide-to-arinc-429-standard-3pptx
https://www.slideshare.net/LogicFruit/a-swift-introduction-to-milstd
https://www.slideshare.net/LogicFruit/arinc-the-ultimate-guide-to-modern-avionics-protocol/LogicFruit/arinc-the-ultimate-guide-to-modern-avionics-protocol
https://www.slideshare.net/LogicFruit/arinc-629-digital-data-bus-specifications/LogicFruit/arinc-629-digital-data-bus-specifications
https://www.slideshare.net/LogicFruit/afdx
https://www.slideshare.net/LogicFruit/end-system-design-parameters-of-the-arinc-664-part-7
https://www.slideshare.net/LogicFruit/compute-express-link-cxl-everything-you-ought-to-know
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of Quintuple Processor Architecture Using FPGAIJERA Editor
The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.
SIT is proud to be part of the global movement in confronting COVID-19 by moving some SIT operations into an online format.
At the #SITinsights in Technology talk, we’re blending computing and economics, bringing knowledge and expertise from all relevant fields to help enable global efforts.
There are many challenges on FPGA design such as: FPGA Selection, System Design Challenges, Power and Resource optimization, Verification of Design etc.
Each and every FPGA Engineer face this challenges, so if they prepare for such challenges then they can accomplish and optimize FPGA based project or design in time and within budget.
For more details and consultation: www.digitronixnepal.com, email: digitronixnepali@gmail.com
FPGA Selection Methodology for Real time projectsKrishna Gaihre
How to Select FPGA Chip (Vendor/Family/Series) for your Project?
Different FPGA families from Xilinx, Altera,Microsemi and Lattice have different features and cost range, so we are assisting you for how to select FPGA chip according to your project requirement.
If you are interested to design your project on FPGA platform, then you can consult us for how to select best FPGA Family and Class.
for more detail: www.digitronixnepal.com or email: digitronixnepali@gmail.com
Course: "Introductory course to HLS FPGA programming"Mirko Mariotti
Slides of the course: "Introductory course to HLS FPGA programming", Nov 27 – 30, 2023. ICSC National research center on HPC, big data and Quantum Computing
Slides of the talk at: "Joint ICTP-IAEA School on FPGA-based SoC and its
Applications to Nuclear and Scientific Instrumentation". 14 November - 02 December 2022 ICTP, Trieste, Italy
International Journal of Computational Engineering Research(IJCER) ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Performance Optimization of SPH Algorithms for Multi/Many-Core ArchitecturesDr. Fabio Baruffa
In the framework of the Intel Parallel Computing Centre at the Research Campus Garching in Munich, our group at LRZ presents recent results on performance optimization of Gadget-3, a widely used community code for computational astrophysics. We identify and isolate a sample code kernel, which is representative of a typical Smoothed Particle Hydrodynamics (SPH) algorithm and focus on threading parallelism optimization, change of the data layout into Structure of Arrays (SoA), compiler auto-vectorization and algorithmic improvements in the particle sorting. We measure lower execution time and improved threading scalability both on Intel Xeon (2.6× on Ivy Bridge) and Xeon Phi (13.7× on Knights Corner) systems. First tests on second generation Xeon Phi (Knights Landing) demonstrate the portability of the devised optimization solutions to upcoming architectures.
An FPGA is a programmable logic device with a reconfigurable gate array logic circuits matrix.
To know more about “FPGA Design, Architecture and Applications,” click on the link https://www.logic-fruit.com/blog/fpga/fpga-design-architecture-and-applications/
About Logic Fruit Technologies
Logic Fruit Technologies is a product engineering R&D & consulting services provider for embedded systems and application development. We provide end-to-end solutions from the conception of the idea and design to the finished product. We have been servicing customers globally for over a decade.
The company has specific experience in various fields, such as
-FPGA Design & hardware design
-RTL IP Design
-A variety of digital protocols
-Communication buses as1G, 10G Ethernet
-PCIe
-DIGRF
-STM16/64
-HDMI.
Logic Fruit Technologies is also an expert in developing,
-software-defined radio (SDR) IPs
-Encryption
-Signal generation
-Data analysis, and
-Multiple Image Processing Techniques.
Recently Logic Fruit technologies are also exploring FPGA acceleration on data centers for real-time data processing.
**Our Social Media Channels**
Facebook: https://www.facebook.com/LogicFruit/
Twitter: https://twitter.com/logicfruit
LinkedIn: https://www.linkedin.com/company/logi…
Website: https://www.logic-fruit.com/
#LFT #LogicFruitTechnologies #LogicFruit
Interested to view more Slide Shares, Click on the below links,
https://www.slideshare.net/LogicFruit/a-designers-practical-guide-to-arinc-429-standard-3pptx
https://www.slideshare.net/LogicFruit/a-swift-introduction-to-milstd
https://www.slideshare.net/LogicFruit/arinc-the-ultimate-guide-to-modern-avionics-protocol/LogicFruit/arinc-the-ultimate-guide-to-modern-avionics-protocol
https://www.slideshare.net/LogicFruit/arinc-629-digital-data-bus-specifications/LogicFruit/arinc-629-digital-data-bus-specifications
https://www.slideshare.net/LogicFruit/afdx
https://www.slideshare.net/LogicFruit/end-system-design-parameters-of-the-arinc-664-part-7
https://www.slideshare.net/LogicFruit/compute-express-link-cxl-everything-you-ought-to-know
PPC64 Open ISA and A2I Core along with the PPC64 Open Hardware Notebook PCB and Libre-Soc project.
This year IBM released the A2I POWER processor core design and associated FPGA environment. In 2019 IBM opened the POWER Instruction Set Architecture (ISA). The Power Progress Community released the PCB of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. Libre-SOC is a software-hardware project that aims to deliver a physical POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR controller. We will discover these concrete projects.
Selective fitting strategy based real time placement algorithm for dynamicall...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Similar to The BondMachine Toolkit, enabling machine learning on FPGA (20)
Slides of the talk: "Machine Learning on FPGA: The BondMachine Project". Given at "IV International School on Open Science Cloud", 28 Nov - 2 Dec 2022 - Perugia - Italy
Harvesting dispersed computational resources with OpenstackMirko Mariotti
Harvesting dispersed computational resources is nowadays an important and strategic topic especially in an environment, like the computational science one, where computing needs constantly increase. On the other hand managing dispersed resources might not be neither an easy task not costly effective. We successfully explored the usage of OpenStack middleware to achieve this objective, aiming not only at harvesting resource but also at providing a modern paradigm of computing and data usage access. The deployment of a multi-sites Cloud implies the management of multiple computing services with the goal of sharing resources between more sites, allowing local data centers to scale out with external assets. The cited scenario immediately points out portability, interoperability and compatibility issues, but on the other side this opens really interesting scenarios and use cases especially in load balancing, disaster recovery and advanced features such as cross-site networks, cross-site storage systems, cross-site scheduling and placement of remote VMs. Moreover, a cloud infrastructure allows the exploitation of Platform as a Service, and software as a server solutions which in the end it is what really matter for the science. The main goal of the present work is to illustrate a real example on how to build a geographically distributed cloud to share and manage computing and storage resources, owned by heterogeneous cooperating entities. The sites are connected via a SDN technology through encrypted point-to-point channels being the “backbone” for the overlay networks. Specifically openVPN and IPsec have been used, depending on specific networking constraints. Over the point-to-point mesh, OSI L2 Ethernet frames of both the OpenStack management and projects VLAN networks have been encapsulated using the VXLAN protocol. The networking structure has been deployed for the specific purpose of creating a distributed overlay L2 Ethernet to be used by OpenStack. Finally, to fine tune the network setup and avoid cross site unnecessary traffic, different sites have been logically separated using different availability zones, with VMs on every zone having the capability of independently accessing the Internet through the site where they are physically running.
Pim - Un Esempio di integrazione AA dei servizi INFN/Universita'Mirko Mariotti
Slides presentate al Workshop CCR 2016 dell' Istituto Nazionale di Fisica Nucleare, riguardanti la progettazione e lo sviluppo del sistema di gestione dei servizi erogati dal Dipartimento di Fisica e Geologia dell'Universita' di Perugia e dalla locale sezione INFN.
Presentazione delle attivita' svolte utilizzando il sistema di virtualizzazione Xen nel dipartimento di fisica dell' universita' di Perugia fino al 2006.
Slide 1: Title Slide
Extrachromosomal Inheritance
Slide 2: Introduction to Extrachromosomal Inheritance
Definition: Extrachromosomal inheritance refers to the transmission of genetic material that is not found within the nucleus.
Key Components: Involves genes located in mitochondria, chloroplasts, and plasmids.
Slide 3: Mitochondrial Inheritance
Mitochondria: Organelles responsible for energy production.
Mitochondrial DNA (mtDNA): Circular DNA molecule found in mitochondria.
Inheritance Pattern: Maternally inherited, meaning it is passed from mothers to all their offspring.
Diseases: Examples include Leber’s hereditary optic neuropathy (LHON) and mitochondrial myopathy.
Slide 4: Chloroplast Inheritance
Chloroplasts: Organelles responsible for photosynthesis in plants.
Chloroplast DNA (cpDNA): Circular DNA molecule found in chloroplasts.
Inheritance Pattern: Often maternally inherited in most plants, but can vary in some species.
Examples: Variegation in plants, where leaf color patterns are determined by chloroplast DNA.
Slide 5: Plasmid Inheritance
Plasmids: Small, circular DNA molecules found in bacteria and some eukaryotes.
Features: Can carry antibiotic resistance genes and can be transferred between cells through processes like conjugation.
Significance: Important in biotechnology for gene cloning and genetic engineering.
Slide 6: Mechanisms of Extrachromosomal Inheritance
Non-Mendelian Patterns: Do not follow Mendel’s laws of inheritance.
Cytoplasmic Segregation: During cell division, organelles like mitochondria and chloroplasts are randomly distributed to daughter cells.
Heteroplasmy: Presence of more than one type of organellar genome within a cell, leading to variation in expression.
Slide 7: Examples of Extrachromosomal Inheritance
Four O’clock Plant (Mirabilis jalapa): Shows variegated leaves due to different cpDNA in leaf cells.
Petite Mutants in Yeast: Result from mutations in mitochondrial DNA affecting respiration.
Slide 8: Importance of Extrachromosomal Inheritance
Evolution: Provides insight into the evolution of eukaryotic cells.
Medicine: Understanding mitochondrial inheritance helps in diagnosing and treating mitochondrial diseases.
Agriculture: Chloroplast inheritance can be used in plant breeding and genetic modification.
Slide 9: Recent Research and Advances
Gene Editing: Techniques like CRISPR-Cas9 are being used to edit mitochondrial and chloroplast DNA.
Therapies: Development of mitochondrial replacement therapy (MRT) for preventing mitochondrial diseases.
Slide 10: Conclusion
Summary: Extrachromosomal inheritance involves the transmission of genetic material outside the nucleus and plays a crucial role in genetics, medicine, and biotechnology.
Future Directions: Continued research and technological advancements hold promise for new treatments and applications.
Slide 11: Questions and Discussion
Invite Audience: Open the floor for any questions or further discussion on the topic.
DERIVATION OF MODIFIED BERNOULLI EQUATION WITH VISCOUS EFFECTS AND TERMINAL V...Wasswaderrick3
In this book, we use conservation of energy techniques on a fluid element to derive the Modified Bernoulli equation of flow with viscous or friction effects. We derive the general equation of flow/ velocity and then from this we derive the Pouiselle flow equation, the transition flow equation and the turbulent flow equation. In the situations where there are no viscous effects , the equation reduces to the Bernoulli equation. From experimental results, we are able to include other terms in the Bernoulli equation. We also look at cases where pressure gradients exist. We use the Modified Bernoulli equation to derive equations of flow rate for pipes of different cross sectional areas connected together. We also extend our techniques of energy conservation to a sphere falling in a viscous medium under the effect of gravity. We demonstrate Stokes equation of terminal velocity and turbulent flow equation. We look at a way of calculating the time taken for a body to fall in a viscous medium. We also look at the general equation of terminal velocity.
Earliest Galaxies in the JADES Origins Field: Luminosity Function and Cosmic ...Sérgio Sacani
We characterize the earliest galaxy population in the JADES Origins Field (JOF), the deepest
imaging field observed with JWST. We make use of the ancillary Hubble optical images (5 filters
spanning 0.4−0.9µm) and novel JWST images with 14 filters spanning 0.8−5µm, including 7 mediumband filters, and reaching total exposure times of up to 46 hours per filter. We combine all our data
at > 2.3µm to construct an ultradeep image, reaching as deep as ≈ 31.4 AB mag in the stack and
30.3-31.0 AB mag (5σ, r = 0.1” circular aperture) in individual filters. We measure photometric
redshifts and use robust selection criteria to identify a sample of eight galaxy candidates at redshifts
z = 11.5 − 15. These objects show compact half-light radii of R1/2 ∼ 50 − 200pc, stellar masses of
M⋆ ∼ 107−108M⊙, and star-formation rates of SFR ∼ 0.1−1 M⊙ yr−1
. Our search finds no candidates
at 15 < z < 20, placing upper limits at these redshifts. We develop a forward modeling approach to
infer the properties of the evolving luminosity function without binning in redshift or luminosity that
marginalizes over the photometric redshift uncertainty of our candidate galaxies and incorporates the
impact of non-detections. We find a z = 12 luminosity function in good agreement with prior results,
and that the luminosity function normalization and UV luminosity density decline by a factor of ∼ 2.5
from z = 12 to z = 14. We discuss the possible implications of our results in the context of theoretical
models for evolution of the dark matter halo mass function.
(May 29th, 2024) Advancements in Intravital Microscopy- Insights for Preclini...Scintica Instrumentation
Intravital microscopy (IVM) is a powerful tool utilized to study cellular behavior over time and space in vivo. Much of our understanding of cell biology has been accomplished using various in vitro and ex vivo methods; however, these studies do not necessarily reflect the natural dynamics of biological processes. Unlike traditional cell culture or fixed tissue imaging, IVM allows for the ultra-fast high-resolution imaging of cellular processes over time and space and were studied in its natural environment. Real-time visualization of biological processes in the context of an intact organism helps maintain physiological relevance and provide insights into the progression of disease, response to treatments or developmental processes.
In this webinar we give an overview of advanced applications of the IVM system in preclinical research. IVIM technology is a provider of all-in-one intravital microscopy systems and solutions optimized for in vivo imaging of live animal models at sub-micron resolution. The system’s unique features and user-friendly software enables researchers to probe fast dynamic biological processes such as immune cell tracking, cell-cell interaction as well as vascularization and tumor metastasis with exceptional detail. This webinar will also give an overview of IVM being utilized in drug development, offering a view into the intricate interaction between drugs/nanoparticles and tissues in vivo and allows for the evaluation of therapeutic intervention in a variety of tissues and organs. This interdisciplinary collaboration continues to drive the advancements of novel therapeutic strategies.
Deep Behavioral Phenotyping in Systems Neuroscience for Functional Atlasing a...Ana Luísa Pinho
Functional Magnetic Resonance Imaging (fMRI) provides means to characterize brain activations in response to behavior. However, cognitive neuroscience has been limited to group-level effects referring to the performance of specific tasks. To obtain the functional profile of elementary cognitive mechanisms, the combination of brain responses to many tasks is required. Yet, to date, both structural atlases and parcellation-based activations do not fully account for cognitive function and still present several limitations. Further, they do not adapt overall to individual characteristics. In this talk, I will give an account of deep-behavioral phenotyping strategies, namely data-driven methods in large task-fMRI datasets, to optimize functional brain-data collection and improve inference of effects-of-interest related to mental processes. Key to this approach is the employment of fast multi-functional paradigms rich on features that can be well parametrized and, consequently, facilitate the creation of psycho-physiological constructs to be modelled with imaging data. Particular emphasis will be given to music stimuli when studying high-order cognitive mechanisms, due to their ecological nature and quality to enable complex behavior compounded by discrete entities. I will also discuss how deep-behavioral phenotyping and individualized models applied to neuroimaging data can better account for the subject-specific organization of domain-general cognitive systems in the human brain. Finally, the accumulation of functional brain signatures brings the possibility to clarify relationships among tasks and create a univocal link between brain systems and mental functions through: (1) the development of ontologies proposing an organization of cognitive processes; and (2) brain-network taxonomies describing functional specialization. To this end, tools to improve commensurability in cognitive science are necessary, such as public repositories, ontology-based platforms and automated meta-analysis tools. I will thus discuss some brain-atlasing resources currently under development, and their applicability in cognitive as well as clinical neuroscience.
Salas, V. (2024) "John of St. Thomas (Poinsot) on the Science of Sacred Theol...Studia Poinsotiana
I Introduction
II Subalternation and Theology
III Theology and Dogmatic Declarations
IV The Mixed Principles of Theology
V Virtual Revelation: The Unity of Theology
VI Theology as a Natural Science
VII Theology’s Certitude
VIII Conclusion
Notes
Bibliography
All the contents are fully attributable to the author, Doctor Victor Salas. Should you wish to get this text republished, get in touch with the author or the editorial committee of the Studia Poinsotiana. Insofar as possible, we will be happy to broker your contact.
Professional air quality monitoring systems provide immediate, on-site data for analysis, compliance, and decision-making.
Monitor common gases, weather parameters, particulates.
This presentation explores a brief idea about the structural and functional attributes of nucleotides, the structure and function of genetic materials along with the impact of UV rays and pH upon them.
The BondMachine Toolkit, enabling machine learning on FPGA
1. The BondMachine Toolkit
Enabling Machine Learning on FPGA
Mirko Mariotti
Department of Physics and Geology - University of Perugia
INFN Perugia
International Symposium on Grids & Clouds 2019 (ISGC 2019)
April 5, 2019
Academia Sinica - Taipei (TW)
2. Introduction
Introduction
The BondMachine Toolkit: Enabling Machine Learning on FPGA
In this presentation i will talk about:
Technological background of the project.
The BondMachine Project: architecture and tools.
BondMachine for Machine Learning.
Building accelerators and their use on the Cloud.
Conclusion.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 2/37
3. Introduction Programmable Logic
FPGA
What is it ?
A field-programmable gate array (FPGA) is an integrated circuit whose
logic is re-programmable. It’s used to build reconfigurable digital circuits.
FPGAs contain an array of programmable
logic blocks, and a hierarchy of reconfig-
urable interconnects that allow the blocks
to be wired together.
Logic blocks can be configured to perform
complex combinational functions.
The FPGA configuration is generally specified using a hardware
description language (HDL).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 3/37
4. Introduction Programmable Logic
FPGA
What is it ?
A field-programmable gate array (FPGA) is an integrated circuit whose
logic is re-programmable. It’s used to build reconfigurable digital circuits.
FPGAs contain an array of programmable
logic blocks, and a hierarchy of reconfig-
urable interconnects that allow the blocks
to be wired together.
Logic blocks can be configured to perform
complex combinational functions.
The FPGA configuration is generally specified using a hardware
description language (HDL).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 3/37
5. Introduction Programmable Logic
FPGA
What is it ?
A field-programmable gate array (FPGA) is an integrated circuit whose
logic is re-programmable. It’s used to build reconfigurable digital circuits.
FPGAs contain an array of programmable
logic blocks, and a hierarchy of reconfig-
urable interconnects that allow the blocks
to be wired together.
Logic blocks can be configured to perform
complex combinational functions.
The FPGA configuration is generally specified using a hardware
description language (HDL).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 3/37
6. Introduction Programmable Logic
FPGA
What is it ?
A field-programmable gate array (FPGA) is an integrated circuit whose
logic is re-programmable. It’s used to build reconfigurable digital circuits.
FPGAs contain an array of programmable
logic blocks, and a hierarchy of reconfig-
urable interconnects that allow the blocks
to be wired together.
Logic blocks can be configured to perform
complex combinational functions.
The FPGA configuration is generally specified using a hardware
description language (HDL).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 3/37
7. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
8. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
9. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
10. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
11. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
12. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
13. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
14. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
15. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
16. Introduction Architectures
Computer Architectures
Multi-core and Heterogeneous
Today’s computer architecture are:
Multi-core,Two or more independent actual processing units
execute multiple instructions at the same time.
The power is given by the number of cores.
Parallelism has to be addressed.
Heterogeneous, different types of processing units.
Cell, GPU, Parallela, TPU.
The power is given by the specialization.
The units data transfer has to be addressed.
The scheduling has to be addressed.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 4/37
17. BondMachine The Idea
The BondMachine
The idea
High level sources: Go, TensorFlow, NN
Building a new kind of computer architecture (multi-core and
heterogeneous both in cores types and interconnections) which
dynamically adapt to the specific computational problem rather than
be static.
BM architecture Layer
FPGA
Concurrency
and Special-
ization
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 5/37
18. BondMachine The Idea
The BondMachine
The idea
High level sources: Go, TensorFlow, NN
Building a new kind of computer architecture (multi-core and
heterogeneous both in cores types and interconnections) which
dynamically adapt to the specific computational problem rather than
be static.
BM architecture Layer
FPGA
Concurrency
and Special-
ization
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 5/37
19. BondMachine The Idea
The BondMachine
The idea
High level sources: Go, TensorFlow, NN
Building a new kind of computer architecture (multi-core and
heterogeneous both in cores types and interconnections) which
dynamically adapt to the specific computational problem rather than
be static.
BM architecture Layer
FPGA
Concurrency
and Special-
ization
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 5/37
20. BondMachine The Idea
The BondMachine
The idea
High level sources: Go, TensorFlow, NN
Building a new kind of computer architecture (multi-core and
heterogeneous both in cores types and interconnections) which
dynamically adapt to the specific computational problem rather than
be static.
BM architecture Layer
FPGA
Concurrency
and Special-
ization
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 5/37
21. BondMachine The Idea
The BondMachine
The idea
High level sources: Go, TensorFlow, NN
Building a new kind of computer architecture (multi-core and
heterogeneous both in cores types and interconnections) which
dynamically adapt to the specific computational problem rather than
be static.
BM architecture Layer
FPGA
Concurrency
and Special-
ization
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 5/37
22. BondMachine Architecture
Introducing the BondMachine (BM)
The BondMachine is a software ecosystem for the dynamic generation
of computer architectures that:
Are composed by many, possibly hundreds, computing cores.
Have very small cores and not necessarily of the same type
(different ISA and ABI).
Have a not fixed way of interconnecting cores.
May have some elements shared among cores (for example channels
and shared memories).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 6/37
23. BondMachine Architecture
Introducing the BondMachine (BM)
The BondMachine is a software ecosystem for the dynamic generation
of computer architectures that:
Are composed by many, possibly hundreds, computing cores.
Have very small cores and not necessarily of the same type
(different ISA and ABI).
Have a not fixed way of interconnecting cores.
May have some elements shared among cores (for example channels
and shared memories).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 6/37
24. BondMachine Architecture
Introducing the BondMachine (BM)
The BondMachine is a software ecosystem for the dynamic generation
of computer architectures that:
Are composed by many, possibly hundreds, computing cores.
Have very small cores and not necessarily of the same type
(different ISA and ABI).
Have a not fixed way of interconnecting cores.
May have some elements shared among cores (for example channels
and shared memories).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 6/37
25. BondMachine Architecture
Introducing the BondMachine (BM)
The BondMachine is a software ecosystem for the dynamic generation
of computer architectures that:
Are composed by many, possibly hundreds, computing cores.
Have very small cores and not necessarily of the same type
(different ISA and ABI).
Have a not fixed way of interconnecting cores.
May have some elements shared among cores (for example channels
and shared memories).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 6/37
26. BondMachine Architecture
Introducing the BondMachine (BM)
The BondMachine is a software ecosystem for the dynamic generation
of computer architectures that:
Are composed by many, possibly hundreds, computing cores.
Have very small cores and not necessarily of the same type
(different ISA and ABI).
Have a not fixed way of interconnecting cores.
May have some elements shared among cores (for example channels
and shared memories).
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 6/37
28. BondMachine Connecting Processors
Connecting Processor (CP)
The computational unit of the BM
The atomic computational unit of a BM is the “connecting processor”
(CP) and has:
Some general purpose registers of size Rsize.
Some I/O dedicated registers of size Rsize.
A set of implemented opcodes chosen among many available.
Dedicated ROM and RAM.
There possible operating modes.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 8/37
29. BondMachine Connecting Processors
Connecting Processor (CP)
The computational unit of the BM
The atomic computational unit of a BM is the “connecting processor”
(CP) and has:
Some general purpose registers of size Rsize.
Some I/O dedicated registers of size Rsize.
A set of implemented opcodes chosen among many available.
Dedicated ROM and RAM.
There possible operating modes.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 8/37
30. BondMachine Connecting Processors
Connecting Processor (CP)
The computational unit of the BM
The atomic computational unit of a BM is the “connecting processor”
(CP) and has:
Some general purpose registers of size Rsize.
Some I/O dedicated registers of size Rsize.
A set of implemented opcodes chosen among many available.
Dedicated ROM and RAM.
There possible operating modes.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 8/37
31. BondMachine Connecting Processors
Connecting Processor (CP)
The computational unit of the BM
The atomic computational unit of a BM is the “connecting processor”
(CP) and has:
Some general purpose registers of size Rsize.
Some I/O dedicated registers of size Rsize.
A set of implemented opcodes chosen among many available.
Dedicated ROM and RAM.
There possible operating modes.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 8/37
32. BondMachine Connecting Processors
Connecting Processor (CP)
The computational unit of the BM
The atomic computational unit of a BM is the “connecting processor”
(CP) and has:
Some general purpose registers of size Rsize.
Some I/O dedicated registers of size Rsize.
A set of implemented opcodes chosen among many available.
Dedicated ROM and RAM.
There possible operating modes.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 8/37
33. BondMachine Connecting Processors
Connecting Processor (CP)
The computational unit of the BM
The atomic computational unit of a BM is the “connecting processor”
(CP) and has:
Some general purpose registers of size Rsize.
Some I/O dedicated registers of size Rsize.
A set of implemented opcodes chosen among many available.
Dedicated ROM and RAM.
There possible operating modes.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 8/37
34. BondMachine Shared Objects
Shared Objects (SO)
The non-computational element of the BM
Alongside CPs, BondMachines include non-computing units called
“Shared Objects” (SO).
Examples of their purposes are:
Data storage (Memories).
Message passing.
CP synchronization.
A single SO can be shared among different CPs. To use it CPs have
special instructions (opcodes) oriented to the specific SO.
Four kind of SO have been developed so far: the Channel, the
Shared Memory, the Barrier and a Pseudo Random Numbers Gen-
erator.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 9/37
35. BondMachine Shared Objects
Shared Objects (SO)
The non-computational element of the BM
Alongside CPs, BondMachines include non-computing units called
“Shared Objects” (SO).
Examples of their purposes are:
Data storage (Memories).
Message passing.
CP synchronization.
A single SO can be shared among different CPs. To use it CPs have
special instructions (opcodes) oriented to the specific SO.
Four kind of SO have been developed so far: the Channel, the
Shared Memory, the Barrier and a Pseudo Random Numbers Gen-
erator.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 9/37
36. BondMachine Shared Objects
Shared Objects (SO)
The non-computational element of the BM
Alongside CPs, BondMachines include non-computing units called
“Shared Objects” (SO).
Examples of their purposes are:
Data storage (Memories).
Message passing.
CP synchronization.
A single SO can be shared among different CPs. To use it CPs have
special instructions (opcodes) oriented to the specific SO.
Four kind of SO have been developed so far: the Channel, the
Shared Memory, the Barrier and a Pseudo Random Numbers Gen-
erator.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 9/37
37. BondMachine Shared Objects
Shared Objects (SO)
The non-computational element of the BM
Alongside CPs, BondMachines include non-computing units called
“Shared Objects” (SO).
Examples of their purposes are:
Data storage (Memories).
Message passing.
CP synchronization.
A single SO can be shared among different CPs. To use it CPs have
special instructions (opcodes) oriented to the specific SO.
Four kind of SO have been developed so far: the Channel, the
Shared Memory, the Barrier and a Pseudo Random Numbers Gen-
erator.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 9/37
38. BondMachine Shared Objects
Shared Objects (SO)
The non-computational element of the BM
Alongside CPs, BondMachines include non-computing units called
“Shared Objects” (SO).
Examples of their purposes are:
Data storage (Memories).
Message passing.
CP synchronization.
A single SO can be shared among different CPs. To use it CPs have
special instructions (opcodes) oriented to the specific SO.
Four kind of SO have been developed so far: the Channel, the
Shared Memory, the Barrier and a Pseudo Random Numbers Gen-
erator.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 9/37
39. BondMachine Shared Objects
Shared Objects (SO)
The non-computational element of the BM
Alongside CPs, BondMachines include non-computing units called
“Shared Objects” (SO).
Examples of their purposes are:
Data storage (Memories).
Message passing.
CP synchronization.
A single SO can be shared among different CPs. To use it CPs have
special instructions (opcodes) oriented to the specific SO.
Four kind of SO have been developed so far: the Channel, the
Shared Memory, the Barrier and a Pseudo Random Numbers Gen-
erator.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 9/37
40. BondMachine Tools
Handle the BM computer architecture
The BM computer architecture is managed by a set of tools to:
build a specify architecture
modify a pre-existing architecture
simulate or emulate the behavior
Generate the Register Tranfer Code (RTL)
Processor Builder
Selects the single pro-
cessor, assembles and
disassembles, saves on
disk as JSON, creates
the RTL code of a CP
BondMachine Builder
Connects CPs and SOs
together in custom
topologies, loads and
saves on disk as JSON,
create BM’s RTL code
Simulation Framework
Simulates the be-
haviour, emulates a
BM on a standard
Linux workstation
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 10/37
41. BondMachine Tools
Handle the BM computer architecture
The BM computer architecture is managed by a set of tools to:
build a specify architecture
modify a pre-existing architecture
simulate or emulate the behavior
Generate the Register Tranfer Code (RTL)
Processor Builder
Selects the single pro-
cessor, assembles and
disassembles, saves on
disk as JSON, creates
the RTL code of a CP
BondMachine Builder
Connects CPs and SOs
together in custom
topologies, loads and
saves on disk as JSON,
create BM’s RTL code
Simulation Framework
Simulates the be-
haviour, emulates a
BM on a standard
Linux workstation
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 10/37
42. BondMachine Tools
Handle the BM computer architecture
The BM computer architecture is managed by a set of tools to:
build a specify architecture
modify a pre-existing architecture
simulate or emulate the behavior
Generate the Register Tranfer Code (RTL)
Processor Builder
Selects the single pro-
cessor, assembles and
disassembles, saves on
disk as JSON, creates
the RTL code of a CP
BondMachine Builder
Connects CPs and SOs
together in custom
topologies, loads and
saves on disk as JSON,
create BM’s RTL code
Simulation Framework
Simulates the be-
haviour, emulates a
BM on a standard
Linux workstation
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 10/37
43. BondMachine Tools
Handle the BM computer architecture
The BM computer architecture is managed by a set of tools to:
build a specify architecture
modify a pre-existing architecture
simulate or emulate the behavior
Generate the Register Tranfer Code (RTL)
Processor Builder
Selects the single pro-
cessor, assembles and
disassembles, saves on
disk as JSON, creates
the RTL code of a CP
BondMachine Builder
Connects CPs and SOs
together in custom
topologies, loads and
saves on disk as JSON,
create BM’s RTL code
Simulation Framework
Simulates the be-
haviour, emulates a
BM on a standard
Linux workstation
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 10/37
44. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
45. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
46. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
47. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
48. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
49. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
50. Moulding API and Libraries
Use the BM computer architecture
Mapping specific computational problems to BMs
Symbond
Map symbolic
mathematical
expressions to BM
Boolbond
Map boolean systems
to BM
Matrixwork
Basic matrix
computation
Evolutive BM
Evolutionary
computing to BM
Neuralbond
Map neural networks
to BM
tf2bm nnef2bm
Map computational
graphs to BM
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 11/37
51. Moulding Bondgo
Bondgo
The major innovation of the BondMachine Project is its compiler.
Bondgo is the name chosen for the compiler developed for the
BondMachine.
The compiler source language is Go as the name suggest.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 12/37
52. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
53. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
high level GO source
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
54. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
high level GO source
assembly file
Compiling
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
55. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
high level GO source
assembly file
Compiling
CP specs
Arch generating
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
56. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
high level GO source
assembly file
Compiling
CP specs
Arch generating
machine code
Assembling
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
57. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
high level GO source
assembly file
Compiling
CP specs
Arch generating
machine code
Assembling
Processor implementation
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
58. Moulding Bondgo
Bondgo
Bondgo does something different from standard compilers ...
high level GO source
assembly file
Compiling
CP specs
Arch generating
machine code
Assembling
Processor implementation
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 13/37
59. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
60. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
61. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
62. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
63. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
64. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
65. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
66. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
67. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
68. Moulding Bondgo
Bondgo
A first example
counter go source
package main
import (
bondgo
)
func main () {
var outgoing bondgo.Output
var reg_int uint8
outgoing =
bondgo.Make(bondgo.Output , 3)
reg_int = 0
for {
bondgo.IOWrite(outgoing ,
reg_int)
reg_int ++
}
}
bondgo –input-file counter.go
-mpm
BM JSON rapresentation
counter asm
clr r0
rset r1 0
cpy r0 r1
cpy r1 r0
r2o r1 o0
inc r0
j 3
bondmachine tool
BM HDL code
FPGA
procbuilder tool
Binary
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 14/37
69. Moulding Bondgo
Bondgo
... bondgo may not only create the binaries, but also the CP
architecture, and ...
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 15/37
70. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
71. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
high level GO source
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
72. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
high level GO source
assembly CP 1
assembly CP 2
assembly CP 3
assembly CP 4
assembly CP ...
assembly CP N
Compiling
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
73. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
high level GO source
assembly CP 1
assembly CP 2
assembly CP 3
assembly CP 4
assembly CP ...
assembly CP N
Compiling
CP 1 specs
CP 2
CP 3
CP 4
CP ...
CP N
Archs generating
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
74. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
high level GO source
assembly CP 1
assembly CP 2
assembly CP 3
assembly CP 4
assembly CP ...
assembly CP N
Compiling
CP 1 specs
CP 2
CP 3
CP 4
CP ...
CP N
Archs generating
Asm and Binaries
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
75. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
high level GO source
assembly CP 1
assembly CP 2
assembly CP 3
assembly CP 4
assembly CP ...
assembly CP N
Compiling
CP 1 specs
CP 2
CP 3
CP 4
CP ...
CP N
Archs generating
Asm and Binaries
Interconnections
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
76. Moulding Bondgo
Bondgo
... it can do even much more interesting things when compiling
concurrent programs.
high level GO source
assembly CP 1
assembly CP 2
assembly CP 3
assembly CP 4
assembly CP ...
assembly CP N
Compiling
CP 1 specs
CP 2
CP 3
CP 4
CP ...
CP N
Archs generating
Asm and Binaries
BondMachine
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 16/37
78. Moulding Bondgo
Compiling Architectures
One of the most important result
The architecture creation is a part of the compilation process.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 18/37
79. Machine Learning with BondMachine
Machine Learning with BondMachine
Architectures with multiple interconnected processors like the ones
produced by the BondMachine Toolkit are a perfect fit for Neural
Networks and Computational Graphs.
Several ways to map this structures to BondMachine has been
developed:
A native Neural Network library
A Tensorflow to BondMachine translator
An NNEF based BondMachine composer
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 19/37
80. Machine Learning with BondMachine
Machine Learning with BondMachine
Architectures with multiple interconnected processors like the ones
produced by the BondMachine Toolkit are a perfect fit for Neural
Networks and Computational Graphs.
Several ways to map this structures to BondMachine has been
developed:
A native Neural Network library
A Tensorflow to BondMachine translator
An NNEF based BondMachine composer
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 19/37
81. Machine Learning with BondMachine Bondmachine native Neural Network library
Machine Learning with BondMachine
Native Neural Network library
The tool neuralbond allow the creation of BM-based neural chips from
an API go interface.
Neurons are converted to BondMachine connecting processors.
Tensors are mapped to CP connections.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 20/37
82. Machine Learning with BondMachine TensorFlow to Bondmachine
TensorFlow™ to Bondmachine
tf2bm
TensorFlow™ is an open source software library for numerical
computation using data flow graphs.
Graphs can be converted to BondMachines with the tf2bm tool.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 21/37
83. Machine Learning with BondMachine NNEF Composer
Machine Learning with BondMachine
NNEF Composer
Neural Network Exchange Format (NNEF) is a standard from Khronos
Group to enable the easy transfer of trained networks among
frameworks, inference engines and devices
The NNEF BM tool approach is to descent NNEF models and build
BondMachine multi-core accordingly
This approch has several advandages over the previous:
It is not limited to a single framework
NNEF is a textual file, so no complex operations are needed to
read models
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 22/37
84. Clustering
BondMachine Clustering
So far we saw:
An user friendly approach to create processors (single core).
Optimizing a single device to support intricate computational
work-flows (multi-cores) over an heterogeneous layer.
Interconnected BondMachines
What if we could extend the this layer to multiple interconnected
devices ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 23/37
85. Clustering
BondMachine Clustering
So far we saw:
An user friendly approach to create processors (single core).
Optimizing a single device to support intricate computational
work-flows (multi-cores) over an heterogeneous layer.
Interconnected BondMachines
What if we could extend the this layer to multiple interconnected
devices ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 23/37
86. Clustering
BondMachine Clustering
So far we saw:
An user friendly approach to create processors (single core).
Optimizing a single device to support intricate computational
work-flows (multi-cores) over an heterogeneous layer.
Interconnected BondMachines
What if we could extend the this layer to multiple interconnected
devices ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 23/37
87. Clustering
BondMachine Clustering
So far we saw:
An user friendly approach to create processors (single core).
Optimizing a single device to support intricate computational
work-flows (multi-cores) over an heterogeneous layer.
Interconnected BondMachines
What if we could extend the this layer to multiple interconnected
devices ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 23/37
88. Clustering
BondMachine Clustering
The same logic existing among CP have been extended among different
BondMachines organized in clusters.
Protocols, one ethernet called etherbond and one using UDP called
udpbond have been created for the purpose.
FPGA based BondMachines, standard Linux Workstations, Emulated
BondMachines might join a cluster an contribute to a single distributed
computational problem.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 24/37
89. Clustering
BondMachine Clustering
The same logic existing among CP have been extended among different
BondMachines organized in clusters.
Protocols, one ethernet called etherbond and one using UDP called
udpbond have been created for the purpose.
FPGA based BondMachines, standard Linux Workstations, Emulated
BondMachines might join a cluster an contribute to a single distributed
computational problem.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 24/37
90. Clustering
BondMachine Clustering
The same logic existing among CP have been extended among different
BondMachines organized in clusters.
Protocols, one ethernet called etherbond and one using UDP called
udpbond have been created for the purpose.
FPGA based BondMachines, standard Linux Workstations, Emulated
BondMachines might join a cluster an contribute to a single distributed
computational problem.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 24/37
92. Clustering
BondMachine Clustering
Results
Results
User can deploy an entire HW/SW cluster starting from code
written in a high level description (Go, NNEF, etc)
Workstation with emulated BondMachines, workstation with
etherbond drivers, standalone BondMachines (FPGA) may join
these clusters.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 26/37
93. Clustering
BondMachine Clustering
Results
Results
User can deploy an entire HW/SW cluster starting from code
written in a high level description (Go, NNEF, etc)
Workstation with emulated BondMachines, workstation with
etherbond drivers, standalone BondMachines (FPGA) may join
these clusters.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 26/37
94. Uses
Use cases
Two use cases in Physics experiments are currently being developed:
Real time pulse shape analysis in neutron detectors
bringing the intelligence to the edge
Test beam for space experiments (DAMPE, HERD)
increasing testbed operations efficiency
Computing Accelerator
Our effort is now in enabling the possibility of building computing
accelerators to be used from within standard (Linux) applications.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 27/37
95. Uses
Use cases
Two use cases in Physics experiments are currently being developed:
Real time pulse shape analysis in neutron detectors
bringing the intelligence to the edge
Test beam for space experiments (DAMPE, HERD)
increasing testbed operations efficiency
Computing Accelerator
Our effort is now in enabling the possibility of building computing
accelerators to be used from within standard (Linux) applications.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 27/37
96. Uses
Accelerators
Types
We are currently working to enable the use the BM as accelerator in
two directions:
Using standard processor/FPGA hybrid chips
Zynq, Cyclone V
Using PCI-express FPGA evaluation boards
Kintek 7 Evaluation board
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 28/37
107. Uses
Accelerators
Cloud
FPGA accelerators can be used in the cloud:
Several public cloud providers offers solution of VM connected to
FPGAs (Amazon, Nimbix)
FPGAs can be inserted in private clouds infrastructures
To be used a firmware has to be uploaded to the accelerated VM FPGA
The BondMachine toolkit can be used to build such firmware
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 32/37
108. Uses
Accelerators
Cloud
FPGA accelerators can be used in the cloud:
Several public cloud providers offers solution of VM connected to
FPGAs (Amazon, Nimbix)
FPGAs can be inserted in private clouds infrastructures
To be used a firmware has to be uploaded to the accelerated VM FPGA
The BondMachine toolkit can be used to build such firmware
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 32/37
109. Uses
Accelerators
Cloud
FPGA accelerators can be used in the cloud:
Several public cloud providers offers solution of VM connected to
FPGAs (Amazon, Nimbix)
FPGAs can be inserted in private clouds infrastructures
To be used a firmware has to be uploaded to the accelerated VM FPGA
The BondMachine toolkit can be used to build such firmware
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 32/37
110. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
111. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
112. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
113. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
114. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
115. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
116. Uses
Accelerated ML in the Cloud
Neural Network API TF2BM NNEF
BM firmware
Prebuild BM
firmware
library
FPGA enabled
VM
BM
hw
deploy
BM
sw
deploy
Accelerated VM
Application
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 33/37
117. Project History
Project History
May 2016 - First tests on the idea.
October 2016 - Prototype at “Makerfaire 2016 Rome”
Jul 2018 - InnovateFPGA EMEA Silver Award.
Aug 2018 - Presented at Intel Campus, Santa Jose (CA) .
Aug 2018 - InnovateFPGA Iron Award in the Grand Final.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 34/37
118. Conclusions
Conclusions
The BondMachine is a new kind of computing device made possible in
practice only by the emerging of new re-programmable hardware technologies
such as FPGA.
The result of this process is the construction of a computer architecture that
is not anymore a static constraint where computing occurs but its creation
becomes a part of the computing process, gaining computing power and
flexibility.
Over this abstraction is it possible to create a full computing Ecosystem,
ranging from small interconnected IoT devices to Machine Learning
accelerators.
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 35/37
119. Future work
Future work
The project is at the stage of a working prototype, so work has to be
done in several areas:
Include new processor shared objects and currently unsupported
opcodes.
Extend the compiler to include more data structures.
Improve the networking including new interconnection firmwares.
Work on BondMachine as accelerators.
What would an OS for BondMachines look like ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 36/37
120. Future work
Future work
The project is at the stage of a working prototype, so work has to be
done in several areas:
Include new processor shared objects and currently unsupported
opcodes.
Extend the compiler to include more data structures.
Improve the networking including new interconnection firmwares.
Work on BondMachine as accelerators.
What would an OS for BondMachines look like ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 36/37
121. Future work
Future work
The project is at the stage of a working prototype, so work has to be
done in several areas:
Include new processor shared objects and currently unsupported
opcodes.
Extend the compiler to include more data structures.
Improve the networking including new interconnection firmwares.
Work on BondMachine as accelerators.
What would an OS for BondMachines look like ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 36/37
122. Future work
Future work
The project is at the stage of a working prototype, so work has to be
done in several areas:
Include new processor shared objects and currently unsupported
opcodes.
Extend the compiler to include more data structures.
Improve the networking including new interconnection firmwares.
Work on BondMachine as accelerators.
What would an OS for BondMachines look like ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 36/37
123. Future work
Future work
The project is at the stage of a working prototype, so work has to be
done in several areas:
Include new processor shared objects and currently unsupported
opcodes.
Extend the compiler to include more data structures.
Improve the networking including new interconnection firmwares.
Work on BondMachine as accelerators.
What would an OS for BondMachines look like ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 36/37
124. Future work
Future work
The project is at the stage of a working prototype, so work has to be
done in several areas:
Include new processor shared objects and currently unsupported
opcodes.
Extend the compiler to include more data structures.
Improve the networking including new interconnection firmwares.
Work on BondMachine as accelerators.
What would an OS for BondMachines look like ?
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 36/37
125. Future work
If you have question/curiosity on the project:
Mirko Mariotti
mirko.mariotti@unipg.it
http://bondmachine.fisica.unipg.it
Mirko Mariotti The BondMachine Toolkit ISGC 2019 - Academia Sinica - Taipei 37/37