This document summarizes the PSpice model parameters and simulation results for a TC75S59FE voltage comparator chip made by Toshiba. It describes the model parameters, provides circuit diagrams used in simulations, shows simulation waveforms, and compares the simulation results to measurement values for various specifications like output low voltage, propagation delay time, input bias current, and voltage gain. The simulations matched the measurement values closely with less than 3.5% error for all tested specifications.

1. Device Modeling Report
COMPONENTS : VOLTAGE COMPARATOR (CMOS)
PART NUMBER : TC75S59FE
MANUFACTURER : TOSHIBA
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

2. MODEL PARAMETER
Pspice model
Model description
parameter
LEVEL
L Channel Length
W Channel Width
KP Transconductance
RS Source Ohmic Resistance
RD Ohmic Drain Resistance
VTO Zero-bias Threshold Voltage
RDS Drain-Source Shunt Resistance
TOX Gate Oxide Thickness
CGSO Zero-bias Gate-Source Capacitance
CGDO Zero-bias Gate-Drain Capacitance
CBD Zero-bias Bulk-Drain Junction Capacitance
MJ Bulk Junction Grading Coefficient
PB Bulk Junction Potential
FC Bulk Junction Forward-bias Capacitance Coefficient
RG Gate Ohmic Resistance
IS Bulk Junction Saturation Current
N Bulk Junction Emission Coefficient
RB Bulk Series Resistance
PHI Surface Inversion Potential
GAMMA Body-effect Parameter
DELTA Width effect on Threshold Voltage
ETA Static Feedback on Threshold Voltage
THETA Modility Modulation
KAPPA Saturation Field Factor
VMAX Maximum Drift Velocity of Carriers
XJ Metallurgical Junction Depth
UO Surface Mobility
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

3. Output Low Voltage
Simulation result
Simulation
Evaluation Circuit
VDD VOUT
Vol
- + U1
TC75S59F
V2 VIN- VSS VIN+ I1
5
V1 5m
1
0
Comparison Table
Isink=5mA Measurement Simulation %Error
Vol (V) 0.1 0.097472 -2.528
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

4. Output Sink Current
Simulation result
Simulation
Evaluation Circuit
VDD VOUT
- + U2
TC75S59F
VIN- VSS VIN+
5 V3 Vsink
0.5
V4
1
0
Comparison Table
VOL = 0.5 V Measurement Simulation %Error
Isink (mA) 25 24.375 -2.50
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

5. Propagation Delay Time and Response Time
Simulation result
Simulation
Evaluation Circuit
VDD VOUT
OUTPUT
R1
1
- + U1 10k
TC75S59F
V1
VIN- VSS VIN+ 1
5
V1 = -100m
V4 V2 = 100m
TD = 1u
TR = 10n
TF = 10n
PW = 5u
PER = 10u
0
Comparison Table
Over drive=100mV Measurement Simulation %Error
tPLH (ns) 200 193.856 -3.072
tPHL (ns) 80 81.214 1.518
tr (ns) 160 159.177 -0.514
tf (ns) 3 2.9152 -2.827
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

6. Input Bias Current and Input Offset Current Characteristics
Simulation result
Ib
Ios
Evaluation Circuit
VDD VOUT
- + U3
V3 TC75S59F
5
VIN- VSS VIN+ R1
1k
V2 V1
0
0
0
Comparison Table
Measurement Simulation %Error
Ib (pA) 1 1 0
Ios(pA) 1 1 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

7. Input Offset Voltage Characteristics
Simulation result
Simulation
Evaluation Circuit
VDD VOUT
OUTPUT
R1
1 - + U3
TC75S59F 10k
VIN- VSS VIN+
V3 1
5
V1
0
0
Comparison Table
Measurement Simulation %Error
Vio(mV) 1 1.005 0.5
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

8. Voltage Gain Characteristics
Simulation result
Simulation
Evaluation Circuit
OUTPUT
VDD VOUT
R1
1 10k
- + U1
V3 1
TC75S59F
5
VIN- VSS VIN+
IN
V1 VOFF = 1.005m
VAMPL = 0
FREQ = 0
AC = 1m
0
Comparison Table
Measurement Simulation %Error
Av (dB) 94 94.05 0.053
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005