Download to read offline
More Related Content
Similar to Story behind Microelectronic Circuits
Story behind Microelectronic Circuits
- 1. Monday, 13 July2020. 10:37am 15/7/2020 arXiv is a free distribution service and an open-access archive for 1,732,191 scholarly articles in the fields of physics, mathematics, computer science, quantitative biology, quantitative finance, statistics, electrical engineering and systems science, and economics. Materials on this site are not peer- reviewed by arXiv. https://arxiv.org/ Open course ware VLSI https://ocw.tudelft.nl/courses/vlsi-test-technology-reliabillity/ 17/7/2020 The story behind Microelectronic Circuits https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5325492 18/7/2020 A free, AI-powered research tool for scientific literature https://www.semanticscholar.org/ 22/7/2020 Prabook is meant to preserve information about people. And it is done by people. https://prabook.com/web/home.html 25/7/2020 ECEN 474/704 Lab 1: Introduction to Cadence & MOS Device Characterization http://www.ece.tamu.edu/~spalermo/ecen474/Lab1.pdf ECEN 474/704 Lab 2: Layout Design http://www.ece.tamu.edu/~spalermo/ecen474/Lab2.pdf ECEN 474/704 Lab 3: Advanced Layout Techniques http://www.ece.tamu.edu/~spalermo/ecen474/Lab3.pdf ECEN 474/704 Lab 4: Current Mirrors http://www.ece.tamu.edu/~spalermo/ecen474/Lab4.pdf ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier http://www.ece.tamu.edu/~spalermo/ecen474/Lab8.pdf ECEN 474 layout http://ece.tamu.edu/~spalermo/ecen474/lecture05_ee474_layout.pdf What should neuromorphic computing architectures be like? https://si2.epfl.ch/~demichel/si.epfl.ch/page-132659-en.html Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design https://www.researchgate.net/publication/340880469_Gaussian-Process- Based_Surrogate_for_Optimization-Aided_and_Process-Variations-Aware_Analog_Circuit_Design
- 2. Monday, 13 July2020. 10:37am Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions https://www.researchgate.net/publication/342363919_Sizing_CMOS_Amplifiers_by_PSO_and_MOL _to_Improve_DC_Operating_Point_Conditions 26/7/2020 How About a Faster Fast SPICE? Much Faster! https://semiwiki.com/eda/288711-how-about-a-faster-fast-spice-much-faster/ Analog FastSPICE (AFS) Platform https://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/analog- fastspice-platform 4/8/2020 Cleanroom at Electrical and Computer engineering department, Brigham Young University https://cleanroom.byu.edu/ MOSFET Calculator https://cleanroom.byu.edu/mosfet_calc MOSIS EDUCATIONAL RUN REPORT Name of students involved in the project Antonio F Mondragon- Torres, Area used 25mm2, Technology (foundry, size, technology code, description) TSMC 0.35um SCN4ME_SUBM T13Q-AQ, Advisor Dr. Edgar Sanchez-Sinencio https://www.mosis.com/files/research/texas_am_univ/report&proposal_62050.pdf an analog integrated circuit design laboratory at tamu https://www.yumpu.com/en/document/read/31237020/an-analog-integrated-circuit-design- laboratory-texas-am-university ANALOG & MIXED SIGNAL CENTER (amsc.tamu.edu) https://www.yumpu.com/user/amsc.tamu.edu 7/8/2020 HSPICE - Ananlog SPICE Simulation (different CMOS technology models) https://www.vtvt.ece.vt.edu/tutorial/tutorialSynopsys_hspice.php Selecting a MOSFET Model https://class.ece.uw.edu/cadta/hspice/chapter_16.pdf 11/8/2020 A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS https://ieeexplore.ieee.org/abstract/document/9136747 Analog and Mixed-Signal Center http://amsc.tamu.edu/amsc/amsc.pdf 16/8/2020 AMS Laurea Institutional Theses Repository https://amslaurea.unibo.it/ 27/8/2020
- 3. Monday, 13 July2020. 10:37am Machine Learning-Based Approach for Hardware Faults Prediction https://ieeexplore.ieee.org/document/9162469/ Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies: With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well. https://www.researchgate.net/publication/221341207_Emerging_Yield_and_Reliability_Challenges_ in_Nanometer_CMOS_Technologies Jaya a novel optimization algorithm: What, how and why? This paper presents a comprehensive discussion of the Jaya algorithm, a novel approach for the optimization. There exist two broad categories of heuristic algorithms are: evolutionary algorithms and swarm intelligence. These algorithms' performance vastly depends on the parameters used need extensive tuning during the computational experiments to achieve the superior performance. The Jaya algorithm is a new optimization algorithm has been proposed recently is parameter less and therefore parameters tuning is not needed for it. The primary aim of this paper is to discuss the Jaya algorithm based on the rational aspects outlined as: (a) what is Jaya algorithm; (b) How it works and (c) why one should use it. The author believes that this discussion might be useful to explore the potential of the Jaya to the general audience working for the optimization. An advanced optimization algorithm called Jaya (a Sanskrit word meaning victory) https://sites.google.com/site/jayaalgorithm/ Jaya: An Advanced Optimization Algorithm and Its Engineering Applications by Venkata Rao, R. https://www.springer.com/gp/book/9783319789217 Tutorial: Analog Artist with HSPICE https://ece.northeastern.edu/courses/eece7353/2020sp/Cadence/Analog_Artist_with_HSPICE.pdf https://ece.northeastern.edu/courses/eece7353/2020sp/ https://ece.northeastern.edu/courses/eece7353/2020sp/cadence_manual.pdf 9/2/2020 Virtuoso Layout Rice University https://www.clear.rice.edu/elec522/w9/virtuoso_layout/ Cadence at Rice ECE University https://eceweb.rice.edu/undergraduate-study/resources/cadence A Creative Path Towards Becoming Female Engineer Enabling the Next Opportunities in Computing https://link.springer.com/chapter/10.1007/978-3-030-46377-9_11 Statistical modeling for computer-aided design of analog MOS integrated circuits https://etd.ohiolink.edu/!etd.send_file?accession=osu1487688973683252&disposition=inline search for papers (CMOS EEG) http://eds.b.ebscohost.com.uoseresources.remotexs.xyz/eds/results?vid=3&sid=f1825098-a3ae- 4205-a580-e81e27ba87f5%40pdc-v-